2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
41 #ifndef CONFIG_FEC_XCV_TYPE
42 #define CONFIG_FEC_XCV_TYPE MII100
46 * The i.MX28 operates with packets in big endian. We need to swap them before
47 * sending and after receiving.
50 #define CONFIG_FEC_MXC_SWAP_PACKET
53 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
55 /* Check various alignment issues at compile time */
56 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
57 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
60 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
61 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
62 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
68 uint8_t data[1500]; /**< actual data */
69 int length; /**< actual length */
70 int used; /**< buffer in use or not */
71 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
76 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
77 static void swap_packet(uint32_t *packet, int length)
81 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
82 packet[i] = __swab32(packet[i]);
87 * MII-interface related functions
89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
92 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
101 writel(FEC_IEVENT_MII, ð->ievent);
102 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
106 phy | reg, ð->mii_data);
109 * wait for the related interrupt
111 start = get_timer(0);
112 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
113 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
114 if (readl(ð->ievent) & FEC_IEVENT_MII)
116 printf("Read MDIO failed...\n");
122 * clear mii interrupt bit
124 writel(FEC_IEVENT_MII, ð->ievent);
127 * it's now safe to read the PHY's register
129 val = (unsigned short)readl(ð->mii_data);
130 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
135 static void fec_mii_setspeed(struct fec_priv *fec)
138 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
139 * and do not drop the Preamble.
141 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
142 &fec->eth->mii_speed);
143 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
146 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
147 uint8_t regAddr, uint16_t data)
149 uint32_t reg; /* convenient holder for the PHY register */
150 uint32_t phy; /* convenient holder for the PHY */
153 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
154 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
156 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
157 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
160 * wait for the MII interrupt
162 start = get_timer(0);
163 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
164 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
165 if (readl(ð->ievent) & FEC_IEVENT_MII)
167 printf("Write MDIO failed...\n");
173 * clear MII interrupt bit
175 writel(FEC_IEVENT_MII, ð->ievent);
176 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
182 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
184 return fec_mdio_read(bus->priv, phyAddr, regAddr);
187 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
190 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
193 #ifndef CONFIG_PHYLIB
194 static int miiphy_restart_aneg(struct eth_device *dev)
197 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
198 struct fec_priv *fec = (struct fec_priv *)dev->priv;
199 struct ethernet_regs *eth = fec->bus->priv;
202 * Wake up from sleep if necessary
203 * Reset PHY, then delay 300ns
206 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
208 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
212 * Set the auto-negotiation advertisement register bits
214 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
215 LPA_100FULL | LPA_100HALF | LPA_10FULL |
216 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
217 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
218 BMCR_ANENABLE | BMCR_ANRESTART);
220 if (fec->mii_postcall)
221 ret = fec->mii_postcall(fec->phy_id);
227 static int miiphy_wait_aneg(struct eth_device *dev)
231 struct fec_priv *fec = (struct fec_priv *)dev->priv;
232 struct ethernet_regs *eth = fec->bus->priv;
235 * Wait for AN completion
237 start = get_timer(0);
239 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
240 printf("%s: Autonegotiation timeout\n", dev->name);
244 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
246 printf("%s: Autonegotiation failed. status: %d\n",
250 } while (!(status & BMSR_LSTATUS));
256 static inline void fec_rx_task_enable(struct fec_priv *fec)
258 writel(1 << 24, &fec->eth->r_des_active);
261 static inline void fec_rx_task_disable(struct fec_priv *fec)
265 static inline void fec_tx_task_enable(struct fec_priv *fec)
267 writel(1 << 24, &fec->eth->x_des_active);
270 static inline void fec_tx_task_disable(struct fec_priv *fec)
275 * Initialize receive task's buffer descriptors
276 * @param[in] fec all we know about the device yet
277 * @param[in] count receive buffer count to be allocated
278 * @param[in] dsize desired size of each receive buffer
279 * @return 0 on success
281 * For this task we need additional memory for the data buffers. And each
282 * data buffer requires some alignment. Thy must be aligned to a specific
285 static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
291 * Allocate memory for the buffers. This allocation respects the
294 size = roundup(dsize, ARCH_DMA_MINALIGN);
295 for (i = 0; i < count; i++) {
296 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
298 uint8_t *data = memalign(ARCH_DMA_MINALIGN,
301 printf("%s: error allocating rxbuf %d\n",
305 writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
306 } /* needs allocation */
307 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
308 writew(0, &fec->rbd_base[i].data_length);
311 /* Mark the last RBD to close the ring. */
312 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
318 for (; i >= 0; i--) {
319 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
320 free((void *)data_ptr);
327 * Initialize transmit task's buffer descriptors
328 * @param[in] fec all we know about the device yet
330 * Transmit buffers are created externally. We only have to init the BDs here.\n
331 * Note: There is a race condition in the hardware. When only one BD is in
332 * use it must be marked with the WRAP bit to use it for every transmitt.
333 * This bit in combination with the READY bit results into double transmit
334 * of each data buffer. It seems the state machine checks READY earlier then
335 * resetting it after the first transfer.
336 * Using two BDs solves this issue.
338 static void fec_tbd_init(struct fec_priv *fec)
340 unsigned addr = (unsigned)fec->tbd_base;
341 unsigned size = roundup(2 * sizeof(struct fec_bd),
343 writew(0x0000, &fec->tbd_base[0].status);
344 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
346 flush_dcache_range(addr, addr + size);
350 * Mark the given read buffer descriptor as free
351 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
352 * @param[in] pRbd buffer descriptor to mark free again
354 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
356 unsigned short flags = FEC_RBD_EMPTY;
358 flags |= FEC_RBD_WRAP;
359 writew(flags, &pRbd->status);
360 writew(0, &pRbd->data_length);
363 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
366 imx_get_mac_from_fuse(dev_id, mac);
367 return !is_valid_ether_addr(mac);
370 static int fec_set_hwaddr(struct eth_device *dev)
372 uchar *mac = dev->enetaddr;
373 struct fec_priv *fec = (struct fec_priv *)dev->priv;
375 writel(0, &fec->eth->iaddr1);
376 writel(0, &fec->eth->iaddr2);
377 writel(0, &fec->eth->gaddr1);
378 writel(0, &fec->eth->gaddr2);
381 * Set physical address
383 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
385 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
390 static void fec_eth_phy_config(struct eth_device *dev)
393 struct fec_priv *fec = (struct fec_priv *)dev->priv;
394 struct phy_device *phydev;
396 if (fec->phy_id < 0) {
399 for (phy_id = 0; phy_id < 32; phy_id++) {
400 debug("%s: Probing PHY ID %02x\n", __func__, phy_id);
401 phydev = phy_connect(fec->bus, phy_id, dev,
402 PHY_INTERFACE_MODE_RGMII);
408 phydev = phy_connect(fec->bus, fec->phy_id, dev,
409 PHY_INTERFACE_MODE_RGMII);
412 fec->phydev = phydev;
419 * Do initial configuration of the FEC registers
421 static void fec_reg_setup(struct fec_priv *fec)
426 * Set interrupt mask register
428 writel(0x00000000, &fec->eth->imask);
431 * Clear FEC-Lite interrupt event register(IEVENT)
433 writel(0xffffffff, &fec->eth->ievent);
437 * Set FEC-Lite receive control register(R_CNTRL):
440 /* Start with frame length = 1518, common for all modes. */
441 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
442 if (fec->xcv_type == SEVENWIRE)
443 rcntrl |= FEC_RCNTRL_FCE;
444 else if (fec->xcv_type == RGMII)
445 rcntrl |= FEC_RCNTRL_RGMII;
446 else if (fec->xcv_type == RMII)
447 rcntrl |= FEC_RCNTRL_RMII;
449 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
451 writel(rcntrl, &fec->eth->r_cntrl);
455 * Start the FEC engine
456 * @param[in] dev Our device to handle
458 static int fec_open(struct eth_device *edev)
460 struct fec_priv *fec = edev->priv;
465 debug("fec_open: fec_open(dev)\n");
466 /* full-duplex, heartbeat disabled */
467 writel(1 << 2, &fec->eth->x_cntrl);
470 /* Invalidate all descriptors */
471 for (i = 0; i < FEC_RBD_NUM - 1; i++)
472 fec_rbd_clean(0, &fec->rbd_base[i]);
473 fec_rbd_clean(1, &fec->rbd_base[i]);
475 /* Flush the descriptors into RAM */
476 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
478 addr = (uint32_t)fec->rbd_base;
479 flush_dcache_range(addr, addr + size);
481 #ifdef FEC_QUIRK_ENET_MAC
482 /* Enable ENET HW endian SWAP */
483 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
485 /* Enable ENET store and forward mode */
486 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
490 * Enable FEC-Lite controller
492 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
494 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
497 * setup the MII gasket for RMII mode
500 /* disable the gasket */
501 writew(0, &fec->eth->miigsk_enr);
503 /* wait for the gasket to be disabled */
504 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
507 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
508 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
510 /* re-enable the gasket */
511 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
513 /* wait until MII gasket is ready */
515 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
516 if (--max_loops <= 0) {
517 printf("WAIT for MII Gasket ready timed out\n");
525 fec_eth_phy_config(edev);
527 /* Start up the PHY */
528 phy_startup(fec->phydev);
529 speed = fec->phydev->speed;
534 miiphy_wait_aneg(edev);
535 speed = miiphy_speed(edev->name, fec->phy_id);
536 miiphy_duplex(edev->name, fec->phy_id);
539 #ifdef FEC_QUIRK_ENET_MAC
541 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
542 u32 rcr = (readl(&fec->eth->r_cntrl) &
543 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
544 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
545 if (speed == _1000BASET)
546 ecr |= FEC_ECNTRL_SPEED;
547 else if (speed != _100BASET)
548 rcr |= FEC_RCNTRL_RMII_10T;
549 writel(ecr, &fec->eth->ecntrl);
550 writel(rcr, &fec->eth->r_cntrl);
553 debug("%s:Speed=%i\n", __func__, speed);
556 * Enable SmartDMA receive task
558 fec_rx_task_enable(fec);
564 static int fec_init(struct eth_device *dev, bd_t* bd)
566 struct fec_priv *fec = dev->priv;
567 uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
571 /* Initialize MAC address */
575 * Allocate transmit descriptors, there are two in total. This
576 * allocation respects cache alignment.
578 if (!fec->tbd_base) {
579 size = roundup(2 * sizeof(struct fec_bd),
581 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
582 if (!fec->tbd_base) {
586 memset(fec->tbd_base, 0, size);
588 flush_dcache_range((unsigned)fec->tbd_base, size);
592 * Allocate receive descriptors. This allocation respects cache
595 if (!fec->rbd_base) {
596 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
598 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
599 if (!fec->rbd_base) {
603 memset(fec->rbd_base, 0, size);
605 * Initialize RxBD ring
607 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
611 flush_dcache_range((unsigned)fec->rbd_base,
612 (unsigned)fec->rbd_base + size);
617 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
618 fec_mii_setspeed(fec);
621 * Set Opcode/Pause Duration Register
623 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
624 writel(0x2, &fec->eth->x_wmrk);
626 * Set multicast address filter
628 writel(0x00000000, &fec->eth->gaddr1);
629 writel(0x00000000, &fec->eth->gaddr2);
633 for (i = 0; i <= 0xfc >> 2; i++)
634 writel(0, &mib_ptr[i]);
636 /* FIFO receive start register */
637 writel(0x520, &fec->eth->r_fstart);
639 /* size and address of each buffer */
640 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
641 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
642 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
644 #ifndef CONFIG_PHYLIB
645 if (fec->xcv_type != SEVENWIRE)
646 miiphy_restart_aneg(dev);
660 * Halt the FEC engine
661 * @param[in] dev Our device to handle
663 static void fec_halt(struct eth_device *dev)
665 struct fec_priv *fec = (struct fec_priv *)dev->priv;
669 * issue graceful stop command to the FEC transmitter if necessary
671 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
674 debug("eth_halt: wait for stop regs\n");
676 * wait for graceful stop to register
678 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
682 * Disable SmartDMA tasks
684 fec_tx_task_disable(fec);
685 fec_rx_task_disable(fec);
688 * Disable the Ethernet Controller
689 * Note: this will also reset the BD index counter!
691 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
695 debug("eth_halt: done\n");
700 * @param[in] dev Our ethernet device to handle
701 * @param[in] packet Pointer to the data to be transmitted
702 * @param[in] length Data count in bytes
703 * @return 0 on success
705 static int fec_send(struct eth_device *dev, volatile void *packet, int length)
713 * This routine transmits one frame. This routine only accepts
714 * 6-byte Ethernet addresses.
716 struct fec_priv *fec = dev->priv;
719 * Check for valid length of data.
721 if ((length > 1500) || (length <= 0)) {
722 printf("Payload (%d) too large\n", length);
727 * Setup the transmit buffer. We are always using the first buffer for
728 * transmission, the second will be empty and only used to stop the DMA
729 * engine. We also flush the packet to RAM here to avoid cache trouble.
731 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
732 swap_packet((uint32_t *)packet, length);
735 addr = (uint32_t)packet;
736 size = roundup(length, ARCH_DMA_MINALIGN);
737 flush_dcache_range(addr, addr + size);
739 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
740 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
743 * update BD's status now
745 * - is always the last in a chain (means no chain)
746 * - should transmit the CRC
747 * - might be the last BD in the list, so the address counter should
748 * wrap (-> keep the WRAP flag)
750 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
751 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
752 writew(status, &fec->tbd_base[fec->tbd_index].status);
755 * Flush data cache. This code flushes both TX descriptors to RAM.
756 * After this code, the descriptors will be safely in RAM and we
759 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
760 addr = (uint32_t)fec->tbd_base;
761 flush_dcache_range(addr, addr + size);
764 * Enable SmartDMA transmit task
766 fec_tx_task_enable(fec);
769 * Wait until frame is sent. On each turn of the wait cycle, we must
770 * invalidate data cache to see what's really in RAM. Also, we need
773 invalidate_dcache_range(addr, addr + size);
774 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
778 invalidate_dcache_range(addr, addr + size);
781 debug("fec_send: status 0x%04x index %d\n",
782 readw(&fec->tbd_base[fec->tbd_index].status),
784 /* for next transmission use the other buffer */
794 * Pull one frame from the card
795 * @param[in] dev Our ethernet device to handle
796 * @return Length of packet read
798 static int fec_recv(struct eth_device *dev)
800 struct fec_priv *fec = (struct fec_priv *)dev->priv;
801 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
802 unsigned long ievent;
803 int frame_length, len = 0;
810 * Check if any critical events have happened
812 ievent = readl(&fec->eth->ievent);
813 writel(ievent, &fec->eth->ievent);
816 debug("fec_recv: ievent 0x%lx\n", ievent);
817 if (ievent & FEC_IEVENT_BABR) {
819 fec_init(dev, fec->bd);
820 printf("some error: 0x%08lx\n", ievent);
823 if (ievent & FEC_IEVENT_HBERR) {
824 /* Heartbeat error */
825 writel(0x00000001 | readl(&fec->eth->x_cntrl),
828 if (ievent & FEC_IEVENT_GRA) {
829 /* Graceful stop complete */
830 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
832 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
834 fec_init(dev, fec->bd);
839 * Read the buffer status. Before the status can be read, the data cache
840 * must be invalidated, because the data in RAM might have been changed
841 * by DMA. The descriptors are properly aligned to cachelines so there's
842 * no need to worry they'd overlap.
844 * WARNING: By invalidating the descriptor here, we also invalidate
845 * the descriptors surrounding this one. Therefore we can NOT change the
846 * contents of this descriptor nor the surrounding ones. The problem is
847 * that in order to mark the descriptor as processed, we need to change
848 * the descriptor. The solution is to mark the whole cache line when all
849 * descriptors in the cache line are processed.
851 addr = (uint32_t)rbd;
852 addr &= ~(ARCH_DMA_MINALIGN - 1);
853 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
854 invalidate_dcache_range(addr, addr + size);
856 bd_status = readw(&rbd->status);
857 if (!(bd_status & FEC_RBD_EMPTY)) {
858 debug("fec_recv: status 0x%04x len %u\n", bd_status,
859 readw(&rbd->data_length) - 4);
860 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
861 ((readw(&rbd->data_length) - 4) > 14)) {
863 * Get buffer address and size
865 frame = (struct nbuf *)readl(&rbd->data_pointer);
866 frame_length = readw(&rbd->data_length) - 4;
869 * Invalidate data cache over the buffer
871 addr = (uint32_t)frame;
872 size = roundup(frame_length, ARCH_DMA_MINALIGN);
873 invalidate_dcache_range(addr, addr + size);
876 * Fill the buffer and pass it to upper layers
878 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
879 swap_packet((uint32_t *)frame->data, frame_length);
881 memcpy((void *)NetRxPackets[rx_idx], frame->data, frame_length);
882 NetReceive(NetRxPackets[rx_idx], frame_length);
883 rx_idx = (rx_idx + 1) % PKTBUFSRX;
886 if (bd_status & FEC_RBD_ERR)
887 printf("error frame: 0x%08lx 0x%08x\n",
888 (ulong)rbd->data_pointer,
893 * Free the current buffer, restart the engine and move forward
894 * to the next buffer. Here we check if the whole cacheline of
895 * descriptors was already processed and if so, we mark it free
898 size = RXDESC_PER_CACHELINE - 1;
899 if ((fec->rbd_index & size) == size) {
900 i = fec->rbd_index - size;
901 addr = (uint32_t)&fec->rbd_base[i];
902 for (; i <= fec->rbd_index ; i++) {
903 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
906 flush_dcache_range(addr,
907 addr + ARCH_DMA_MINALIGN);
910 fec_rx_task_enable(fec);
911 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
912 debug("fec_recv: stop\n");
918 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
920 struct eth_device *edev;
921 struct fec_priv *fec;
923 unsigned char ethaddr[6];
927 /* create and fill edev struct */
928 edev = calloc(sizeof(struct eth_device), 1);
930 puts("fec_mxc: not enough malloc memory for eth_device\n");
935 fec = calloc(sizeof(struct fec_priv), 1);
937 puts("fec_mxc: not enough malloc memory for fec_priv\n");
943 edev->init = fec_init;
944 edev->send = fec_send;
945 edev->recv = fec_recv;
946 edev->halt = fec_halt;
947 edev->write_hwaddr = fec_set_hwaddr;
949 fec->eth = (struct ethernet_regs *)base_addr;
952 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
955 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
956 start = get_timer(0);
957 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
958 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
959 printf("FEC MXC: Timeout reseting chip\n");
966 fec_mii_setspeed(fec);
969 sprintf(edev->name, "FEC");
972 sprintf(edev->name, "FEC%i", dev_id);
973 fec->dev_id = dev_id;
975 fec->phy_id = phy_id;
979 printf("mdio_alloc failed\n");
983 bus->read = fec_phy_read;
984 bus->write = fec_phy_write;
985 sprintf(bus->name, edev->name);
988 * The i.MX28 has two ethernet interfaces, but they are not equal.
989 * Only the first one can access the MDIO bus.
991 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
993 bus->priv = fec->eth;
995 ret = mdio_register(bus);
997 printf("mdio_register failed\n");
1005 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1006 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1007 memcpy(edev->enetaddr, ethaddr, 6);
1010 fec_eth_phy_config(edev);
1021 #ifndef CONFIG_FEC_MXC_MULTI
1022 int fecmxc_initialize(bd_t *bd)
1026 debug("eth_init: fec_probe(PHY %02x FEC: %08x)\n",
1027 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
1028 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
1034 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1038 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1039 lout = fec_probe(bd, dev_id, phy_id, addr);
1044 #ifndef CONFIG_PHYLIB
1045 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1047 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1048 fec->mii_postcall = cb;