drivers/net/fm/t1040.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <fm_eth.h>
   9 #include <asm/io.h>
  10 #include <asm/immap_85xx.h>
  11 #include <asm/fsl_serdes.h>
  12
  13 phy_interface_t fman_port_enet_if(enum fm_port port)
  14 {
  15         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  16         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  17
  18         /* handle RGMII first */
  19         if ((port == FM1_DTSEC2) &&
  20             ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
  21                         FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
  22                 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  23                                 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
  24                         return PHY_INTERFACE_MODE_RGMII;
  25                 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  26                                 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
  27                         return PHY_INTERFACE_MODE_MII;
  28                 else
  29                         return PHY_INTERFACE_MODE_NONE;
  30         }
  31
  32         if ((port == FM1_DTSEC4) &&
  33             ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
  34                         FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
  35                 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  36                                 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
  37                         return PHY_INTERFACE_MODE_RGMII;
  38                 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  39                                 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
  40                         return PHY_INTERFACE_MODE_MII;
  41                 else
  42                         return PHY_INTERFACE_MODE_NONE;
  43         }
  44
  45         if (port == FM1_DTSEC5) {
  46                 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  47                                 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
  48                         return PHY_INTERFACE_MODE_RGMII;
  49                 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  50                                 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
  51                         return PHY_INTERFACE_MODE_MII;
  52         }
  53
  54         switch (port) {
  55         case FM1_DTSEC1:
  56         case FM1_DTSEC2:
  57                 if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
  58                         return PHY_INTERFACE_MODE_QSGMII;
  59         case FM1_DTSEC3:
  60         case FM1_DTSEC4:
  61         case FM1_DTSEC5:
  62                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  63                         return PHY_INTERFACE_MODE_SGMII;
  64                 break;
  65         default:
  66                 return PHY_INTERFACE_MODE_NONE;
  67         }
  68
  69         return PHY_INTERFACE_MODE_NONE;
  70 }