1 /******************************************************************************
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7 * Purpose: Second header file for driver and all other modules
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * The information in this file is provided "AS IS" without warranty.
22 ******************************************************************************/
24 /******************************************************************************
29 * Revision 1.1.3.1 2011-02-28 14:53:20 lothar
30 * imported Ka-Ro specific additions to U-Boot 2009.08 for TX28
32 * Revision 1.15 2003/02/25 14:16:40 mlindner
33 * Fix: Copyright statement
35 * Revision 1.14 2003/02/25 13:26:26 mlindner
36 * Add: Support for various vendors
38 * Revision 1.13 2002/10/02 12:46:02 mlindner
39 * Add: Support for Yukon
41 * Revision 1.12.2.2 2001/09/05 12:14:50 mlindner
42 * add: New hardware revision int
44 * Revision 1.12.2.1 2001/03/12 16:50:59 mlindner
45 * chg: kernel 2.4 adaption
47 * Revision 1.12 2001/03/01 12:52:15 mlindner
50 * Revision 1.11 2001/02/19 13:28:02 mlindner
51 * Changed PNMI parameter values
53 * Revision 1.10 2001/01/22 14:16:04 mlindner
54 * added ProcFs functionality
55 * Dual Net functionality integrated
58 * Revision 1.1 2000/10/05 19:46:50 phargrov
59 * Add directory src/vipk_devs_nonlbl/vipk_sk98lin/
60 * This is the SysKonnect SK-98xx Gigabit Ethernet driver,
61 * contributed by SysKonnect.
63 * Revision 1.9 2000/02/21 10:39:55 cgoos
64 * Added flag for jumbo support usage.
66 * Revision 1.8 1999/11/22 13:50:44 cgoos
67 * Changed license header to GPL.
70 * Revision 1.7 1999/09/28 12:38:21 cgoos
71 * Added CheckQueue to SK_AC.
73 * Revision 1.6 1999/07/27 08:04:05 cgoos
74 * Added checksumming variables to SK_AC.
76 * Revision 1.5 1999/03/29 12:33:26 cgoos
77 * Rreversed to fine lock granularity.
79 * Revision 1.4 1999/03/15 12:14:02 cgoos
80 * Added DriverLock to SK_AC.
81 * Removed other locks.
83 * Revision 1.3 1999/03/01 08:52:27 cgoos
84 * Changed pAC->PciDev declaration.
86 * Revision 1.2 1999/02/18 10:57:14 cgoos
87 * Removed SkDrvTimeStamp prototype.
88 * Fixed SkGeOsGetTime prototype.
90 * Revision 1.1 1999/02/16 07:41:01 cgoos
95 ******************************************************************************/
97 /******************************************************************************
101 * This is the second include file of the driver, which includes all other
102 * neccessary files and defines all structures and constants used by the
103 * driver and the common modules.
105 * Include File Hierarchy:
109 ******************************************************************************/
111 #ifndef __INC_SKDRV2ND_H
112 #define __INC_SKDRV2ND_H
114 #include "h/skqueue.h"
115 #include "h/skgehwt.h"
116 #include "h/sktimer.h"
118 #include "h/skgepnmi.h"
120 #include "h/skgehw.h"
121 #include "h/skgeinit.h"
122 #include "h/skaddr.h"
123 #include "h/skgesirq.h"
124 #include "h/skcsum.h"
125 #include "h/skrlmt.h"
126 #include "h/skgedrv.h"
128 #define SK_PCI_ISCOMPLIANT(result, pdev) { \
129 result = SK_FALSE; /* default */ \
130 /* 3Com (0x10b7) */ \
131 if (pdev->vendor == 0x10b7) { \
132 /* Gigabit Ethernet Adapter (0x1700) */ \
133 if ((pdev->device == 0x1700)) { \
136 /* SysKonnect (0x1148) */ \
137 } else if (pdev->vendor == 0x1148) { \
138 /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \
139 /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \
140 if ((pdev->device == 0x4300) || \
141 (pdev->device == 0x4320)) { \
144 /* D-Link (0x1186) */ \
145 } else if (pdev->vendor == 0x1186) { \
146 /* Gigabit Ethernet Adapter (0x4c00) */ \
147 if ((pdev->device == 0x4c00)) { \
150 /* CNet (0x1371) */ \
151 } else if (pdev->vendor == 0x1371) { \
152 /* GigaCard Network Adapter (0x434e) */ \
153 if ((pdev->device == 0x434e)) { \
156 /* Linksys (0x1737) */ \
157 } else if (pdev->vendor == 0x1737) { \
158 /* Gigabit Network Adapter (0x1032) */ \
159 /* Gigabit Network Adapter (0x1064) */ \
160 if ((pdev->device == 0x1032) || \
161 (pdev->device == 0x1064)) { \
170 extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
171 extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
172 extern SK_U64 SkOsGetTime(SK_AC*);
173 extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
174 extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
175 extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
176 extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
177 extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
178 extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
179 extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
181 struct s_DrvRlmtMbuf {
182 SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
183 SK_U8 *pData; /* Data buffer (virtually contig.). */
184 unsigned Size; /* Data buffer size. */
185 unsigned Length; /* Length of packet (<= Size). */
186 SK_U32 PortIdx; /* Receiving/transmitting port. */
187 #ifdef SK_RLMT_MBUF_PRIVATE
188 SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
189 #endif /* SK_RLMT_MBUF_PRIVATE */
190 struct sk_buff *pOs; /* Pointer to message block */
197 #define SK_IOCTL_BASE (SIOCDEVPRIVATE)
198 #define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
199 #define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
200 #define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
202 typedef struct s_IOCTL SK_GE_IOCTL;
211 * define sizes of descriptor rings in bytes
215 #define TX_RING_SIZE (8*1024)
216 #define RX_RING_SIZE (24*1024)
218 #define TX_RING_SIZE (10 * 40)
219 #define RX_RING_SIZE (10 * 40)
223 * Buffer size for ethernet packets
225 #define ETH_BUF_SIZE 1540
226 #define ETH_MAX_MTU 1514
227 #define ETH_MIN_MTU 60
228 #define ETH_MULTICAST_BIT 0x01
229 #define SK_JUMBO_MTU 9000
232 * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
234 #define TX_PRIO_LOW 0
235 #define TX_PRIO_HIGH 1
238 * alignment of rx/tx descriptors
240 #define DESCR_ALIGN 8
243 * definitions for pnmi. TODO
245 #define SK_DRIVER_RESET(pAC, IoC) 0
246 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0
247 #define SK_DRIVER_SELFTEST(pAC, IoC) 0
248 /* For get mtu you must add an own function */
249 #define SK_DRIVER_GET_MTU(pAc,IoC,i) 0
250 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
251 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
254 /* TX and RX descriptors *****************************************************/
256 typedef struct s_RxD RXD; /* the receive descriptor */
259 volatile SK_U32 RBControl; /* Receive Buffer Control */
260 SK_U32 VNextRxd; /* Next receive descriptor,low dword */
261 SK_U32 VDataLow; /* Receive buffer Addr, low dword */
262 SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
263 SK_U32 FrameStat; /* Receive Frame Status word */
264 SK_U32 TimeStamp; /* Time stamp from XMAC */
265 SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
266 SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
267 RXD *pNextRxd; /* Pointer to next Rxd */
268 struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
271 typedef struct s_TxD TXD; /* the transmit descriptor */
274 volatile SK_U32 TBControl; /* Transmit Buffer Control */
275 SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
276 SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
277 SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
278 SK_U32 FrameStat; /* Transmit Frame Status Word */
279 SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
280 SK_U16 TcpSumSt; /* TCP Sum Start */
281 SK_U16 TcpSumWr; /* TCP Sum Write */
282 SK_U32 TcpReserved; /* not used */
283 TXD *pNextTxd; /* Pointer to next Txd */
284 struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
288 /* definition of flags in descriptor control field */
289 #define RX_CTRL_OWN_BMU UINT32_C(0x80000000)
290 #define RX_CTRL_STF UINT32_C(0x40000000)
291 #define RX_CTRL_EOF UINT32_C(0x20000000)
292 #define RX_CTRL_EOB_IRQ UINT32_C(0x10000000)
293 #define RX_CTRL_EOF_IRQ UINT32_C(0x08000000)
294 #define RX_CTRL_DEV_NULL UINT32_C(0x04000000)
295 #define RX_CTRL_STAT_VALID UINT32_C(0x02000000)
296 #define RX_CTRL_TIME_VALID UINT32_C(0x01000000)
297 #define RX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000)
298 #define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000)
299 #define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
301 #define TX_CTRL_OWN_BMU UINT32_C(0x80000000)
302 #define TX_CTRL_STF UINT32_C(0x40000000)
303 #define TX_CTRL_EOF UINT32_C(0x20000000)
304 #define TX_CTRL_EOB_IRQ UINT32_C(0x10000000)
305 #define TX_CTRL_EOF_IRQ UINT32_C(0x08000000)
306 #define TX_CTRL_ST_FWD UINT32_C(0x04000000)
307 #define TX_CTRL_DISAB_CRC UINT32_C(0x02000000)
308 #define TX_CTRL_SOFTWARE UINT32_C(0x01000000)
309 #define TX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000)
310 #define TX_CTRL_CHECK_CSUM UINT32_C(0x00560000)
311 #define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
314 /* The offsets of registers in the TX and RX queue control io area ***********/
316 #define RX_Q_BUF_CTRL_CNT 0x00
317 #define RX_Q_NEXT_DESCR_LOW 0x04
318 #define RX_Q_BUF_ADDR_LOW 0x08
319 #define RX_Q_BUF_ADDR_HIGH 0x0c
320 #define RX_Q_FRAME_STAT 0x10
321 #define RX_Q_TIME_STAMP 0x14
322 #define RX_Q_CSUM_1_2 0x18
323 #define RX_Q_CSUM_START_1_2 0x1c
324 #define RX_Q_CUR_DESCR_LOW 0x20
325 #define RX_Q_DESCR_HIGH 0x24
326 #define RX_Q_CUR_ADDR_LOW 0x28
327 #define RX_Q_CUR_ADDR_HIGH 0x2c
328 #define RX_Q_CUR_BYTE_CNT 0x30
329 #define RX_Q_CTRL 0x34
330 #define RX_Q_FLAG 0x38
331 #define RX_Q_TEST1 0x3c
332 #define RX_Q_TEST2 0x40
333 #define RX_Q_TEST3 0x44
335 #define TX_Q_BUF_CTRL_CNT 0x00
336 #define TX_Q_NEXT_DESCR_LOW 0x04
337 #define TX_Q_BUF_ADDR_LOW 0x08
338 #define TX_Q_BUF_ADDR_HIGH 0x0c
339 #define TX_Q_FRAME_STAT 0x10
340 #define TX_Q_CSUM_START 0x14
341 #define TX_Q_CSUM_START_POS 0x18
342 #define TX_Q_RESERVED 0x1c
343 #define TX_Q_CUR_DESCR_LOW 0x20
344 #define TX_Q_DESCR_HIGH 0x24
345 #define TX_Q_CUR_ADDR_LOW 0x28
346 #define TX_Q_CUR_ADDR_HIGH 0x2c
347 #define TX_Q_CUR_BYTE_CNT 0x30
348 #define TX_Q_CTRL 0x34
349 #define TX_Q_FLAG 0x38
350 #define TX_Q_TEST1 0x3c
351 #define TX_Q_TEST2 0x40
352 #define TX_Q_TEST3 0x44
354 /* definition of flags in the queue control field */
355 #define RX_Q_CTRL_POLL_ON 0x00000080
356 #define RX_Q_CTRL_POLL_OFF 0x00000040
357 #define RX_Q_CTRL_STOP 0x00000020
358 #define RX_Q_CTRL_START 0x00000010
359 #define RX_Q_CTRL_CLR_I_PAR 0x00000008
360 #define RX_Q_CTRL_CLR_I_EOB 0x00000004
361 #define RX_Q_CTRL_CLR_I_EOF 0x00000002
362 #define RX_Q_CTRL_CLR_I_ERR 0x00000001
364 #define TX_Q_CTRL_POLL_ON 0x00000080
365 #define TX_Q_CTRL_POLL_OFF 0x00000040
366 #define TX_Q_CTRL_STOP 0x00000020
367 #define TX_Q_CTRL_START 0x00000010
368 #define TX_Q_CTRL_CLR_I_EOB 0x00000004
369 #define TX_Q_CTRL_CLR_I_EOF 0x00000002
370 #define TX_Q_CTRL_CLR_I_ERR 0x00000001
373 /* Interrupt bits in the interrupts source register **************************/
374 #define IRQ_HW_ERROR 0x80000000
375 #define IRQ_RESERVED 0x40000000
376 #define IRQ_PKT_TOUT_RX1 0x20000000
377 #define IRQ_PKT_TOUT_RX2 0x10000000
378 #define IRQ_PKT_TOUT_TX1 0x08000000
379 #define IRQ_PKT_TOUT_TX2 0x04000000
380 #define IRQ_I2C_READY 0x02000000
381 #define IRQ_SW 0x01000000
382 #define IRQ_EXTERNAL_REG 0x00800000
383 #define IRQ_TIMER 0x00400000
384 #define IRQ_MAC1 0x00200000
385 #define IRQ_LINK_SYNC_C_M1 0x00100000
386 #define IRQ_MAC2 0x00080000
387 #define IRQ_LINK_SYNC_C_M2 0x00040000
388 #define IRQ_EOB_RX1 0x00020000
389 #define IRQ_EOF_RX1 0x00010000
390 #define IRQ_CHK_RX1 0x00008000
391 #define IRQ_EOB_RX2 0x00004000
392 #define IRQ_EOF_RX2 0x00002000
393 #define IRQ_CHK_RX2 0x00001000
394 #define IRQ_EOB_SY_TX1 0x00000800
395 #define IRQ_EOF_SY_TX1 0x00000400
396 #define IRQ_CHK_SY_TX1 0x00000200
397 #define IRQ_EOB_AS_TX1 0x00000100
398 #define IRQ_EOF_AS_TX1 0x00000080
399 #define IRQ_CHK_AS_TX1 0x00000040
400 #define IRQ_EOB_SY_TX2 0x00000020
401 #define IRQ_EOF_SY_TX2 0x00000010
402 #define IRQ_CHK_SY_TX2 0x00000008
403 #define IRQ_EOB_AS_TX2 0x00000004
404 #define IRQ_EOF_AS_TX2 0x00000002
405 #define IRQ_CHK_AS_TX2 0x00000001
407 #define DRIVER_IRQS (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \
408 IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \
409 IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2)
411 #define SPECIAL_IRQS (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
412 IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
413 IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
414 IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \
415 IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \
416 IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
417 IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
418 IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
420 #define IRQ_MASK (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \
421 IRQ_EOB_RX2 | IRQ_EOF_RX2 | \
422 IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \
423 IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \
424 IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \
425 IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \
426 IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
427 IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
428 IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
431 IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
432 IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
433 IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
435 #define IRQ_HWE_MASK 0x00000FFF /* enable all HW irqs */
437 typedef struct s_DevNet DEV_NET;
447 typedef struct s_TxPort TX_PORT;
450 /* the transmit descriptor rings */
451 caddr_t pTxDescrRing; /* descriptor area memory */
452 SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
453 TXD *pTxdRingHead; /* Head of Tx rings */
454 TXD *pTxdRingTail; /* Tail of Tx rings */
455 TXD *pTxdRingPrev; /* descriptor sent previously */
456 int TxdRingFree; /* # of free entrys */
458 spinlock_t TxDesRingLock; /* serialize descriptor accesses */
460 caddr_t HwAddr; /* bmu registers address */
461 int PortIndex; /* index number of port (0 or 1) */
464 typedef struct s_RxPort RX_PORT;
467 /* the receive descriptor rings */
468 caddr_t pRxDescrRing; /* descriptor area memory */
469 SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
470 RXD *pRxdRingHead; /* Head of Rx rings */
471 RXD *pRxdRingTail; /* Tail of Rx rings */
472 RXD *pRxdRingPrev; /* descriptor given to BMU previously */
473 int RxdRingFree; /* # of free entrys */
475 spinlock_t RxDesRingLock; /* serialize descriptor accesses */
477 int RxFillLimit; /* limit for buffers in ring */
478 caddr_t HwAddr; /* bmu registers address */
479 int PortIndex; /* index number of port (0 or 1) */
482 typedef struct s_PerStrm PER_STRM;
484 #define SK_ALLOC_IRQ 0x00000001
486 /****************************************************************************
487 * Per board structure / Adapter Context structure:
488 * Allocated within attach(9e) and freed within detach(9e).
489 * Contains all 'per device' necessary handles, flags, locks etc.:
492 SK_GEINIT GIni; /* GE init struct */
493 SK_PNMI Pnmi; /* PNMI data struct */
494 SK_VPD vpd; /* vpd data struct */
495 SK_QUEUE Event; /* Event queue */
496 SK_HWT Hwt; /* Hardware Timer control struct */
497 SK_TIMCTRL Tim; /* Software Timer control struct */
498 SK_I2C I2c; /* I2C relevant data structure */
499 SK_ADDR Addr; /* for Address module */
500 SK_CSUM Csum; /* for checksum module */
501 SK_RLMT Rlmt; /* for rlmt module */
503 spinlock_t SlowPathLock; /* Normal IRQ lock */
505 SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
506 int RlmtMode; /* link check mode to set */
507 int RlmtNets; /* Number of nets */
509 SK_IOC IoBase; /* register set of adapter */
510 int BoardLevel; /* level of active hw init (0-2) */
511 char DeviceStr[80]; /* adapter string from vpd */
512 SK_U32 AllocFlag; /* flag allocation of resources */
514 struct pci_dev *PciDev; /* for access to pci config space */
515 SK_U32 PciDevId; /* pci device id */
519 struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
520 char Name[30]; /* driver name */
521 struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */
522 int RxBufSize; /* length of receive buffers */
524 struct net_device_stats stats; /* linux 'netstat -i' statistics */
526 int Index; /* internal board index number */
528 /* adapter RAM sizes for queues of active port */
529 int RxQueueSize; /* memory used for receive queue */
530 int TxSQueueSize; /* memory used for sync. tx queue */
531 int TxAQueueSize; /* memory used for async. tx queue */
533 int PromiscCount; /* promiscuous mode counter */
534 int AllMultiCount; /* allmulticast mode counter */
535 int MulticCount; /* number of different MC */
536 /* addresses for this board */
537 /* (may be more than HW can)*/
539 int HWRevision; /* Hardware revision */
540 int ActivePort; /* the active XMAC port */
541 int MaxPorts; /* number of activated ports */
542 int TxDescrPerRing; /* # of descriptors per tx ring */
543 int RxDescrPerRing; /* # of descriptors per rx ring */
545 caddr_t pDescrMem; /* Pointer to the descriptor area */
546 dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
548 /* the port structures with descriptor rings */
549 TX_PORT TxPort[SK_MAX_MACS][2];
550 RX_PORT RxPort[SK_MAX_MACS];
552 unsigned int CsOfs1; /* for checksum calculation */
553 unsigned int CsOfs2; /* for checksum calculation */
554 SK_U32 CsOfs; /* for checksum calculation */
556 SK_BOOL CheckQueue; /* check event queue soon */
564 #endif /* __INC_SKDRV2ND_H */