]> git.kernelconcepts.de Git - karo-tx-uboot.git/blob - drivers/pci.c
* Patch by Thomas Frieden, 13 Nov 2002:
[karo-tx-uboot.git] / drivers / pci.c
1 /*
2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3  * Andreas Heppel <aheppel@sysgo.de>
4  *
5  * (C) Copyright 2002
6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 /*
28  * PCI routines
29  */
30
31 #include <common.h>
32
33 #ifdef CONFIG_PCI
34
35 #include <command.h>
36 #include <cmd_boot.h>
37 #include <asm/processor.h>
38 #include <asm/io.h>
39 #include <pci.h>
40
41 #ifdef DEBUG
42 #define DEBUGF(x...) printf(x)
43 #else
44 #define DEBUGF(x...)
45 #endif /* DEBUG */
46
47 /*
48  *
49  */
50
51 #define PCI_HOSE_OP(rw, size, type)                                             \
52 int pci_hose_##rw##_config_##size(struct pci_controller *hose,                  \
53                                   pci_dev_t dev,                                \
54                                   int offset, type value)                       \
55 {                                                                               \
56         return hose->rw##_##size(hose, dev, offset, value);                     \
57 }
58
59 PCI_HOSE_OP(read, byte, u8 *)
60 PCI_HOSE_OP(read, word, u16 *)
61 PCI_HOSE_OP(read, dword, u32 *)
62 PCI_HOSE_OP(write, byte, u8)
63 PCI_HOSE_OP(write, word, u16)
64 PCI_HOSE_OP(write, dword, u32)
65
66 #define PCI_OP(rw, size, type, error_code)                                      \
67 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)             \
68 {                                                                               \
69         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));            \
70                                                                                 \
71         if (!hose)                                                              \
72         {                                                                       \
73                 error_code;                                                     \
74                 return -1;                                                      \
75         }                                                                       \
76                                                                                 \
77         return pci_hose_##rw##_config_##size(hose, dev, offset, value);         \
78 }
79
80 PCI_OP(read, byte, u8 *, *value = 0xff)
81 PCI_OP(read, word, u16 *, *value = 0xffff)
82 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
83 PCI_OP(write, byte, u8, )
84 PCI_OP(write, word, u16, )
85 PCI_OP(write, dword, u32, )
86
87 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                             \
88 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,        \
89                                         pci_dev_t dev,                          \
90                                         int offset, type val)                   \
91 {                                                                               \
92         u32 val32;                                                              \
93                                                                                 \
94         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)   \
95                 return -1;                                                      \
96                                                                                 \
97         *val = (val32 >> ((offset & (int)off_mask) * 8));                       \
98                                                                                 \
99         return 0;                                                               \
100 }
101
102 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)                  \
103 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,       \
104                                              pci_dev_t dev,                     \
105                                              int offset, type val)              \
106 {                                                                               \
107         u32 val32, mask, ldata;                                                 \
108                                                                                 \
109         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)   \
110                 return -1;                                                      \
111                                                                                 \
112         mask = val_mask;                                                        \
113         ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\
114         mask <<= ((mask & (int)off_mask) * 8);                                  \
115         val32 = (val32 & ~mask) | ldata;                                        \
116                                                                                 \
117         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)   \
118                 return -1;                                                      \
119                                                                                 \
120         return 0;                                                               \
121 }
122
123 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
124 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
125 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
126 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
127
128 /*
129  *
130  */
131
132 static struct pci_controller* hose_head = NULL;
133
134 void pci_register_hose(struct pci_controller* hose)
135 {
136         struct pci_controller **phose = &hose_head;
137
138         while(*phose)
139                 phose = &(*phose)->next;
140
141         hose->next = NULL;
142
143         *phose = hose;
144 }
145
146 struct pci_controller* pci_bus_to_hose(int bus)
147 {
148         struct pci_controller *hose;
149
150         for (hose = hose_head; hose; hose = hose->next)
151                 if (bus >= hose->first_busno &&
152                     bus <= hose->last_busno)
153                         return hose;
154
155         return NULL;
156 }
157
158 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
159 {
160         struct pci_controller * hose;
161         u16 vendor, device;
162         u8 header_type;
163         pci_dev_t bdf;
164         int i, bus, found_multi = 0;
165
166         for (hose = hose_head; hose; hose = hose->next)
167         {
168 #if CFG_SCSI_SCAN_BUS_REVERSE
169                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
170 #else
171                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
172 #endif
173                         for (bdf = PCI_BDF(bus,0,0);
174 #ifdef CONFIG_ELPPC
175                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
176 #else
177                              bdf < PCI_BDF(bus+1,0,0);
178 #endif
179                              bdf += PCI_BDF(0,0,1))
180                         {
181                                 if (!PCI_FUNC(bdf))
182                                 {
183                                         pci_read_config_byte(bdf,
184                                                              PCI_HEADER_TYPE,
185                                                              &header_type);
186
187                                         found_multi = header_type & 0x80;
188                                 }
189                                 else
190                                 {
191                                         if (!found_multi)
192                                                 continue;
193                                 }
194
195                                 pci_read_config_word(bdf,
196                                                      PCI_VENDOR_ID,
197                                                      &vendor);
198                                 pci_read_config_word(bdf,
199                                                      PCI_DEVICE_ID,
200                                                      &device);
201
202                                 for (i=0; ids[i].vendor != 0; i++)
203                                         if (vendor == ids[i].vendor &&
204                                             device == ids[i].device)
205                                         {
206                                                 if (index <= 0)
207                                                         return bdf;
208
209                                                 index--;
210                                         }
211                         }
212         }
213
214         return (-1);
215 }
216
217 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
218 {
219         static struct pci_device_id ids[2] = {{}, {0, 0}};
220
221         ids[0].vendor = vendor;
222         ids[0].device = device;
223
224         return pci_find_devices(ids, index);
225 }
226
227 /*
228  *
229  */
230
231 unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
232                                    unsigned long phys_addr,
233                                    unsigned long flags)
234 {
235         struct pci_region *res;
236         unsigned long bus_addr;
237         int i;
238
239         if (!hose)
240         {
241                 printf("pci_hose_phys_to_bus: %s\n", "invalid hose");
242                 goto Done;
243         }
244
245         for (i=0; i<hose->region_count; i++)
246         {
247                 res = &hose->regions[i];
248
249                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
250                         continue;
251
252                 bus_addr = phys_addr - res->phys_start + res->bus_start;
253
254                 if (bus_addr >= res->bus_start &&
255                     bus_addr <  res->bus_start + res->size)
256                 {
257                         return bus_addr;
258                 }
259         }
260
261         printf("pci_hose_phys_to_bus: %s\n", "invalid physical address");
262
263  Done:
264         return 0;
265 }
266
267 unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
268                                    unsigned long bus_addr,
269                                    unsigned long flags)
270 {
271         struct pci_region *res;
272         int i;
273
274         if (!hose)
275         {
276                 printf("pci_hose_bus_to_phys: %s\n", "invalid hose");
277                 goto Done;
278         }
279
280         for (i=0; i<hose->region_count; i++)
281         {
282                 res = &hose->regions[i];
283
284                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
285                         continue;
286
287                 if (bus_addr >= res->bus_start &&
288                     bus_addr <  res->bus_start + res->size)
289                 {
290                         return bus_addr - res->bus_start + res->phys_start;
291                 }
292         }
293
294         printf("pci_hose_bus_to_phys: %s\n", "invalid physical address");
295
296  Done:
297         return 0;
298 }
299
300 /*
301  *
302  */
303
304 int pci_hose_config_device(struct pci_controller *hose,
305                            pci_dev_t dev,
306                            unsigned long io,
307                            unsigned long mem,
308                            unsigned long command)
309 {
310         unsigned int bar_response, bar_size, bar_value, old_command;
311         unsigned char pin;
312         int bar, found_mem64;
313
314         DEBUGF("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", io, mem, command);
315
316         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
317
318         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4)
319         {
320                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
321                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
322
323                 if (!bar_response)
324                         continue;
325
326                 found_mem64 = 0;
327
328                 /* Check the BAR type and set our address mask */
329                 if (bar_response & PCI_BASE_ADDRESS_SPACE)
330                 {
331                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
332                         bar_value = io;
333
334                         io = ((io - 1) | (bar_size - 1)) + 1;
335                 }
336                 else
337                 {
338                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
339                              PCI_BASE_ADDRESS_MEM_TYPE_64)
340                                 found_mem64 = 1;
341
342                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
343                         bar_value = mem;
344
345                         mem = ((mem - 1) | (bar_size - 1)) + 1;
346                 }
347
348                 /* Write it out and update our limit */
349                 pci_hose_write_config_dword(hose, dev, bar, bar_value);
350
351                 if (found_mem64)
352                 {
353                         bar += 4;
354                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
355                 }
356         }
357
358         /* Configure Cache Line Size Register */
359         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
360
361         /* Configure Latency Timer */
362         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
363
364         /* Disable interrupt line, if device says it wants to use interrupts */
365         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
366         if (pin != 0)
367         {
368                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
369         }
370
371         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
372         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
373                                     (old_command & 0xffff0000) | command );
374
375         return 0;
376 }
377
378 /*
379  *
380  */
381
382 struct pci_config_table *pci_find_config(struct pci_controller *hose,
383                                          unsigned short class,
384                                          unsigned int vendor,
385                                          unsigned int device,
386                                          unsigned int bus,
387                                          unsigned int dev,
388                                          unsigned int func)
389 {
390         struct pci_config_table *table;
391
392         for (table = hose->config_table; table && table->vendor; table++)
393         {
394                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
395                     (table->device == PCI_ANY_ID || table->device == device) &&
396                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
397                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
398                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
399                     (table->func   == PCI_ANY_ID || table->func   == func))
400                 {
401                         return table;
402                 }
403         }
404
405         return NULL;
406 }
407
408 void pci_cfgfunc_config_device(struct pci_controller *hose,
409                                pci_dev_t dev,
410                                struct pci_config_table *entry)
411 {
412         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
413 }
414
415 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
416                             pci_dev_t dev, struct pci_config_table *entry)
417 {
418 }
419
420 /*
421  *
422  */
423
424 /* HJF: Changed this to return int. I think this is required
425  * to get the correct result when scanning bridges
426  */
427 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
428 extern void pciauto_config_init(struct pci_controller *hose);
429
430 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
431 {
432         unsigned int sub_bus, found_multi=0;
433         unsigned short vendor, device, class;
434         unsigned char header_type;
435         struct pci_config_table *cfg;
436         pci_dev_t dev;
437
438         sub_bus = bus;
439
440         for (dev =  PCI_BDF(bus,0,0);
441              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
442              dev += PCI_BDF(0,0,1))
443         {
444 #ifndef CONFIG_405GP /* don't skip host bridge on ppc405gp */
445                 /* Skip our host bridge */
446                 if ( dev == PCI_BDF(hose->first_busno,0,0) )
447                         continue;
448 #endif
449
450                 if (PCI_FUNC(dev) && !found_multi)
451                         continue;
452
453                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
454
455                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
456
457                 if (vendor != 0xffff && vendor != 0x0000) {
458
459                         if (!PCI_FUNC(dev))
460                                 found_multi = header_type & 0x80;
461
462                         DEBUGF("PCI Scan: Found Bus %d, Device %d, Function %d\n",
463                             PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
464
465                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
466                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
467
468                         cfg = pci_find_config(hose, class, vendor, device,
469                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
470                         if (cfg) {
471                                 cfg->config_device(hose, dev, cfg);
472 #ifdef CONFIG_PCI_PNP
473                         } else {
474                                 int n = pciauto_config_device(hose, dev);
475
476                                 sub_bus = max(sub_bus, n);
477 #endif
478                         }
479                         if (hose->fixup_irq)
480                                 hose->fixup_irq(hose, dev);
481
482 #ifdef CONFIG_PCI_SCAN_SHOW
483                         /* Skip our host bridge */
484                         if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
485                             unsigned char int_line;
486
487                             pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
488                                                       &int_line);
489                             printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
490                                    PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
491                                    int_line);
492                         }
493 #endif
494                 }
495         }
496
497         return sub_bus;
498 }
499
500 int pci_hose_scan(struct pci_controller *hose)
501 {
502 #ifdef CONFIG_PCI_PNP
503         pciauto_config_init(hose);
504 #endif
505         return pci_hose_scan_bus(hose, hose->first_busno);
506 }
507
508 #endif /* CONFIG_PCI */