2 * SuperH SCIF device driver.
3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <asm/processor.h>
23 #if defined (CONFIG_CONS_SCIF0)
24 #define SCIF_BASE SCIF0_BASE
25 #elif defined (CONFIG_CONS_SCIF1)
26 #define SCIF_BASE SCIF1_BASE
27 #elif defined (CONFIG_CONS_SCIF2)
28 #define SCIF_BASE SCIF2_BASE
30 #error "Default SCIF doesn't set....."
34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0)
35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4)
36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
40 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
41 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
42 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
44 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
45 # define SCFSR (vu_short *)(SCIF_BASE + 0x10)
46 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
49 #if defined(CONFIG_CPU_SH7780) || \
50 defined(CONFIG_CPU_SH7785)
51 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
52 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
53 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
54 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
56 # define FIFOLEVEL_MASK 0xFF
57 #elif defined(CONFIG_CPU_SH7763)
58 # if defined (CONFIG_CONS_SCIF2)
59 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
60 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
62 # define FIFOLEVEL_MASK 0x1F
64 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
65 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
66 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
67 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
69 # define FIFOLEVEL_MASK 0xFF
71 #elif defined(CONFIG_CPU_SH7750) || \
72 defined(CONFIG_CPU_SH7751) || \
73 defined(CONFIG_CPU_SH7722) || \
74 defined(CONFIG_CPU_SH7203)
75 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
76 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
78 # define FIFOLEVEL_MASK 0x1F
79 #elif defined(CONFIG_CPU_SH7720)
80 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
81 # define LSR_ORER 0x0200
82 # define FIFOLEVEL_MASK 0x1F
83 #elif defined(CONFIG_CPU_SH7710) || \
84 defined(CONFIG_CPU_SH7712)
85 # define SCLSR SCFSR /* SCSSR */
87 # define FIFOLEVEL_MASK 0x1F
90 /* SCBRR register value setting */
91 #if defined(CONFIG_CPU_SH7720)
92 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
93 #else /* Generic SuperH */
94 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
97 #define SCR_RE (1 << 4)
98 #define SCR_TE (1 << 5)
99 #define FCR_RFRST (1 << 1) /* RFCL */
100 #define FCR_TFRST (1 << 2) /* TFCL */
101 #define FSR_DR (1 << 0)
102 #define FSR_RDF (1 << 1)
103 #define FSR_FER (1 << 3)
104 #define FSR_BRK (1 << 4)
105 #define FSR_FER (1 << 3)
106 #define FSR_TEND (1 << 6)
107 #define FSR_ER (1 << 7)
109 /*----------------------------------------------------------------------*/
111 void serial_setbrg(void)
113 DECLARE_GLOBAL_DATA_PTR;
114 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
117 int serial_init(void)
119 *SCSCR = (SCR_RE | SCR_TE);
122 *SCFCR = (FCR_RFRST | FCR_TFRST);
130 static int serial_rx_fifo_level(void)
133 return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
135 return (*SCFDR >> 0) & FIFOLEVEL_MASK;
139 void serial_raw_putc(const char c)
141 unsigned int fsr_bits_to_clear;
144 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
145 fsr_bits_to_clear = FSR_TEND;
151 if (fsr_bits_to_clear != 0)
152 *SCFSR &= ~fsr_bits_to_clear;
155 void serial_putc(const char c)
158 serial_raw_putc('\r');
162 void serial_puts(const char *s)
165 while ((c = *s++) != 0)
169 int serial_tstc(void)
171 return serial_rx_fifo_level()? 1 : 0;
174 #define FSR_ERR_CLEAR 0x0063
175 #define RDRF_CLEAR 0x00fc
176 void handle_error(void)
180 *SCFSR = FSR_ERR_CLEAR;
185 int serial_getc_check(void)
187 unsigned short status;
191 if (status & (FSR_FER | FSR_ER | FSR_BRK))
193 if (*SCLSR & LSR_ORER)
195 return (status & (FSR_DR | FSR_RDF));
198 int serial_getc(void)
200 unsigned short status;
202 while (!serial_getc_check()) ;
209 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
212 if (*SCLSR & LSR_ORER)