4 bool "Enable SPI support"
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
11 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
12 the SPI uclass. Drivers provide methods to access the SPI
13 buses that they control. The uclass interface is defined in
14 include/spi.h. The existing spi_slave structure is attached
15 as 'parent data' to every slave on each bus. Slaves
16 typically use driver-private data instead of extending the
22 bool "Cadence QSPI driver"
24 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
25 used to access the SPI NOR flash on platforms embedding this
29 bool "Designware SPI driver"
31 Enable the Designware SPI driver. This driver can be used to
32 access the SPI NOR flash on platforms embedding this Designware
36 bool "Samsung Exynos SPI driver"
38 Enable the Samsung Exynos SPI driver. This driver can be used to
39 access the SPI NOR flash on platforms embedding this Samsung
43 bool "Freescale DSPI driver"
45 Enable the Freescale DSPI driver. This driver can be used to
46 access the SPI NOR flash and SPI Data flash on platforms embedding
47 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
51 bool "Freescale QSPI driver"
53 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
54 used to access the SPI NOR flash on platforms embedding this
58 bool "Intel ICH SPI driver"
60 Enable the Intel ICH SPI driver. This driver can be used to
61 access the SPI NOR flash on platforms embedding this Intel
65 bool "Sandbox SPI driver"
66 depends on SANDBOX && DM
68 Enable SPI support for sandbox. This is an emulation of a real SPI
69 bus. Devices can be attached to the bus using the device tree
70 which specifies the driver to use. As an example, see this device
71 tree fragment from sandbox.dts. It shows that the SPI bus has a
72 single flash device on chip select 0 which is emulated by the driver
73 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
79 compatible = "sandbox,spi";
80 cs-gpios = <0>, <&gpio_a 0>;
83 compatible = "spansion,m25p16", "sandbox,spi-flash";
84 spi-max-frequency = <40000000>;
85 sandbox,filename = "spi.bin";
90 bool "nVidia Tegra114 SPI driver"
92 Enable the nVidia Tegra114 SPI driver. This driver can be used to
93 access the SPI NOR flash on platforms embedding this nVidia Tegra114
96 This controller is different than the older SoCs SPI controller and
97 also register interface get changed with this controller.
100 bool "nVidia Tegra20 Serial Flash controller driver"
102 Enable the nVidia Tegra20 Serial Flash controller driver. This driver
103 can be used to access the SPI NOR flash on platforms embedding this
104 nVidia Tegra20 IP core.
107 bool "nVidia Tegra20/Tegra30 SLINK driver"
109 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
110 be used to access the SPI NOR flash on platforms embedding this
111 nVidia Tegra20/Tegra30 IP cores.
114 bool "Xilinx SPI driver"
116 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
117 controller support 8 bit SPI transfers only, with or w/o FIFO.
118 For more info on Xilinx SPI Register Definitions and Overview
119 see driver file - drivers/spi/xilinx_spi.c
122 bool "Zynq SPI driver"
123 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
125 Enable the Zynq SPI driver. This driver can be used to
126 access the SPI NOR flash on platforms embedding this Zynq
132 bool "Freescale eSPI driver"
134 Enable the Freescale eSPI driver. This driver can be used to
135 access the SPI interface and SPI NOR flash on platforms embedding
136 this Freescale eSPI IP core.
139 bool "TI QSPI driver"
141 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
142 This driver support spi flash single, quad and memory reads.
144 endmenu # menu "SPI Support"