drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <usb.h>
  11 #include <malloc.h>
  12 #include <phys2bus.h>
  13 #include <usbroothubdes.h>
  14 #include <asm/io.h>
  15
  16 #include "dwc2.h"
  17
  18 /* Use only HC channel 0. */
  19 #define DWC2_HC_CHANNEL                 0
  20
  21 #define DWC2_STATUS_BUF_SIZE            64
  22 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  23
  24 /* We need doubleword-aligned buffers for DMA transfers */
  25 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
  26 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
  27
  28 #define MAX_DEVICE                      16
  29 #define MAX_ENDPOINT                    16
  30 static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  31
  32 static int root_hub_devnum;
  33
  34 static struct dwc2_core_regs *regs =
  35         (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
  36
  37 /*
  38  * DWC2 IP interface
  39  */
  40 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  41 {
  42         unsigned int timeout = 1000000;
  43         uint32_t val;
  44
  45         while (--timeout) {
  46                 val = readl(reg);
  47                 if (!set)
  48                         val = ~val;
  49
  50                 if ((val & mask) == mask)
  51                         return 0;
  52
  53                 udelay(1);
  54         }
  55
  56         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  57               __func__, reg, mask, set);
  58
  59         return -ETIMEDOUT;
  60 }
  61
  62 /*
  63  * Initializes the FSLSPClkSel field of the HCFG register
  64  * depending on the PHY type.
  65  */
  66 static void init_fslspclksel(struct dwc2_core_regs *regs)
  67 {
  68         uint32_t phyclk;
  69
  70 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  71         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  72 #else
  73         /* High speed PHY running at full speed or high speed */
  74         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  75 #endif
  76
  77 #ifdef CONFIG_DWC2_ULPI_FS_LS
  78         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  79         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  80                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  81         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  82                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  83
  84         if (hval == 2 && fval == 1)
  85                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  86 #endif
  87
  88         clrsetbits_le32(&regs->host_regs.hcfg,
  89                         DWC2_HCFG_FSLSPCLKSEL_MASK,
  90                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  91 }
  92
  93 /*
  94  * Flush a Tx FIFO.
  95  *
  96  * @param regs Programming view of DWC_otg controller.
  97  * @param num Tx FIFO to flush.
  98  */
  99 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 100 {
 101         int ret;
 102
 103         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 104                &regs->grstctl);
 105         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 106         if (ret)
 107                 printf("%s: Timeout!\n", __func__);
 108
 109         /* Wait for 3 PHY Clocks */
 110         udelay(1);
 111 }
 112
 113 /*
 114  * Flush Rx FIFO.
 115  *
 116  * @param regs Programming view of DWC_otg controller.
 117  */
 118 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 119 {
 120         int ret;
 121
 122         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 123         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 124         if (ret)
 125                 printf("%s: Timeout!\n", __func__);
 126
 127         /* Wait for 3 PHY Clocks */
 128         udelay(1);
 129 }
 130
 131 /*
 132  * Do core a soft reset of the core.  Be careful with this because it
 133  * resets all the internal state machines of the core.
 134  */
 135 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 136 {
 137         int ret;
 138
 139         /* Wait for AHB master IDLE state. */
 140         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 141         if (ret)
 142                 printf("%s: Timeout!\n", __func__);
 143
 144         /* Core Soft Reset */
 145         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 146         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 147         if (ret)
 148                 printf("%s: Timeout!\n", __func__);
 149
 150         /*
 151          * Wait for core to come out of reset.
 152          * NOTE: This long sleep is _very_ important, otherwise the core will
 153          *       not stay in host mode after a connector ID change!
 154          */
 155         mdelay(100);
 156 }
 157
 158 /*
 159  * This function initializes the DWC_otg controller registers for
 160  * host mode.
 161  *
 162  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 163  * request queues. Host channels are reset to ensure that they are ready for
 164  * performing transfers.
 165  *
 166  * @param regs Programming view of DWC_otg controller
 167  *
 168  */
 169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 170 {
 171         uint32_t nptxfifosize = 0;
 172         uint32_t ptxfifosize = 0;
 173         uint32_t hprt0 = 0;
 174         int i, ret, num_channels;
 175
 176         /* Restart the Phy Clock */
 177         writel(0, &regs->pcgcctl);
 178
 179         /* Initialize Host Configuration Register */
 180         init_fslspclksel(regs);
 181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 182         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 183 #endif
 184
 185         /* Configure data FIFO sizes */
 186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 187         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 188                 /* Rx FIFO */
 189                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 190
 191                 /* Non-periodic Tx FIFO */
 192                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 193                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 194                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 195                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 196                 writel(nptxfifosize, &regs->gnptxfsiz);
 197
 198                 /* Periodic Tx FIFO */
 199                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 200                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 201                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 202                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 203                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 204                 writel(ptxfifosize, &regs->hptxfsiz);
 205         }
 206 #endif
 207
 208         /* Clear Host Set HNP Enable in the OTG Control Register */
 209         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 210
 211         /* Make sure the FIFOs are flushed. */
 212         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 213         dwc_otg_flush_rx_fifo(regs);
 214
 215         /* Flush out any leftover queued requests. */
 216         num_channels = readl(&regs->ghwcfg2);
 217         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 218         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 219         num_channels += 1;
 220
 221         for (i = 0; i < num_channels; i++)
 222                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 223                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 224                                 DWC2_HCCHAR_CHDIS);
 225
 226         /* Halt all channels to put them into a known state. */
 227         for (i = 0; i < num_channels; i++) {
 228                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 229                                 DWC2_HCCHAR_EPDIR,
 230                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 231                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 232                                    DWC2_HCCHAR_CHEN, 0);
 233                 if (ret)
 234                         printf("%s: Timeout!\n", __func__);
 235         }
 236
 237         /* Turn on the vbus power. */
 238         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 239                 hprt0 = readl(&regs->hprt0);
 240                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 241                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 242                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 243                         hprt0 |= DWC2_HPRT0_PRTPWR;
 244                         writel(hprt0, &regs->hprt0);
 245                 }
 246         }
 247 }
 248
 249 /*
 250  * This function initializes the DWC_otg controller registers and
 251  * prepares the core for device mode or host mode operation.
 252  *
 253  * @param regs Programming view of the DWC_otg controller
 254  */
 255 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 256 {
 257         uint32_t ahbcfg = 0;
 258         uint32_t usbcfg = 0;
 259         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 260
 261         /* Common Initialization */
 262         usbcfg = readl(&regs->gusbcfg);
 263
 264         /* Program the ULPI External VBUS bit if needed */
 265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 266         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 267 #else
 268         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 269 #endif
 270
 271         /* Set external TS Dline pulsing */
 272 #ifdef CONFIG_DWC2_TS_DLINE
 273         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 274 #else
 275         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 276 #endif
 277         writel(usbcfg, &regs->gusbcfg);
 278
 279         /* Reset the Controller */
 280         dwc_otg_core_reset(regs);
 281
 282         /*
 283          * This programming sequence needs to happen in FS mode before
 284          * any other programming occurs
 285          */
 286 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 287         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 288         /* If FS mode with FS PHY */
 289         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 290
 291         /* Reset after a PHY select */
 292         dwc_otg_core_reset(regs);
 293
 294         /*
 295          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 296          * Also do this on HNP Dev/Host mode switches (done in dev_init
 297          * and host_init).
 298          */
 299         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 300                 init_fslspclksel(regs);
 301
 302 #ifdef CONFIG_DWC2_I2C_ENABLE
 303         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 304         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 305
 306         /* Program GI2CCTL.I2CEn */
 307         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 308                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 309                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 310         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 311 #endif
 312
 313 #else
 314         /* High speed PHY. */
 315
 316         /*
 317          * HS PHY parameters. These parameters are preserved during
 318          * soft reset so only program the first time. Do a soft reset
 319          * immediately after setting phyif.
 320          */
 321         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 322         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 323
 324         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 325 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 326                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 327 #else
 328                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 329 #endif
 330         } else {        /* UTMI+ interface */
 331 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 332                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 333 #endif
 334         }
 335
 336         writel(usbcfg, &regs->gusbcfg);
 337
 338         /* Reset after setting the PHY parameters */
 339         dwc_otg_core_reset(regs);
 340 #endif
 341
 342         usbcfg = readl(&regs->gusbcfg);
 343         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 344 #ifdef CONFIG_DWC2_ULPI_FS_LS
 345         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 346         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 347                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 348         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 349                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 350         if (hval == 2 && fval == 1) {
 351                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 352                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 353         }
 354 #endif
 355         writel(usbcfg, &regs->gusbcfg);
 356
 357         /* Program the GAHBCFG Register. */
 358         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 359         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 360                 break;
 361         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 362                 while (brst_sz > 1) {
 363                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 364                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 365                         brst_sz >>= 1;
 366                 }
 367
 368 #ifdef CONFIG_DWC2_DMA_ENABLE
 369                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 370 #endif
 371                 break;
 372
 373         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 374                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 375 #ifdef CONFIG_DWC2_DMA_ENABLE
 376                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 377 #endif
 378                 break;
 379         }
 380
 381         writel(ahbcfg, &regs->gahbcfg);
 382
 383         /* Program the GUSBCFG register for HNP/SRP. */
 384         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 385
 386 #ifdef CONFIG_DWC2_IC_USB_CAP
 387         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 388 #endif
 389 }
 390
 391 /*
 392  * Prepares a host channel for transferring packets to/from a specific
 393  * endpoint. The HCCHARn register is set up with the characteristics specified
 394  * in _hc. Host channel interrupts that may need to be serviced while this
 395  * transfer is in progress are enabled.
 396  *
 397  * @param regs Programming view of DWC_otg controller
 398  * @param hc Information needed to initialize the host channel
 399  */
 400 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 401                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 402                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 403 {
 404         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 405         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 406                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 407                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 408                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 409                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 410
 411         if (dev->speed == USB_SPEED_LOW)
 412                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 413
 414         /* Clear old interrupt conditions for this host channel. */
 415         writel(0x3fff, &hc_regs->hcint);
 416
 417         /*
 418          * Program the HCCHARn register with the endpoint characteristics
 419          * for the current transfer.
 420          */
 421         writel(hcchar, &hc_regs->hcchar);
 422
 423         /* Program the HCSPLIT register for SPLITs */
 424         writel(0, &hc_regs->hcsplt);
 425 }
 426
 427 /*
 428  * DWC2 to USB API interface
 429  */
 430 /* Direction: In ; Request: Status */
 431 static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
 432                                            int txlen, struct devrequest *cmd)
 433 {
 434         uint32_t hprt0 = 0;
 435         uint32_t port_status = 0;
 436         uint32_t port_change = 0;
 437         int len = 0;
 438         int stat = 0;
 439
 440         switch (cmd->requesttype & ~USB_DIR_IN) {
 441         case 0:
 442                 *(uint16_t *)buffer = cpu_to_le16(1);
 443                 len = 2;
 444                 break;
 445         case USB_RECIP_INTERFACE:
 446         case USB_RECIP_ENDPOINT:
 447                 *(uint16_t *)buffer = cpu_to_le16(0);
 448                 len = 2;
 449                 break;
 450         case USB_TYPE_CLASS:
 451                 *(uint32_t *)buffer = cpu_to_le32(0);
 452                 len = 4;
 453                 break;
 454         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 455                 hprt0 = readl(&regs->hprt0);
 456                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 457                         port_status |= USB_PORT_STAT_CONNECTION;
 458                 if (hprt0 & DWC2_HPRT0_PRTENA)
 459                         port_status |= USB_PORT_STAT_ENABLE;
 460                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 461                         port_status |= USB_PORT_STAT_SUSPEND;
 462                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 463                         port_status |= USB_PORT_STAT_OVERCURRENT;
 464                 if (hprt0 & DWC2_HPRT0_PRTRST)
 465                         port_status |= USB_PORT_STAT_RESET;
 466                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 467                         port_status |= USB_PORT_STAT_POWER;
 468
 469                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 470                         port_status |= USB_PORT_STAT_LOW_SPEED;
 471                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 472                          DWC2_HPRT0_PRTSPD_HIGH)
 473                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 474
 475                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 476                         port_change |= USB_PORT_STAT_C_ENABLE;
 477                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 478                         port_change |= USB_PORT_STAT_C_CONNECTION;
 479                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 480                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 481
 482                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 483                                         (port_change << 16));
 484                 len = 4;
 485                 break;
 486         default:
 487                 puts("unsupported root hub command\n");
 488                 stat = USB_ST_STALLED;
 489         }
 490
 491         dev->act_len = min(len, txlen);
 492         dev->status = stat;
 493
 494         return stat;
 495 }
 496
 497 /* Direction: In ; Request: Descriptor */
 498 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 499                                                void *buffer, int txlen,
 500                                                struct devrequest *cmd)
 501 {
 502         unsigned char data[32];
 503         uint32_t dsc;
 504         int len = 0;
 505         int stat = 0;
 506         uint16_t wValue = cpu_to_le16(cmd->value);
 507         uint16_t wLength = cpu_to_le16(cmd->length);
 508
 509         switch (cmd->requesttype & ~USB_DIR_IN) {
 510         case 0:
 511                 switch (wValue & 0xff00) {
 512                 case 0x0100:    /* device descriptor */
 513                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 514                         memcpy(buffer, root_hub_dev_des, len);
 515                         break;
 516                 case 0x0200:    /* configuration descriptor */
 517                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 518                         memcpy(buffer, root_hub_config_des, len);
 519                         break;
 520                 case 0x0300:    /* string descriptors */
 521                         switch (wValue & 0xff) {
 522                         case 0x00:
 523                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 524                                            (int)wLength);
 525                                 memcpy(buffer, root_hub_str_index0, len);
 526                                 break;
 527                         case 0x01:
 528                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 529                                            (int)wLength);
 530                                 memcpy(buffer, root_hub_str_index1, len);
 531                                 break;
 532                         }
 533                         break;
 534                 default:
 535                         stat = USB_ST_STALLED;
 536                 }
 537                 break;
 538
 539         case USB_TYPE_CLASS:
 540                 /* Root port config, set 1 port and nothing else. */
 541                 dsc = 0x00000001;
 542
 543                 data[0] = 9;            /* min length; */
 544                 data[1] = 0x29;
 545                 data[2] = dsc & RH_A_NDP;
 546                 data[3] = 0;
 547                 if (dsc & RH_A_PSM)
 548                         data[3] |= 0x1;
 549                 if (dsc & RH_A_NOCP)
 550                         data[3] |= 0x10;
 551                 else if (dsc & RH_A_OCPM)
 552                         data[3] |= 0x8;
 553
 554                 /* corresponds to data[4-7] */
 555                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 556                 data[7] = dsc & RH_B_DR;
 557                 if (data[2] < 7) {
 558                         data[8] = 0xff;
 559                 } else {
 560                         data[0] += 2;
 561                         data[8] = (dsc & RH_B_DR) >> 8;
 562                         data[9] = 0xff;
 563                         data[10] = data[9];
 564                 }
 565
 566                 len = min3(txlen, (int)data[0], (int)wLength);
 567                 memcpy(buffer, data, len);
 568                 break;
 569         default:
 570                 puts("unsupported root hub command\n");
 571                 stat = USB_ST_STALLED;
 572         }
 573
 574         dev->act_len = min(len, txlen);
 575         dev->status = stat;
 576
 577         return stat;
 578 }
 579
 580 /* Direction: In ; Request: Configuration */
 581 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 582                                                   void *buffer, int txlen,
 583                                                   struct devrequest *cmd)
 584 {
 585         int len = 0;
 586         int stat = 0;
 587
 588         switch (cmd->requesttype & ~USB_DIR_IN) {
 589         case 0:
 590                 *(uint8_t *)buffer = 0x01;
 591                 len = 1;
 592                 break;
 593         default:
 594                 puts("unsupported root hub command\n");
 595                 stat = USB_ST_STALLED;
 596         }
 597
 598         dev->act_len = min(len, txlen);
 599         dev->status = stat;
 600
 601         return stat;
 602 }
 603
 604 /* Direction: In */
 605 static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
 606                                  void *buffer, int txlen,
 607                                  struct devrequest *cmd)
 608 {
 609         switch (cmd->request) {
 610         case USB_REQ_GET_STATUS:
 611                 return dwc_otg_submit_rh_msg_in_status(dev, buffer,
 612                                                        txlen, cmd);
 613         case USB_REQ_GET_DESCRIPTOR:
 614                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 615                                                            txlen, cmd);
 616         case USB_REQ_GET_CONFIGURATION:
 617                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 618                                                               txlen, cmd);
 619         default:
 620                 puts("unsupported root hub command\n");
 621                 return USB_ST_STALLED;
 622         }
 623 }
 624
 625 /* Direction: Out */
 626 static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
 627                                  void *buffer, int txlen,
 628                                  struct devrequest *cmd)
 629 {
 630         int len = 0;
 631         int stat = 0;
 632         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 633         uint16_t wValue = cpu_to_le16(cmd->value);
 634
 635         switch (bmrtype_breq & ~USB_DIR_IN) {
 636         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 637         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 638                 break;
 639
 640         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 641                 switch (wValue) {
 642                 case USB_PORT_FEAT_C_CONNECTION:
 643                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 644                         break;
 645                 }
 646                 break;
 647
 648         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 649                 switch (wValue) {
 650                 case USB_PORT_FEAT_SUSPEND:
 651                         break;
 652
 653                 case USB_PORT_FEAT_RESET:
 654                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 655                                         DWC2_HPRT0_PRTCONNDET |
 656                                         DWC2_HPRT0_PRTENCHNG |
 657                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 658                                         DWC2_HPRT0_PRTRST);
 659                         mdelay(50);
 660                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 661                         break;
 662
 663                 case USB_PORT_FEAT_POWER:
 664                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 665                                         DWC2_HPRT0_PRTCONNDET |
 666                                         DWC2_HPRT0_PRTENCHNG |
 667                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 668                                         DWC2_HPRT0_PRTRST);
 669                         break;
 670
 671                 case USB_PORT_FEAT_ENABLE:
 672                         break;
 673                 }
 674                 break;
 675         case (USB_REQ_SET_ADDRESS << 8):
 676                 root_hub_devnum = wValue;
 677                 break;
 678         case (USB_REQ_SET_CONFIGURATION << 8):
 679                 break;
 680         default:
 681                 puts("unsupported root hub command\n");
 682                 stat = USB_ST_STALLED;
 683         }
 684
 685         len = min(len, txlen);
 686
 687         dev->act_len = len;
 688         dev->status = stat;
 689
 690         return stat;
 691 }
 692
 693 static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 694                                  void *buffer, int txlen,
 695                                  struct devrequest *cmd)
 696 {
 697         int stat = 0;
 698
 699         if (usb_pipeint(pipe)) {
 700                 puts("Root-Hub submit IRQ: NOT implemented\n");
 701                 return 0;
 702         }
 703
 704         if (cmd->requesttype & USB_DIR_IN)
 705                 stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
 706         else
 707                 stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
 708
 709         mdelay(1);
 710
 711         return stat;
 712 }
 713
 714 int wait_for_chhltd(uint32_t *sub, int *toggle, bool ignore_ack)
 715 {
 716         uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
 717         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 718         int ret;
 719         uint32_t hcint, hctsiz;
 720
 721         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 722         if (ret)
 723                 return ret;
 724
 725         hcint = readl(&hc_regs->hcint);
 726         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 727                 return -EAGAIN;
 728         if (ignore_ack)
 729                 hcint &= ~DWC2_HCINT_ACK;
 730         else
 731                 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
 732         if (hcint != hcint_comp_hlt_ack) {
 733                 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 734                 return -EINVAL;
 735         }
 736
 737         hctsiz = readl(&hc_regs->hctsiz);
 738         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 739                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 740         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 741
 742         debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
 743
 744         return 0;
 745 }
 746
 747 static int dwc2_eptype[] = {
 748         DWC2_HCCHAR_EPTYPE_ISOC,
 749         DWC2_HCCHAR_EPTYPE_INTR,
 750         DWC2_HCCHAR_EPTYPE_CONTROL,
 751         DWC2_HCCHAR_EPTYPE_BULK,
 752 };
 753
 754 int chunk_msg(struct usb_device *dev, unsigned long pipe, int *pid, int in,
 755               void *buffer, int len, bool ignore_ack)
 756 {
 757         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 758         int devnum = usb_pipedevice(pipe);
 759         int ep = usb_pipeendpoint(pipe);
 760         int max = usb_maxpacket(dev, pipe);
 761         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 762         int done = 0;
 763         int ret = 0;
 764         uint32_t sub;
 765         uint32_t xfer_len;
 766         uint32_t num_packets;
 767         int stop_transfer = 0;
 768
 769         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 770               in, len);
 771
 772         do {
 773                 /* Initialize channel */
 774                 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 775                                 eptype, max);
 776
 777                 xfer_len = len - done;
 778                 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 779                         xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
 780                 if (xfer_len > DWC2_DATA_BUF_SIZE)
 781                         xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 782
 783                 /* Make sure that xfer_len is a multiple of max packet size. */
 784                 if (xfer_len > 0) {
 785                         num_packets = (xfer_len + max - 1) / max;
 786                         if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
 787                                 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
 788                                 xfer_len = num_packets * max;
 789                         }
 790                 } else {
 791                         num_packets = 1;
 792                 }
 793
 794                 if (in)
 795                         xfer_len = num_packets * max;
 796
 797                 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 798                       *pid, xfer_len, num_packets);
 799
 800                 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 801                        (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 802                        (*pid << DWC2_HCTSIZ_PID_OFFSET),
 803                        &hc_regs->hctsiz);
 804
 805                 if (!in)
 806                         memcpy(aligned_buffer, (char *)buffer + done, len);
 807
 808                 writel(phys_to_bus((unsigned long)aligned_buffer),
 809                        &hc_regs->hcdma);
 810
 811                 /* Set host channel enable after all other setup is complete. */
 812                 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 813                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 814                                 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 815                                 DWC2_HCCHAR_CHEN);
 816
 817                 ret = wait_for_chhltd(&sub, pid, ignore_ack);
 818                 if (ret)
 819                         break;
 820
 821                 if (in) {
 822                         xfer_len -= sub;
 823                         memcpy(buffer + done, aligned_buffer, xfer_len);
 824                         if (sub)
 825                                 stop_transfer = 1;
 826                 }
 827
 828                 done += xfer_len;
 829
 830         } while ((done < len) && !stop_transfer);
 831
 832         writel(0, &hc_regs->hcintmsk);
 833         writel(0xFFFFFFFF, &hc_regs->hcint);
 834
 835         dev->status = 0;
 836         dev->act_len = done;
 837
 838         return ret;
 839 }
 840
 841 /* U-Boot USB transmission interface */
 842 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 843                     int len)
 844 {
 845         int devnum = usb_pipedevice(pipe);
 846         int ep = usb_pipeendpoint(pipe);
 847
 848         if (devnum == root_hub_devnum) {
 849                 dev->status = 0;
 850                 return -EINVAL;
 851         }
 852
 853         return chunk_msg(dev, pipe, &bulk_data_toggle[devnum][ep],
 854                          usb_pipein(pipe), buffer, len, true);
 855 }
 856
 857 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 858                        int len, struct devrequest *setup)
 859 {
 860         int devnum = usb_pipedevice(pipe);
 861         int pid, ret, act_len;
 862         /* For CONTROL endpoint pid should start with DATA1 */
 863         int status_direction;
 864
 865         if (devnum == root_hub_devnum) {
 866                 dev->status = 0;
 867                 dev->speed = USB_SPEED_HIGH;
 868                 return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
 869         }
 870
 871         pid = DWC2_HC_PID_SETUP;
 872         ret = chunk_msg(dev, pipe, &pid, 0, setup, 8, true);
 873         if (ret)
 874                 return ret;
 875
 876         if (buffer) {
 877                 pid = DWC2_HC_PID_DATA1;
 878                 ret = chunk_msg(dev, pipe, &pid, usb_pipein(pipe), buffer,
 879                                 len, false);
 880                 if (ret)
 881                         return ret;
 882                 act_len = dev->act_len;
 883         } /* End of DATA stage */
 884         else
 885                 act_len = 0;
 886
 887         /* STATUS stage */
 888         if ((len == 0) || usb_pipeout(pipe))
 889                 status_direction = 1;
 890         else
 891                 status_direction = 0;
 892
 893         pid = DWC2_HC_PID_DATA1;
 894         ret = chunk_msg(dev, pipe, &pid, status_direction, status_buffer, 0,
 895                 false);
 896         if (ret)
 897                 return ret;
 898
 899         dev->act_len = act_len;
 900
 901         return 0;
 902 }
 903
 904 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 905                    int len, int interval)
 906 {
 907         unsigned long timeout;
 908         int ret;
 909
 910         /* FIXME: what is interval? */
 911
 912         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 913         for (;;) {
 914                 if (get_timer(0) > timeout) {
 915                         printf("Timeout poll on interrupt endpoint\n");
 916                         return -ETIMEDOUT;
 917                 }
 918                 ret = submit_bulk_msg(dev, pipe, buffer, len);
 919                 if (ret != -EAGAIN)
 920                         return ret;
 921         }
 922 }
 923
 924 /* U-Boot USB control interface */
 925 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 926 {
 927         uint32_t snpsid;
 928         int i, j;
 929
 930         root_hub_devnum = 0;
 931
 932         /*  board dependant init */
 933         if (board_usb_init(index, USB_INIT_HOST))
 934                 return -1;
 935
 936         snpsid = readl(&regs->gsnpsid);
 937         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
 938
 939         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
 940             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
 941                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
 942                 return -ENODEV;
 943         }
 944
 945         dwc_otg_core_init(regs);
 946         dwc_otg_core_host_init(regs);
 947
 948         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 949                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 950                         DWC2_HPRT0_PRTOVRCURRCHNG,
 951                         DWC2_HPRT0_PRTRST);
 952         mdelay(50);
 953         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
 954                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
 955                      DWC2_HPRT0_PRTRST);
 956
 957         for (i = 0; i < MAX_DEVICE; i++) {
 958                 for (j = 0; j < MAX_ENDPOINT; j++)
 959                         bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
 960         }
 961
 962         return 0;
 963 }
 964
 965 int usb_lowlevel_stop(int index)
 966 {
 967         /* Put everything in reset. */
 968         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 969                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 970                         DWC2_HPRT0_PRTOVRCURRCHNG,
 971                         DWC2_HPRT0_PRTRST);
 972         return 0;
 973 }