drivers/usb/host/ohci-hcd.c

   1 /*
   2  * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
   3  *
   4  * Interrupt support is added. Now, it has been tested
   5  * on ULI1575 chip and works well with USB keyboard.
   6  *
   7  * (C) Copyright 2007
   8  * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
   9  *
  10  * (C) Copyright 2003
  11  * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  12  *
  13  * Note: Much of this code has been derived from Linux 2.4
  14  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  15  * (C) Copyright 2000-2002 David Brownell
  16  *
  17  * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  18  * ebenard@eukrea.com - based on s3c24x0's driver
  19  *
  20  * SPDX-License-Identifier:     GPL-2.0+
  21  */
  22 /*
  23  * IMPORTANT NOTES
  24  * 1 - Read doc/README.generic_usb_ohci
  25  * 2 - this driver is intended for use with USB Mass Storage Devices
  26  *     (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  27  * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  28  *     to activate workaround for bug #41 or this driver will NOT work!
  29  */
  30
  31 #include <common.h>
  32 #include <asm/byteorder.h>
  33
  34 #if defined(CONFIG_PCI_OHCI)
  35 # include <pci.h>
  36 #if !defined(CONFIG_PCI_OHCI_DEVNO)
  37 #define CONFIG_PCI_OHCI_DEVNO   0
  38 #endif
  39 #endif
  40
  41 #include <malloc.h>
  42 #include <usb.h>
  43
  44 #include "ohci.h"
  45
  46 #ifdef CONFIG_AT91RM9200
  47 #include <asm/arch/hardware.h>  /* needed for AT91_USB_HOST_BASE */
  48 #endif
  49
  50 #if defined(CONFIG_CPU_ARM920T) || \
  51     defined(CONFIG_S3C24X0) || \
  52     defined(CONFIG_440EP) || \
  53     defined(CONFIG_PCI_OHCI) || \
  54     defined(CONFIG_MPC5200) || \
  55     defined(CONFIG_SYS_OHCI_USE_NPS)
  56 # define OHCI_USE_NPS           /* force NoPowerSwitching mode */
  57 #endif
  58
  59 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  60 #undef DEBUG
  61 #undef SHOW_INFO
  62 #undef OHCI_FILL_TRACE
  63
  64 /* For initializing controller (mask in an HCFS mode too) */
  65 #define OHCI_CONTROL_INIT \
  66         (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  67
  68 #ifdef CONFIG_PCI_OHCI
  69 static struct pci_device_id ohci_pci_ids[] = {
  70         {0x10b9, 0x5237},       /* ULI1575 PCI OHCI module ids */
  71         {0x1033, 0x0035},       /* NEC PCI OHCI module ids */
  72         {0x1131, 0x1561},       /* Philips 1561 PCI OHCI module ids */
  73         /* Please add supported PCI OHCI controller ids here */
  74         {0, 0}
  75 };
  76 #endif
  77
  78 #ifdef CONFIG_PCI_EHCI_DEVNO
  79 static struct pci_device_id ehci_pci_ids[] = {
  80         {0x1131, 0x1562},       /* Philips 1562 PCI EHCI module ids */
  81         /* Please add supported PCI EHCI controller ids here */
  82         {0, 0}
  83 };
  84 #endif
  85
  86 #ifdef DEBUG
  87 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  88 #else
  89 #define dbg(format, arg...) do {} while (0)
  90 #endif /* DEBUG */
  91 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  92 #ifdef SHOW_INFO
  93 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  94 #else
  95 #define info(format, arg...) do {} while (0)
  96 #endif
  97
  98 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
  99 # define m16_swap(x) cpu_to_be16(x)
 100 # define m32_swap(x) cpu_to_be32(x)
 101 #else
 102 # define m16_swap(x) cpu_to_le16(x)
 103 # define m32_swap(x) cpu_to_le32(x)
 104 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
 105
 106 #ifdef CONFIG_DM_USB
 107 /*
 108  * We really should do proper cache flushing everywhere, but for now we only
 109  * do it for new (driver-model) usb code to avoid regressions.
 110  */
 111 #define flush_dcache_buffer(addr, size) \
 112         flush_dcache_range((unsigned long)(addr), \
 113                 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
 114 #define invalidate_dcache_buffer(addr, size) \
 115         invalidate_dcache_range((unsigned long)(addr), \
 116                 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
 117 #else
 118 #define flush_dcache_buffer(addr, size)
 119 #define invalidate_dcache_buffer(addr, size)
 120 #endif
 121
 122 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
 123 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
 124 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
 125 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
 126 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
 127 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
 128 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
 129 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
 130 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
 131
 132 /* global ohci_t */
 133 static ohci_t gohci;
 134 /* this must be aligned to a 256 byte boundary */
 135 struct ohci_hcca ghcca[1];
 136
 137 /* mapping of the OHCI CC status to error codes */
 138 static int cc_to_error[16] = {
 139         /* No  Error  */               0,
 140         /* CRC Error  */               USB_ST_CRC_ERR,
 141         /* Bit Stuff  */               USB_ST_BIT_ERR,
 142         /* Data Togg  */               USB_ST_CRC_ERR,
 143         /* Stall      */               USB_ST_STALLED,
 144         /* DevNotResp */               -1,
 145         /* PIDCheck   */               USB_ST_BIT_ERR,
 146         /* UnExpPID   */               USB_ST_BIT_ERR,
 147         /* DataOver   */               USB_ST_BUF_ERR,
 148         /* DataUnder  */               USB_ST_BUF_ERR,
 149         /* reservd    */               -1,
 150         /* reservd    */               -1,
 151         /* BufferOver */               USB_ST_BUF_ERR,
 152         /* BuffUnder  */               USB_ST_BUF_ERR,
 153         /* Not Access */               -1,
 154         /* Not Access */               -1
 155 };
 156
 157 static const char *cc_to_string[16] = {
 158         "No Error",
 159         "CRC: Last data packet from endpoint contained a CRC error.",
 160         "BITSTUFFING: Last data packet from endpoint contained a bit " \
 161                      "stuffing violation",
 162         "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
 163                      "that did not match the expected value.",
 164         "STALL: TD was moved to the Done Queue because the endpoint returned" \
 165                      " a STALL PID",
 166         "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
 167                      "not provide a handshake (OUT)",
 168         "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
 169                      "(IN) or handshake (OUT)",
 170         "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
 171                      "value is not defined.",
 172         "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
 173                      "either the size of the maximum data packet allowed\n" \
 174                      "from the endpoint (found in MaximumPacketSize field\n" \
 175                      "of ED) or the remaining buffer size.",
 176         "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
 177                      "and that amount was not sufficient to fill the\n" \
 178                      "specified buffer",
 179         "reserved1",
 180         "reserved2",
 181         "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
 182                      "than it could be written to system memory",
 183         "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
 184                      "system memory fast enough to keep up with data USB " \
 185                      "data rate.",
 186         "NOT ACCESSED: This code is set by software before the TD is placed" \
 187                      "on a list to be processed by the HC.(1)",
 188         "NOT ACCESSED: This code is set by software before the TD is placed" \
 189                      "on a list to be processed by the HC.(2)",
 190 };
 191
 192 static inline u32 roothub_a(struct ohci *hc)
 193         { return ohci_readl(&hc->regs->roothub.a); }
 194 static inline u32 roothub_b(struct ohci *hc)
 195         { return ohci_readl(&hc->regs->roothub.b); }
 196 static inline u32 roothub_status(struct ohci *hc)
 197         { return ohci_readl(&hc->regs->roothub.status); }
 198 static inline u32 roothub_portstatus(struct ohci *hc, int i)
 199         { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
 200
 201 /* forward declaration */
 202 static int hc_interrupt(ohci_t *ohci);
 203 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
 204                           unsigned long pipe, void *buffer, int transfer_len,
 205                           struct devrequest *setup, urb_priv_t *urb,
 206                           int interval);
 207 static int ep_link(ohci_t * ohci, ed_t * ed);
 208 static int ep_unlink(ohci_t * ohci, ed_t * ed);
 209 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
 210                        unsigned long pipe, int interval, int load);
 211
 212 /*-------------------------------------------------------------------------*/
 213
 214 /* TDs ... */
 215 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
 216 {
 217         int i;
 218         struct td *td;
 219
 220         td = NULL;
 221         for (i = 0; i < NUM_TD; i++)
 222         {
 223                 if (ohci_dev->tds[i].usb_dev == NULL)
 224                 {
 225                         td = &ohci_dev->tds[i];
 226                         td->usb_dev = usb_dev;
 227                         break;
 228                 }
 229         }
 230
 231         return td;
 232 }
 233
 234 static inline void ed_free(struct ed *ed)
 235 {
 236         ed->usb_dev = NULL;
 237 }
 238
 239 /*-------------------------------------------------------------------------*
 240  * URB support functions
 241  *-------------------------------------------------------------------------*/
 242
 243 /* free HCD-private data associated with this URB */
 244
 245 static void urb_free_priv(urb_priv_t *urb)
 246 {
 247         int             i;
 248         int             last;
 249         struct td       *td;
 250
 251         last = urb->length - 1;
 252         if (last >= 0) {
 253                 for (i = 0; i <= last; i++) {
 254                         td = urb->td[i];
 255                         if (td) {
 256                                 td->usb_dev = NULL;
 257                                 urb->td[i] = NULL;
 258                         }
 259                 }
 260         }
 261         free(urb);
 262 }
 263
 264 /*-------------------------------------------------------------------------*/
 265
 266 #ifdef DEBUG
 267 static int sohci_get_current_frame_number(ohci_t *ohci);
 268
 269 /* debug| print the main components of an URB
 270  * small: 0) header + data packets 1) just header */
 271
 272 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
 273                       unsigned long pipe, void *buffer, int transfer_len,
 274                       struct devrequest *setup, char *str, int small)
 275 {
 276         dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
 277                         str,
 278                         sohci_get_current_frame_number(ohci),
 279                         usb_pipedevice(pipe),
 280                         usb_pipeendpoint(pipe),
 281                         usb_pipeout(pipe)? 'O': 'I',
 282                         usb_pipetype(pipe) < 2 ? \
 283                                 (usb_pipeint(pipe)? "INTR": "ISOC"): \
 284                                 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
 285                         (purb ? purb->actual_length : 0),
 286                         transfer_len, dev->status);
 287 #ifdef  OHCI_VERBOSE_DEBUG
 288         if (!small) {
 289                 int i, len;
 290
 291                 if (usb_pipecontrol(pipe)) {
 292                         printf(__FILE__ ": cmd(8):");
 293                         for (i = 0; i < 8 ; i++)
 294                                 printf(" %02x", ((__u8 *) setup) [i]);
 295                         printf("\n");
 296                 }
 297                 if (transfer_len > 0 && buffer) {
 298                         printf(__FILE__ ": data(%d/%d):",
 299                                 (purb ? purb->actual_length : 0),
 300                                 transfer_len);
 301                         len = usb_pipeout(pipe)? transfer_len:
 302                                         (purb ? purb->actual_length : 0);
 303                         for (i = 0; i < 16 && i < len; i++)
 304                                 printf(" %02x", ((__u8 *) buffer) [i]);
 305                         printf("%s\n", i < len? "...": "");
 306                 }
 307         }
 308 #endif
 309 }
 310
 311 /* just for debugging; prints non-empty branches of the int ed tree
 312  * inclusive iso eds */
 313 void ep_print_int_eds(ohci_t *ohci, char *str)
 314 {
 315         int i, j;
 316          __u32 *ed_p;
 317         for (i = 0; i < 32; i++) {
 318                 j = 5;
 319                 ed_p = &(ohci->hcca->int_table [i]);
 320                 if (*ed_p == 0)
 321                     continue;
 322                 invalidate_dcache_ed(ed_p);
 323                 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
 324                 while (*ed_p != 0 && j--) {
 325                         ed_t *ed = (ed_t *)m32_swap(ed_p);
 326                         invalidate_dcache_ed(ed);
 327                         printf(" ed: %4x;", ed->hwINFO);
 328                         ed_p = &ed->hwNextED;
 329                 }
 330                 printf("\n");
 331         }
 332 }
 333
 334 static void ohci_dump_intr_mask(char *label, __u32 mask)
 335 {
 336         dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
 337                 label,
 338                 mask,
 339                 (mask & OHCI_INTR_MIE) ? " MIE" : "",
 340                 (mask & OHCI_INTR_OC) ? " OC" : "",
 341                 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
 342                 (mask & OHCI_INTR_FNO) ? " FNO" : "",
 343                 (mask & OHCI_INTR_UE) ? " UE" : "",
 344                 (mask & OHCI_INTR_RD) ? " RD" : "",
 345                 (mask & OHCI_INTR_SF) ? " SF" : "",
 346                 (mask & OHCI_INTR_WDH) ? " WDH" : "",
 347                 (mask & OHCI_INTR_SO) ? " SO" : ""
 348                 );
 349 }
 350
 351 static void maybe_print_eds(char *label, __u32 value)
 352 {
 353         ed_t *edp = (ed_t *)value;
 354
 355         if (value) {
 356                 dbg("%s %08x", label, value);
 357                 invalidate_dcache_ed(edp);
 358                 dbg("%08x", edp->hwINFO);
 359                 dbg("%08x", edp->hwTailP);
 360                 dbg("%08x", edp->hwHeadP);
 361                 dbg("%08x", edp->hwNextED);
 362         }
 363 }
 364
 365 static char *hcfs2string(int state)
 366 {
 367         switch (state) {
 368         case OHCI_USB_RESET:    return "reset";
 369         case OHCI_USB_RESUME:   return "resume";
 370         case OHCI_USB_OPER:     return "operational";
 371         case OHCI_USB_SUSPEND:  return "suspend";
 372         }
 373         return "?";
 374 }
 375
 376 /* dump control and status registers */
 377 static void ohci_dump_status(ohci_t *controller)
 378 {
 379         struct ohci_regs        *regs = controller->regs;
 380         __u32                   temp;
 381
 382         temp = ohci_readl(&regs->revision) & 0xff;
 383         if (temp != 0x10)
 384                 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
 385
 386         temp = ohci_readl(&regs->control);
 387         dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 388                 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
 389                 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
 390                 (temp & OHCI_CTRL_IR) ? " IR" : "",
 391                 hcfs2string(temp & OHCI_CTRL_HCFS),
 392                 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
 393                 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
 394                 (temp & OHCI_CTRL_IE) ? " IE" : "",
 395                 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
 396                 temp & OHCI_CTRL_CBSR
 397                 );
 398
 399         temp = ohci_readl(&regs->cmdstatus);
 400         dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 401                 (temp & OHCI_SOC) >> 16,
 402                 (temp & OHCI_OCR) ? " OCR" : "",
 403                 (temp & OHCI_BLF) ? " BLF" : "",
 404                 (temp & OHCI_CLF) ? " CLF" : "",
 405                 (temp & OHCI_HCR) ? " HCR" : ""
 406                 );
 407
 408         ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
 409         ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
 410
 411         maybe_print_eds("ed_periodcurrent",
 412                         ohci_readl(&regs->ed_periodcurrent));
 413
 414         maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
 415         maybe_print_eds("ed_controlcurrent",
 416                         ohci_readl(&regs->ed_controlcurrent));
 417
 418         maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
 419         maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
 420
 421         maybe_print_eds("donehead", ohci_readl(&regs->donehead));
 422 }
 423
 424 static void ohci_dump_roothub(ohci_t *controller, int verbose)
 425 {
 426         __u32                   temp, ndp, i;
 427
 428         temp = roothub_a(controller);
 429         ndp = (temp & RH_A_NDP);
 430 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 431         ndp = (ndp == 2) ? 1:0;
 432 #endif
 433         if (verbose) {
 434                 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
 435                         ((temp & RH_A_POTPGT) >> 24) & 0xff,
 436                         (temp & RH_A_NOCP) ? " NOCP" : "",
 437                         (temp & RH_A_OCPM) ? " OCPM" : "",
 438                         (temp & RH_A_DT) ? " DT" : "",
 439                         (temp & RH_A_NPS) ? " NPS" : "",
 440                         (temp & RH_A_PSM) ? " PSM" : "",
 441                         ndp
 442                         );
 443                 temp = roothub_b(controller);
 444                 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
 445                         temp,
 446                         (temp & RH_B_PPCM) >> 16,
 447                         (temp & RH_B_DR)
 448                         );
 449                 temp = roothub_status(controller);
 450                 dbg("roothub.status: %08x%s%s%s%s%s%s",
 451                         temp,
 452                         (temp & RH_HS_CRWE) ? " CRWE" : "",
 453                         (temp & RH_HS_OCIC) ? " OCIC" : "",
 454                         (temp & RH_HS_LPSC) ? " LPSC" : "",
 455                         (temp & RH_HS_DRWE) ? " DRWE" : "",
 456                         (temp & RH_HS_OCI) ? " OCI" : "",
 457                         (temp & RH_HS_LPS) ? " LPS" : ""
 458                         );
 459         }
 460
 461         for (i = 0; i < ndp; i++) {
 462                 temp = roothub_portstatus(controller, i);
 463                 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
 464                         i,
 465                         temp,
 466                         (temp & RH_PS_PRSC) ? " PRSC" : "",
 467                         (temp & RH_PS_OCIC) ? " OCIC" : "",
 468                         (temp & RH_PS_PSSC) ? " PSSC" : "",
 469                         (temp & RH_PS_PESC) ? " PESC" : "",
 470                         (temp & RH_PS_CSC) ? " CSC" : "",
 471
 472                         (temp & RH_PS_LSDA) ? " LSDA" : "",
 473                         (temp & RH_PS_PPS) ? " PPS" : "",
 474                         (temp & RH_PS_PRS) ? " PRS" : "",
 475                         (temp & RH_PS_POCI) ? " POCI" : "",
 476                         (temp & RH_PS_PSS) ? " PSS" : "",
 477
 478                         (temp & RH_PS_PES) ? " PES" : "",
 479                         (temp & RH_PS_CCS) ? " CCS" : ""
 480                         );
 481         }
 482 }
 483
 484 static void ohci_dump(ohci_t *controller, int verbose)
 485 {
 486         dbg("OHCI controller usb-%s state", controller->slot_name);
 487
 488         /* dumps some of the state we know about */
 489         ohci_dump_status(controller);
 490         if (verbose)
 491                 ep_print_int_eds(controller, "hcca");
 492         invalidate_dcache_hcca(controller->hcca);
 493         dbg("hcca frame #%04x", controller->hcca->frame_no);
 494         ohci_dump_roothub(controller, 1);
 495 }
 496 #endif /* DEBUG */
 497
 498 /*-------------------------------------------------------------------------*
 499  * Interface functions (URB)
 500  *-------------------------------------------------------------------------*/
 501
 502 /* get a transfer request */
 503
 504 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
 505                      struct devrequest *setup)
 506 {
 507         ed_t *ed;
 508         urb_priv_t *purb_priv = urb;
 509         int i, size = 0;
 510         struct usb_device *dev = urb->dev;
 511         unsigned long pipe = urb->pipe;
 512         void *buffer = urb->transfer_buffer;
 513         int transfer_len = urb->transfer_buffer_length;
 514         int interval = urb->interval;
 515
 516         /* when controller's hung, permit only roothub cleanup attempts
 517          * such as powering down ports */
 518         if (ohci->disabled) {
 519                 err("sohci_submit_job: EPIPE");
 520                 return -1;
 521         }
 522
 523         /* we're about to begin a new transaction here so mark the
 524          * URB unfinished */
 525         urb->finished = 0;
 526
 527         /* every endpoint has a ed, locate and fill it */
 528         ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
 529         if (!ed) {
 530                 err("sohci_submit_job: ENOMEM");
 531                 return -1;
 532         }
 533
 534         /* for the private part of the URB we need the number of TDs (size) */
 535         switch (usb_pipetype(pipe)) {
 536         case PIPE_BULK: /* one TD for every 4096 Byte */
 537                 size = (transfer_len - 1) / 4096 + 1;
 538                 break;
 539         case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
 540                 size = (transfer_len == 0)? 2:
 541                                         (transfer_len - 1) / 4096 + 3;
 542                 break;
 543         case PIPE_INTERRUPT: /* 1 TD */
 544                 size = 1;
 545                 break;
 546         }
 547
 548         ed->purb = urb;
 549
 550         if (size >= (N_URB_TD - 1)) {
 551                 err("need %d TDs, only have %d", size, N_URB_TD);
 552                 return -1;
 553         }
 554         purb_priv->pipe = pipe;
 555
 556         /* fill the private part of the URB */
 557         purb_priv->length = size;
 558         purb_priv->ed = ed;
 559         purb_priv->actual_length = 0;
 560
 561         /* allocate the TDs */
 562         /* note that td[0] was allocated in ep_add_ed */
 563         for (i = 0; i < size; i++) {
 564                 purb_priv->td[i] = td_alloc(ohci_dev, dev);
 565                 if (!purb_priv->td[i]) {
 566                         purb_priv->length = i;
 567                         urb_free_priv(purb_priv);
 568                         err("sohci_submit_job: ENOMEM");
 569                         return -1;
 570                 }
 571         }
 572
 573         if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
 574                 urb_free_priv(purb_priv);
 575                 err("sohci_submit_job: EINVAL");
 576                 return -1;
 577         }
 578
 579         /* link the ed into a chain if is not already */
 580         if (ed->state != ED_OPER)
 581                 ep_link(ohci, ed);
 582
 583         /* fill the TDs and link it to the ed */
 584         td_submit_job(ohci, dev, pipe, buffer, transfer_len,
 585                       setup, purb_priv, interval);
 586
 587         return 0;
 588 }
 589
 590 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
 591 {
 592         struct ohci_regs *regs = hc->regs;
 593
 594         switch (usb_pipetype(urb->pipe)) {
 595         case PIPE_INTERRUPT:
 596                 /* implicitly requeued */
 597                 if (urb->dev->irq_handle &&
 598                                 (urb->dev->irq_act_len = urb->actual_length)) {
 599                         ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
 600                         ohci_readl(&regs->intrenable); /* PCI posting flush */
 601                         urb->dev->irq_handle(urb->dev);
 602                         ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
 603                         ohci_readl(&regs->intrdisable); /* PCI posting flush */
 604                 }
 605                 urb->actual_length = 0;
 606                 td_submit_job(  hc,
 607                                 urb->dev,
 608                                 urb->pipe,
 609                                 urb->transfer_buffer,
 610                                 urb->transfer_buffer_length,
 611                                 NULL,
 612                                 urb,
 613                                 urb->interval);
 614                 break;
 615         case PIPE_CONTROL:
 616         case PIPE_BULK:
 617                 break;
 618         default:
 619                 return 0;
 620         }
 621         return 1;
 622 }
 623
 624 /*-------------------------------------------------------------------------*/
 625
 626 #ifdef DEBUG
 627 /* tell us the current USB frame number */
 628 static int sohci_get_current_frame_number(ohci_t *ohci)
 629 {
 630         invalidate_dcache_hcca(ohci->hcca);
 631         return m16_swap(ohci->hcca->frame_no);
 632 }
 633 #endif
 634
 635 /*-------------------------------------------------------------------------*
 636  * ED handling functions
 637  *-------------------------------------------------------------------------*/
 638
 639 /* search for the right branch to insert an interrupt ed into the int tree
 640  * do some load ballancing;
 641  * returns the branch and
 642  * sets the interval to interval = 2^integer (ld (interval)) */
 643
 644 static int ep_int_ballance(ohci_t *ohci, int interval, int load)
 645 {
 646         int i, branch = 0;
 647
 648         /* search for the least loaded interrupt endpoint
 649          * branch of all 32 branches
 650          */
 651         for (i = 0; i < 32; i++)
 652                 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
 653                         branch = i;
 654
 655         branch = branch % interval;
 656         for (i = branch; i < 32; i += interval)
 657                 ohci->ohci_int_load [i] += load;
 658
 659         return branch;
 660 }
 661
 662 /*-------------------------------------------------------------------------*/
 663
 664 /*  2^int( ld (inter)) */
 665
 666 static int ep_2_n_interval(int inter)
 667 {
 668         int i;
 669         for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
 670         return 1 << i;
 671 }
 672
 673 /*-------------------------------------------------------------------------*/
 674
 675 /* the int tree is a binary tree
 676  * in order to process it sequentially the indexes of the branches have to
 677  * be mapped the mapping reverses the bits of a word of num_bits length */
 678 static int ep_rev(int num_bits, int word)
 679 {
 680         int i, wout = 0;
 681
 682         for (i = 0; i < num_bits; i++)
 683                 wout |= (((word >> i) & 1) << (num_bits - i - 1));
 684         return wout;
 685 }
 686
 687 /*-------------------------------------------------------------------------*
 688  * ED handling functions
 689  *-------------------------------------------------------------------------*/
 690
 691 /* link an ed into one of the HC chains */
 692
 693 static int ep_link(ohci_t *ohci, ed_t *edi)
 694 {
 695         volatile ed_t *ed = edi;
 696         int int_branch;
 697         int i;
 698         int inter;
 699         int interval;
 700         int load;
 701         __u32 *ed_p;
 702
 703         ed->state = ED_OPER;
 704         ed->int_interval = 0;
 705
 706         switch (ed->type) {
 707         case PIPE_CONTROL:
 708                 ed->hwNextED = 0;
 709                 flush_dcache_ed(ed);
 710                 if (ohci->ed_controltail == NULL)
 711                         ohci_writel(ed, &ohci->regs->ed_controlhead);
 712                 else
 713                         ohci->ed_controltail->hwNextED =
 714                                                    m32_swap((unsigned long)ed);
 715
 716                 ed->ed_prev = ohci->ed_controltail;
 717                 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 718                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 719                         ohci->hc_control |= OHCI_CTRL_CLE;
 720                         ohci_writel(ohci->hc_control, &ohci->regs->control);
 721                 }
 722                 ohci->ed_controltail = edi;
 723                 break;
 724
 725         case PIPE_BULK:
 726                 ed->hwNextED = 0;
 727                 flush_dcache_ed(ed);
 728                 if (ohci->ed_bulktail == NULL)
 729                         ohci_writel(ed, &ohci->regs->ed_bulkhead);
 730                 else
 731                         ohci->ed_bulktail->hwNextED =
 732                                                    m32_swap((unsigned long)ed);
 733
 734                 ed->ed_prev = ohci->ed_bulktail;
 735                 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 736                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 737                         ohci->hc_control |= OHCI_CTRL_BLE;
 738                         ohci_writel(ohci->hc_control, &ohci->regs->control);
 739                 }
 740                 ohci->ed_bulktail = edi;
 741                 break;
 742
 743         case PIPE_INTERRUPT:
 744                 load = ed->int_load;
 745                 interval = ep_2_n_interval(ed->int_period);
 746                 ed->int_interval = interval;
 747                 int_branch = ep_int_ballance(ohci, interval, load);
 748                 ed->int_branch = int_branch;
 749
 750                 for (i = 0; i < ep_rev(6, interval); i += inter) {
 751                         inter = 1;
 752                         for (ed_p = &(ohci->hcca->int_table[\
 753                                                 ep_rev(5, i) + int_branch]);
 754                                 (*ed_p != 0) &&
 755                                 (((ed_t *)ed_p)->int_interval >= interval);
 756                                 ed_p = &(((ed_t *)ed_p)->hwNextED))
 757                                         inter = ep_rev(6,
 758                                                  ((ed_t *)ed_p)->int_interval);
 759                         ed->hwNextED = *ed_p;
 760                         flush_dcache_ed(ed);
 761                         *ed_p = m32_swap((unsigned long)ed);
 762                         flush_dcache_hcca(ohci->hcca);
 763                 }
 764                 break;
 765         }
 766         return 0;
 767 }
 768
 769 /*-------------------------------------------------------------------------*/
 770
 771 /* scan the periodic table to find and unlink this ED */
 772 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
 773                             unsigned index, unsigned period)
 774 {
 775         __maybe_unused unsigned long aligned_ed_p;
 776
 777         for (; index < NUM_INTS; index += period) {
 778                 __u32   *ed_p = &ohci->hcca->int_table [index];
 779
 780                 /* ED might have been unlinked through another path */
 781                 while (*ed_p != 0) {
 782                         if (((struct ed *)
 783                                         m32_swap((unsigned long)ed_p)) == ed) {
 784                                 *ed_p = ed->hwNextED;
 785 #ifdef CONFIG_DM_USB
 786                                 aligned_ed_p = (unsigned long)ed_p;
 787                                 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
 788                                 flush_dcache_range(aligned_ed_p,
 789                                         aligned_ed_p + ARCH_DMA_MINALIGN);
 790 #endif
 791                                 break;
 792                         }
 793                         ed_p = &(((struct ed *)
 794                                      m32_swap((unsigned long)ed_p))->hwNextED);
 795                 }
 796         }
 797 }
 798
 799 /* unlink an ed from one of the HC chains.
 800  * just the link to the ed is unlinked.
 801  * the link from the ed still points to another operational ed or 0
 802  * so the HC can eventually finish the processing of the unlinked ed */
 803
 804 static int ep_unlink(ohci_t *ohci, ed_t *edi)
 805 {
 806         volatile ed_t *ed = edi;
 807         int i;
 808
 809         ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
 810         flush_dcache_ed(ed);
 811
 812         switch (ed->type) {
 813         case PIPE_CONTROL:
 814                 if (ed->ed_prev == NULL) {
 815                         if (!ed->hwNextED) {
 816                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 817                                 ohci_writel(ohci->hc_control,
 818                                             &ohci->regs->control);
 819                         }
 820                         ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 821                                 &ohci->regs->ed_controlhead);
 822                 } else {
 823                         ed->ed_prev->hwNextED = ed->hwNextED;
 824                         flush_dcache_ed(ed->ed_prev);
 825                 }
 826                 if (ohci->ed_controltail == ed) {
 827                         ohci->ed_controltail = ed->ed_prev;
 828                 } else {
 829                         ((ed_t *)m32_swap(
 830                             *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 831                 }
 832                 break;
 833
 834         case PIPE_BULK:
 835                 if (ed->ed_prev == NULL) {
 836                         if (!ed->hwNextED) {
 837                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 838                                 ohci_writel(ohci->hc_control,
 839                                             &ohci->regs->control);
 840                         }
 841                         ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 842                                &ohci->regs->ed_bulkhead);
 843                 } else {
 844                         ed->ed_prev->hwNextED = ed->hwNextED;
 845                         flush_dcache_ed(ed->ed_prev);
 846                 }
 847                 if (ohci->ed_bulktail == ed) {
 848                         ohci->ed_bulktail = ed->ed_prev;
 849                 } else {
 850                         ((ed_t *)m32_swap(
 851                              *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 852                 }
 853                 break;
 854
 855         case PIPE_INTERRUPT:
 856                 periodic_unlink(ohci, ed, 0, 1);
 857                 for (i = ed->int_branch; i < 32; i += ed->int_interval)
 858                     ohci->ohci_int_load[i] -= ed->int_load;
 859                 break;
 860         }
 861         ed->state = ED_UNLINK;
 862         return 0;
 863 }
 864
 865 /*-------------------------------------------------------------------------*/
 866
 867 /* add/reinit an endpoint; this should be done once at the
 868  * usb_set_configuration command, but the USB stack is a little bit
 869  * stateless so we do it at every transaction if the state of the ed
 870  * is ED_NEW then a dummy td is added and the state is changed to
 871  * ED_UNLINK in all other cases the state is left unchanged the ed
 872  * info fields are setted anyway even though most of them should not
 873  * change
 874  */
 875 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
 876                        unsigned long pipe, int interval, int load)
 877 {
 878         td_t *td;
 879         ed_t *ed_ret;
 880         volatile ed_t *ed;
 881
 882         ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
 883                         (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
 884
 885         if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
 886                 err("ep_add_ed: pending delete");
 887                 /* pending delete request */
 888                 return NULL;
 889         }
 890
 891         if (ed->state == ED_NEW) {
 892                 /* dummy td; end of td list for ed */
 893                 td = td_alloc(ohci_dev, usb_dev);
 894                 ed->hwTailP = m32_swap((unsigned long)td);
 895                 ed->hwHeadP = ed->hwTailP;
 896                 ed->state = ED_UNLINK;
 897                 ed->type = usb_pipetype(pipe);
 898                 ohci_dev->ed_cnt++;
 899         }
 900
 901         ed->hwINFO = m32_swap(usb_pipedevice(pipe)
 902                         | usb_pipeendpoint(pipe) << 7
 903                         | (usb_pipeisoc(pipe)? 0x8000: 0)
 904                         | (usb_pipecontrol(pipe)? 0: \
 905                                            (usb_pipeout(pipe)? 0x800: 0x1000))
 906                         | (usb_dev->speed == USB_SPEED_LOW) << 13
 907                         | usb_maxpacket(usb_dev, pipe) << 16);
 908
 909         if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
 910                 ed->int_period = interval;
 911                 ed->int_load = load;
 912         }
 913
 914         flush_dcache_ed(ed);
 915
 916         return ed_ret;
 917 }
 918
 919 /*-------------------------------------------------------------------------*
 920  * TD handling functions
 921  *-------------------------------------------------------------------------*/
 922
 923 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 924
 925 static void td_fill(ohci_t *ohci, unsigned int info,
 926         void *data, int len,
 927         struct usb_device *dev, int index, urb_priv_t *urb_priv)
 928 {
 929         volatile td_t  *td, *td_pt;
 930 #ifdef OHCI_FILL_TRACE
 931         int i;
 932 #endif
 933
 934         if (index > urb_priv->length) {
 935                 err("index > length");
 936                 return;
 937         }
 938         /* use this td as the next dummy */
 939         td_pt = urb_priv->td [index];
 940         td_pt->hwNextTD = 0;
 941         flush_dcache_td(td_pt);
 942
 943         /* fill the old dummy TD */
 944         td = urb_priv->td [index] =
 945                              (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
 946
 947         td->ed = urb_priv->ed;
 948         td->next_dl_td = NULL;
 949         td->index = index;
 950         td->data = (__u32)data;
 951 #ifdef OHCI_FILL_TRACE
 952         if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
 953                 for (i = 0; i < len; i++)
 954                 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
 955                 printf("\n");
 956         }
 957 #endif
 958         if (!len)
 959                 data = 0;
 960
 961         td->hwINFO = m32_swap(info);
 962         td->hwCBP = m32_swap((unsigned long)data);
 963         if (data)
 964                 td->hwBE = m32_swap((unsigned long)(data + len - 1));
 965         else
 966                 td->hwBE = 0;
 967
 968         td->hwNextTD = m32_swap((unsigned long)td_pt);
 969         flush_dcache_td(td);
 970
 971         /* append to queue */
 972         td->ed->hwTailP = td->hwNextTD;
 973         flush_dcache_ed(td->ed);
 974 }
 975
 976 /*-------------------------------------------------------------------------*/
 977
 978 /* prepare all TDs of a transfer */
 979
 980 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
 981                           unsigned long pipe, void *buffer, int transfer_len,
 982                           struct devrequest *setup, urb_priv_t *urb,
 983                           int interval)
 984 {
 985         int data_len = transfer_len;
 986         void *data;
 987         int cnt = 0;
 988         __u32 info = 0;
 989         unsigned int toggle = 0;
 990
 991         flush_dcache_buffer(buffer, data_len);
 992
 993         /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
 994          * bits for reseting */
 995         if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
 996                 toggle = TD_T_TOGGLE;
 997         } else {
 998                 toggle = TD_T_DATA0;
 999                 usb_settoggle(dev, usb_pipeendpoint(pipe),
1000                                 usb_pipeout(pipe), 1);
1001         }
1002         urb->td_cnt = 0;
1003         if (data_len)
1004                 data = buffer;
1005         else
1006                 data = 0;
1007
1008         switch (usb_pipetype(pipe)) {
1009         case PIPE_BULK:
1010                 info = usb_pipeout(pipe)?
1011                         TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
1012                 while (data_len > 4096) {
1013                         td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
1014                                 data, 4096, dev, cnt, urb);
1015                         data += 4096; data_len -= 4096; cnt++;
1016                 }
1017                 info = usb_pipeout(pipe)?
1018                         TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
1019                 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
1020                         data_len, dev, cnt, urb);
1021                 cnt++;
1022
1023                 if (!ohci->sleeping) {
1024                         /* start bulk list */
1025                         ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
1026                 }
1027                 break;
1028
1029         case PIPE_CONTROL:
1030                 /* Setup phase */
1031                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
1032                 flush_dcache_buffer(setup, 8);
1033                 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
1034
1035                 /* Optional Data phase */
1036                 if (data_len > 0) {
1037                         info = usb_pipeout(pipe)?
1038                                 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
1039                                 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1040                         /* NOTE:  mishandles transfers >8K, some >4K */
1041                         td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1042                 }
1043
1044                 /* Status phase */
1045                 info = (usb_pipeout(pipe) || data_len == 0) ?
1046                         TD_CC | TD_DP_IN | TD_T_DATA1:
1047                         TD_CC | TD_DP_OUT | TD_T_DATA1;
1048                 td_fill(ohci, info, data, 0, dev, cnt++, urb);
1049
1050                 if (!ohci->sleeping) {
1051                         /* start Control list */
1052                         ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
1053                 }
1054                 break;
1055
1056         case PIPE_INTERRUPT:
1057                 info = usb_pipeout(urb->pipe)?
1058                         TD_CC | TD_DP_OUT | toggle:
1059                         TD_CC | TD_R | TD_DP_IN | toggle;
1060                 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1061                 break;
1062         }
1063         if (urb->length != cnt)
1064                 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
1065 }
1066
1067 /*-------------------------------------------------------------------------*
1068  * Done List handling functions
1069  *-------------------------------------------------------------------------*/
1070
1071 /* calculate the transfer length and update the urb */
1072
1073 static void dl_transfer_length(td_t *td)
1074 {
1075         __u32 tdBE, tdCBP;
1076         urb_priv_t *lurb_priv = td->ed->purb;
1077
1078         tdBE   = m32_swap(td->hwBE);
1079         tdCBP  = m32_swap(td->hwCBP);
1080
1081         if (!(usb_pipecontrol(lurb_priv->pipe) &&
1082             ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
1083                 if (tdBE != 0) {
1084                         if (td->hwCBP == 0)
1085                                 lurb_priv->actual_length += tdBE - td->data + 1;
1086                         else
1087                                 lurb_priv->actual_length += tdCBP - td->data;
1088                 }
1089         }
1090 }
1091
1092 /*-------------------------------------------------------------------------*/
1093 static void check_status(td_t *td_list)
1094 {
1095         urb_priv_t *lurb_priv = td_list->ed->purb;
1096         int        urb_len    = lurb_priv->length;
1097         __u32      *phwHeadP  = &td_list->ed->hwHeadP;
1098         int        cc;
1099
1100         cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1101         if (cc) {
1102                 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1103
1104                 invalidate_dcache_ed(td_list->ed);
1105                 if (*phwHeadP & m32_swap(0x1)) {
1106                         if (lurb_priv &&
1107                             ((td_list->index + 1) < urb_len)) {
1108                                 *phwHeadP =
1109                                         (lurb_priv->td[urb_len - 1]->hwNextTD &\
1110                                                         m32_swap(0xfffffff0)) |
1111                                                    (*phwHeadP & m32_swap(0x2));
1112
1113                                 lurb_priv->td_cnt += urb_len -
1114                                                      td_list->index - 1;
1115                         } else
1116                                 *phwHeadP &= m32_swap(0xfffffff2);
1117                         flush_dcache_ed(td_list->ed);
1118                 }
1119 #ifdef CONFIG_MPC5200
1120                 td_list->hwNextTD = 0;
1121                 flush_dcache_td(td_list);
1122 #endif
1123         }
1124 }
1125
1126 /* replies to the request have to be on a FIFO basis so
1127  * we reverse the reversed done-list */
1128 static td_t *dl_reverse_done_list(ohci_t *ohci)
1129 {
1130         __u32 td_list_hc;
1131         td_t *td_rev = NULL;
1132         td_t *td_list = NULL;
1133
1134         invalidate_dcache_hcca(ohci->hcca);
1135         td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
1136         ohci->hcca->done_head = 0;
1137         flush_dcache_hcca(ohci->hcca);
1138
1139         while (td_list_hc) {
1140                 td_list = (td_t *)td_list_hc;
1141                 invalidate_dcache_td(td_list);
1142                 check_status(td_list);
1143                 td_list->next_dl_td = td_rev;
1144                 td_rev = td_list;
1145                 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
1146         }
1147         return td_list;
1148 }
1149
1150 /*-------------------------------------------------------------------------*/
1151 /*-------------------------------------------------------------------------*/
1152
1153 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1154 {
1155         if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1156                 urb->finished = sohci_return_job(ohci, urb);
1157         else
1158                 dbg("finish_urb: strange.., ED state %x, \n", status);
1159 }
1160
1161 /*
1162  * Used to take back a TD from the host controller. This would normally be
1163  * called from within dl_done_list, however it may be called directly if the
1164  * HC no longer sees the TD and it has not appeared on the donelist (after
1165  * two frames).  This bug has been observed on ZF Micro systems.
1166  */
1167 static int takeback_td(ohci_t *ohci, td_t *td_list)
1168 {
1169         ed_t *ed;
1170         int cc;
1171         int stat = 0;
1172         /* urb_t *urb; */
1173         urb_priv_t *lurb_priv;
1174         __u32 tdINFO, edHeadP, edTailP;
1175
1176         invalidate_dcache_td(td_list);
1177         tdINFO = m32_swap(td_list->hwINFO);
1178
1179         ed = td_list->ed;
1180         lurb_priv = ed->purb;
1181
1182         dl_transfer_length(td_list);
1183
1184         lurb_priv->td_cnt++;
1185
1186         /* error code of transfer */
1187         cc = TD_CC_GET(tdINFO);
1188         if (cc) {
1189                 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1190                 stat = cc_to_error[cc];
1191         }
1192
1193         /* see if this done list makes for all TD's of current URB,
1194         * and mark the URB finished if so */
1195         if (lurb_priv->td_cnt == lurb_priv->length)
1196                 finish_urb(ohci, lurb_priv, ed->state);
1197
1198         dbg("dl_done_list: processing TD %x, len %x\n",
1199                 lurb_priv->td_cnt, lurb_priv->length);
1200
1201         if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
1202                 invalidate_dcache_ed(ed);
1203                 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1204                 edTailP = m32_swap(ed->hwTailP);
1205
1206                 /* unlink eds if they are not busy */
1207                 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1208                         ep_unlink(ohci, ed);
1209         }
1210         return stat;
1211 }
1212
1213 static int dl_done_list(ohci_t *ohci)
1214 {
1215         int stat = 0;
1216         td_t    *td_list = dl_reverse_done_list(ohci);
1217
1218         while (td_list) {
1219                 td_t    *td_next = td_list->next_dl_td;
1220                 stat = takeback_td(ohci, td_list);
1221                 td_list = td_next;
1222         }
1223         return stat;
1224 }
1225
1226 /*-------------------------------------------------------------------------*
1227  * Virtual Root Hub
1228  *-------------------------------------------------------------------------*/
1229
1230 #include <usbroothubdes.h>
1231
1232 /* Hub class-specific descriptor is constructed dynamically */
1233
1234 /*-------------------------------------------------------------------------*/
1235
1236 #define OK(x)                   len = (x); break
1237 #ifdef DEBUG
1238 #define WR_RH_STAT(x)           {info("WR:status %#8x", (x)); ohci_writel((x), \
1239                                                 &ohci->regs->roothub.status); }
1240 #define WR_RH_PORTSTAT(x)       {info("WR:portstatus[%d] %#8x", wIndex-1, \
1241         (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
1242 #else
1243 #define WR_RH_STAT(x)           ohci_writel((x), &ohci->regs->roothub.status)
1244 #define WR_RH_PORTSTAT(x)       ohci_writel((x), \
1245                                     &ohci->regs->roothub.portstatus[wIndex-1])
1246 #endif
1247 #define RD_RH_STAT              roothub_status(ohci)
1248 #define RD_RH_PORTSTAT          roothub_portstatus(ohci, wIndex-1)
1249
1250 /* request to virtual root hub */
1251
1252 int rh_check_port_status(ohci_t *controller)
1253 {
1254         __u32 temp, ndp, i;
1255         int res;
1256
1257         res = -1;
1258         temp = roothub_a(controller);
1259         ndp = (temp & RH_A_NDP);
1260 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1261         ndp = (ndp == 2) ? 1:0;
1262 #endif
1263         for (i = 0; i < ndp; i++) {
1264                 temp = roothub_portstatus(controller, i);
1265                 /* check for a device disconnect */
1266                 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1267                         (RH_PS_PESC | RH_PS_CSC)) &&
1268                         ((temp & RH_PS_CCS) == 0)) {
1269                         res = i;
1270                         break;
1271                 }
1272         }
1273         return res;
1274 }
1275
1276 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
1277         unsigned long pipe, void *buffer, int transfer_len,
1278         struct devrequest *cmd)
1279 {
1280         void *data = buffer;
1281         int leni = transfer_len;
1282         int len = 0;
1283         int stat = 0;
1284         __u16 bmRType_bReq;
1285         __u16 wValue;
1286         __u16 wIndex;
1287         __u16 wLength;
1288         ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
1289
1290 #ifdef DEBUG
1291 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1292           cmd, "SUB(rh)", usb_pipein(pipe));
1293 #else
1294         mdelay(1);
1295 #endif
1296         if (usb_pipeint(pipe)) {
1297                 info("Root-Hub submit IRQ: NOT implemented");
1298                 return 0;
1299         }
1300
1301         bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
1302         wValue        = le16_to_cpu(cmd->value);
1303         wIndex        = le16_to_cpu(cmd->index);
1304         wLength       = le16_to_cpu(cmd->length);
1305
1306         info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1307                 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1308
1309         switch (bmRType_bReq) {
1310         /* Request Destination:
1311            without flags: Device,
1312            RH_INTERFACE: interface,
1313            RH_ENDPOINT: endpoint,
1314            RH_CLASS means HUB here,
1315            RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
1316         */
1317
1318         case RH_GET_STATUS:
1319                 *(u16 *)databuf = cpu_to_le16(1);
1320                 OK(2);
1321         case RH_GET_STATUS | RH_INTERFACE:
1322                 *(u16 *)databuf = cpu_to_le16(0);
1323                 OK(2);
1324         case RH_GET_STATUS | RH_ENDPOINT:
1325                 *(u16 *)databuf = cpu_to_le16(0);
1326                 OK(2);
1327         case RH_GET_STATUS | RH_CLASS:
1328                 *(u32 *)databuf = cpu_to_le32(
1329                                 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1330                 OK(4);
1331         case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1332                 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
1333                 OK(4);
1334
1335         case RH_CLEAR_FEATURE | RH_ENDPOINT:
1336                 switch (wValue) {
1337                 case (RH_ENDPOINT_STALL):
1338                         OK(0);
1339                 }
1340                 break;
1341
1342         case RH_CLEAR_FEATURE | RH_CLASS:
1343                 switch (wValue) {
1344                 case RH_C_HUB_LOCAL_POWER:
1345                         OK(0);
1346                 case (RH_C_HUB_OVER_CURRENT):
1347                         WR_RH_STAT(RH_HS_OCIC);
1348                         OK(0);
1349                 }
1350                 break;
1351
1352         case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1353                 switch (wValue) {
1354                 case (RH_PORT_ENABLE):        WR_RH_PORTSTAT(RH_PS_CCS);  OK(0);
1355                 case (RH_PORT_SUSPEND):       WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1356                 case (RH_PORT_POWER):         WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1357                 case (RH_C_PORT_CONNECTION):  WR_RH_PORTSTAT(RH_PS_CSC);  OK(0);
1358                 case (RH_C_PORT_ENABLE):      WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1359                 case (RH_C_PORT_SUSPEND):     WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1360                 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1361                 case (RH_C_PORT_RESET):       WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
1362                 }
1363                 break;
1364
1365         case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1366                 switch (wValue) {
1367                 case (RH_PORT_SUSPEND):
1368                         WR_RH_PORTSTAT(RH_PS_PSS);  OK(0);
1369                 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1370                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1371                                 WR_RH_PORTSTAT(RH_PS_PRS);
1372                         OK(0);
1373                 case (RH_PORT_POWER):
1374                         WR_RH_PORTSTAT(RH_PS_PPS);
1375                         mdelay(100);
1376                         OK(0);
1377                 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1378                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1379                                 WR_RH_PORTSTAT(RH_PS_PES);
1380                         OK(0);
1381                 }
1382                 break;
1383
1384         case RH_SET_ADDRESS:
1385                 ohci->rh.devnum = wValue;
1386                 OK(0);
1387
1388         case RH_GET_DESCRIPTOR:
1389                 switch ((wValue & 0xff00) >> 8) {
1390                 case (0x01): /* device descriptor */
1391                         len = min_t(unsigned int,
1392                                         leni,
1393                                         min_t(unsigned int,
1394                                         sizeof(root_hub_dev_des),
1395                                         wLength));
1396                         databuf = root_hub_dev_des; OK(len);
1397                 case (0x02): /* configuration descriptor */
1398                         len = min_t(unsigned int,
1399                                         leni,
1400                                         min_t(unsigned int,
1401                                         sizeof(root_hub_config_des),
1402                                         wLength));
1403                         databuf = root_hub_config_des; OK(len);
1404                 case (0x03): /* string descriptors */
1405                         if (wValue == 0x0300) {
1406                                 len = min_t(unsigned int,
1407                                                 leni,
1408                                                 min_t(unsigned int,
1409                                                 sizeof(root_hub_str_index0),
1410                                                 wLength));
1411                                 databuf = root_hub_str_index0;
1412                                 OK(len);
1413                         }
1414                         if (wValue == 0x0301) {
1415                                 len = min_t(unsigned int,
1416                                                 leni,
1417                                                 min_t(unsigned int,
1418                                                 sizeof(root_hub_str_index1),
1419                                                 wLength));
1420                                 databuf = root_hub_str_index1;
1421                                 OK(len);
1422                 }
1423                 default:
1424                         stat = USB_ST_STALLED;
1425                 }
1426                 break;
1427
1428         case RH_GET_DESCRIPTOR | RH_CLASS:
1429         {
1430                 __u32 temp = roothub_a(ohci);
1431
1432                 databuf[0] = 9;         /* min length; */
1433                 databuf[1] = 0x29;
1434                 databuf[2] = temp & RH_A_NDP;
1435 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1436                 databuf[2] = (databuf[2] == 2) ? 1 : 0;
1437 #endif
1438                 databuf[3] = 0;
1439                 if (temp & RH_A_PSM)    /* per-port power switching? */
1440                         databuf[3] |= 0x1;
1441                 if (temp & RH_A_NOCP)   /* no overcurrent reporting? */
1442                         databuf[3] |= 0x10;
1443                 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
1444                         databuf[3] |= 0x8;
1445
1446                 databuf[4] = 0;
1447                 databuf[5] = (temp & RH_A_POTPGT) >> 24;
1448                 databuf[6] = 0;
1449                 temp = roothub_b(ohci);
1450                 databuf[7] = temp & RH_B_DR;
1451                 if (databuf[2] < 7) {
1452                         databuf[8] = 0xff;
1453                 } else {
1454                         databuf[0] += 2;
1455                         databuf[8] = (temp & RH_B_DR) >> 8;
1456                         databuf[10] = databuf[9] = 0xff;
1457                 }
1458
1459                 len = min_t(unsigned int, leni,
1460                             min_t(unsigned int, databuf[0], wLength));
1461                 OK(len);
1462         }
1463
1464         case RH_GET_CONFIGURATION:
1465                 databuf[0] = 0x01;
1466                 OK(1);
1467
1468         case RH_SET_CONFIGURATION:
1469                 WR_RH_STAT(0x10000);
1470                 OK(0);
1471
1472         default:
1473                 dbg("unsupported root hub command");
1474                 stat = USB_ST_STALLED;
1475         }
1476
1477 #ifdef  DEBUG
1478         ohci_dump_roothub(ohci, 1);
1479 #else
1480         mdelay(1);
1481 #endif
1482
1483         len = min_t(int, len, leni);
1484         if (data != databuf)
1485                 memcpy(data, databuf, len);
1486         dev->act_len = len;
1487         dev->status = stat;
1488
1489 #ifdef DEBUG
1490         pkt_print(ohci, NULL, dev, pipe, buffer,
1491                   transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1492 #else
1493         mdelay(1);
1494 #endif
1495
1496         return stat;
1497 }
1498
1499 /*-------------------------------------------------------------------------*/
1500
1501 /* common code for handling submit messages - used for all but root hub */
1502 /* accesses. */
1503 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
1504                 unsigned long pipe, void *buffer, int transfer_len,
1505                 struct devrequest *setup, int interval)
1506 {
1507         int stat = 0;
1508         int maxsize = usb_maxpacket(dev, pipe);
1509         int timeout;
1510         urb_priv_t *urb;
1511
1512         urb = malloc(sizeof(urb_priv_t));
1513         memset(urb, 0, sizeof(urb_priv_t));
1514
1515         urb->dev = dev;
1516         urb->pipe = pipe;
1517         urb->transfer_buffer = buffer;
1518         urb->transfer_buffer_length = transfer_len;
1519         urb->interval = interval;
1520
1521 #ifdef DEBUG
1522         urb->actual_length = 0;
1523         pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1524                   setup, "SUB", usb_pipein(pipe));
1525 #else
1526         mdelay(1);
1527 #endif
1528         if (!maxsize) {
1529                 err("submit_common_message: pipesize for pipe %lx is zero",
1530                         pipe);
1531                 return -1;
1532         }
1533
1534         if (sohci_submit_job(ohci, &ohci->ohci_dev, urb, setup) < 0) {
1535                 err("sohci_submit_job failed");
1536                 return -1;
1537         }
1538
1539 #if 0
1540         mdelay(10);
1541         /* ohci_dump_status(ohci); */
1542 #endif
1543
1544         timeout = USB_TIMEOUT_MS(pipe);
1545
1546         /* wait for it to complete */
1547         for (;;) {
1548                 /* check whether the controller is done */
1549                 stat = hc_interrupt(ohci);
1550                 if (stat < 0) {
1551                         stat = USB_ST_CRC_ERR;
1552                         break;
1553                 }
1554
1555                 /* NOTE: since we are not interrupt driven in U-Boot and always
1556                  * handle only one URB at a time, we cannot assume the
1557                  * transaction finished on the first successful return from
1558                  * hc_interrupt().. unless the flag for current URB is set,
1559                  * meaning that all TD's to/from device got actually
1560                  * transferred and processed. If the current URB is not
1561                  * finished we need to re-iterate this loop so as
1562                  * hc_interrupt() gets called again as there needs to be some
1563                  * more TD's to process still */
1564                 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1565                         /* 0xff is returned for an SF-interrupt */
1566                         break;
1567                 }
1568
1569                 if (--timeout) {
1570                         mdelay(1);
1571                         if (!urb->finished)
1572                                 dbg("*");
1573
1574                 } else {
1575                         if (!usb_pipeint(pipe))
1576                                 err("CTL:TIMEOUT ");
1577                         dbg("submit_common_msg: TO status %x\n", stat);
1578                         urb->finished = 1;
1579                         stat = USB_ST_CRC_ERR;
1580                         break;
1581                 }
1582         }
1583
1584         dev->status = stat;
1585         dev->act_len = urb->actual_length;
1586
1587         if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
1588                 invalidate_dcache_buffer(buffer, dev->act_len);
1589
1590 #ifdef DEBUG
1591         pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1592                   setup, "RET(ctlr)", usb_pipein(pipe));
1593 #else
1594         mdelay(1);
1595 #endif
1596
1597         /* free TDs in urb_priv */
1598         if (!usb_pipeint(pipe))
1599                 urb_free_priv(urb);
1600         return 0;
1601 }
1602
1603 /* submit routines called from usb.c */
1604 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1605                 int transfer_len)
1606 {
1607         info("submit_bulk_msg");
1608         return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
1609                                  NULL, 0);
1610 }
1611
1612 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1613                 int transfer_len, int interval)
1614 {
1615         info("submit_int_msg");
1616         return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
1617                         interval);
1618 }
1619
1620 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
1621         unsigned long pipe, void *buffer, int transfer_len,
1622         struct devrequest *setup)
1623 {
1624         int maxsize = usb_maxpacket(dev, pipe);
1625
1626         info("submit_control_msg");
1627 #ifdef DEBUG
1628         pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1629                   setup, "SUB", usb_pipein(pipe));
1630 #else
1631         mdelay(1);
1632 #endif
1633         if (!maxsize) {
1634                 err("submit_control_message: pipesize for pipe %lx is zero",
1635                         pipe);
1636                 return -1;
1637         }
1638         if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
1639                 ohci->rh.dev = dev;
1640                 /* root hub - redirect */
1641                 return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
1642                                           transfer_len, setup);
1643         }
1644
1645         return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
1646                                  setup, 0);
1647 }
1648
1649 /*-------------------------------------------------------------------------*
1650  * HC functions
1651  *-------------------------------------------------------------------------*/
1652
1653 /* reset the HC and BUS */
1654
1655 static int hc_reset(ohci_t *ohci)
1656 {
1657 #ifdef CONFIG_PCI_EHCI_DEVNO
1658         pci_dev_t pdev;
1659 #endif
1660         int timeout = 30;
1661         int smm_timeout = 50; /* 0,5 sec */
1662
1663         dbg("%s\n", __FUNCTION__);
1664
1665 #ifdef CONFIG_PCI_EHCI_DEVNO
1666         /*
1667          *  Some multi-function controllers (e.g. ISP1562) allow root hub
1668          * resetting via EHCI registers only.
1669          */
1670         pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1671         if (pdev != -1) {
1672                 u32 base;
1673                 int timeout = 1000;
1674
1675                 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1676                 base += EHCI_USBCMD_OFF;
1677                 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
1678
1679                 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
1680                         if (timeout-- <= 0) {
1681                                 printf("USB RootHub reset timed out!");
1682                                 break;
1683                         }
1684                         udelay(1);
1685                 }
1686         } else
1687                 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1688 #endif
1689         if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1690                 /* SMM owns the HC, request ownership */
1691                 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
1692                 info("USB HC TakeOver from SMM");
1693                 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1694                         mdelay(10);
1695                         if (--smm_timeout == 0) {
1696                                 err("USB HC TakeOver failed!");
1697                                 return -1;
1698                         }
1699                 }
1700         }
1701
1702         /* Disable HC interrupts */
1703         ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1704
1705         dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1706                 ohci->slot_name,
1707                 ohci_readl(&ohci->regs->control));
1708
1709         /* Reset USB (needed by some controllers) */
1710         ohci->hc_control = 0;
1711         ohci_writel(ohci->hc_control, &ohci->regs->control);
1712
1713         /* HC Reset requires max 10 us delay */
1714         ohci_writel(OHCI_HCR,  &ohci->regs->cmdstatus);
1715         while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1716                 if (--timeout == 0) {
1717                         err("USB HC reset timed out!");
1718                         return -1;
1719                 }
1720                 udelay(1);
1721         }
1722         return 0;
1723 }
1724
1725 /*-------------------------------------------------------------------------*/
1726
1727 /* Start an OHCI controller, set the BUS operational
1728  * enable interrupts
1729  * connect the virtual root hub */
1730
1731 static int hc_start(ohci_t *ohci)
1732 {
1733         __u32 mask;
1734         unsigned int fminterval;
1735
1736         ohci->disabled = 1;
1737
1738         /* Tell the controller where the control and bulk lists are
1739          * The lists are empty now. */
1740
1741         ohci_writel(0, &ohci->regs->ed_controlhead);
1742         ohci_writel(0, &ohci->regs->ed_bulkhead);
1743
1744         ohci_writel((__u32)ohci->hcca,
1745                     &ohci->regs->hcca); /* reset clears this */
1746
1747         fminterval = 0x2edf;
1748         ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1749         fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1750         ohci_writel(fminterval, &ohci->regs->fminterval);
1751         ohci_writel(0x628, &ohci->regs->lsthresh);
1752
1753         /* start controller operations */
1754         ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1755         ohci->disabled = 0;
1756         ohci_writel(ohci->hc_control, &ohci->regs->control);
1757
1758         /* disable all interrupts */
1759         mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1760                         OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1761                         OHCI_INTR_OC | OHCI_INTR_MIE);
1762         ohci_writel(mask, &ohci->regs->intrdisable);
1763         /* clear all interrupts */
1764         mask &= ~OHCI_INTR_MIE;
1765         ohci_writel(mask, &ohci->regs->intrstatus);
1766         /* Choose the interrupts we care about now  - but w/o MIE */
1767         mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1768         ohci_writel(mask, &ohci->regs->intrenable);
1769
1770 #ifdef  OHCI_USE_NPS
1771         /* required for AMD-756 and some Mac platforms */
1772         ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1773                 &ohci->regs->roothub.a);
1774         ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1775 #endif  /* OHCI_USE_NPS */
1776
1777         /* POTPGT delay is bits 24-31, in 2 ms units. */
1778         mdelay((roothub_a(ohci) >> 23) & 0x1fe);
1779
1780         /* connect the virtual root hub */
1781         ohci->rh.devnum = 0;
1782
1783         return 0;
1784 }
1785
1786 /*-------------------------------------------------------------------------*/
1787
1788 /* an interrupt happens */
1789
1790 static int hc_interrupt(ohci_t *ohci)
1791 {
1792         struct ohci_regs *regs = ohci->regs;
1793         int ints;
1794         int stat = -1;
1795
1796         invalidate_dcache_hcca(ohci->hcca);
1797
1798         if ((ohci->hcca->done_head != 0) &&
1799                                 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1800                 ints =  OHCI_INTR_WDH;
1801         } else {
1802                 ints = ohci_readl(&regs->intrstatus);
1803                 if (ints == ~(u32)0) {
1804                         ohci->disabled++;
1805                         err("%s device removed!", ohci->slot_name);
1806                         return -1;
1807                 } else {
1808                         ints &= ohci_readl(&regs->intrenable);
1809                         if (ints == 0) {
1810                                 dbg("hc_interrupt: returning..\n");
1811                                 return 0xff;
1812                         }
1813                 }
1814         }
1815
1816         /* dbg("Interrupt: %x frame: %x", ints,
1817                                         le16_to_cpu(ohci->hcca->frame_no)); */
1818
1819         if (ints & OHCI_INTR_RHSC)
1820                 stat = 0xff;
1821
1822         if (ints & OHCI_INTR_UE) {
1823                 ohci->disabled++;
1824                 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1825                         ohci->slot_name);
1826                 /* e.g. due to PCI Master/Target Abort */
1827
1828 #ifdef  DEBUG
1829                 ohci_dump(ohci, 1);
1830 #else
1831                 mdelay(1);
1832 #endif
1833                 /* FIXME: be optimistic, hope that bug won't repeat often. */
1834                 /* Make some non-interrupt context restart the controller. */
1835                 /* Count and limit the retries though; either hardware or */
1836                 /* software errors can go forever... */
1837                 hc_reset(ohci);
1838                 return -1;
1839         }
1840
1841         if (ints & OHCI_INTR_WDH) {
1842                 mdelay(1);
1843                 ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
1844                 (void)ohci_readl(&regs->intrdisable); /* flush */
1845                 stat = dl_done_list(ohci);
1846                 ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
1847                 (void)ohci_readl(&regs->intrdisable); /* flush */
1848         }
1849
1850         if (ints & OHCI_INTR_SO) {
1851                 dbg("USB Schedule overrun\n");
1852                 ohci_writel(OHCI_INTR_SO, &regs->intrenable);
1853                 stat = -1;
1854         }
1855
1856         /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
1857         if (ints & OHCI_INTR_SF) {
1858                 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1859                 mdelay(1);
1860                 ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
1861                 if (ohci->ed_rm_list[frame] != NULL)
1862                         ohci_writel(OHCI_INTR_SF, &regs->intrenable);
1863                 stat = 0xff;
1864         }
1865
1866         ohci_writel(ints, &regs->intrstatus);
1867         return stat;
1868 }
1869
1870 /*-------------------------------------------------------------------------*/
1871
1872 /*-------------------------------------------------------------------------*/
1873
1874 /* De-allocate all resources.. */
1875
1876 static void hc_release_ohci(ohci_t *ohci)
1877 {
1878         dbg("USB HC release ohci usb-%s", ohci->slot_name);
1879
1880         if (!ohci->disabled)
1881                 hc_reset(ohci);
1882 }
1883
1884 /*-------------------------------------------------------------------------*/
1885
1886 /*
1887  * low level initalisation routine, called from usb.c
1888  */
1889 static char ohci_inited = 0;
1890
1891 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1892 {
1893 #ifdef CONFIG_PCI_OHCI
1894         pci_dev_t pdev;
1895 #endif
1896
1897 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1898         /* cpu dependant init */
1899         if (usb_cpu_init())
1900                 return -1;
1901 #endif
1902
1903 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1904         /*  board dependant init */
1905         if (board_usb_init(index, USB_INIT_HOST))
1906                 return -1;
1907 #endif
1908         memset(&gohci, 0, sizeof(ohci_t));
1909
1910         /* align the storage */
1911         if ((__u32)&ghcca[0] & 0xff) {
1912                 err("HCCA not aligned!!");
1913                 return -1;
1914         }
1915         gohci.hcca = &ghcca[0];
1916         info("aligned ghcca %p", gohci.hcca);
1917         memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
1918
1919         gohci.disabled = 1;
1920         gohci.sleeping = 0;
1921         gohci.irq = -1;
1922 #ifdef CONFIG_PCI_OHCI
1923         pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
1924
1925         if (pdev != -1) {
1926                 u16 vid, did;
1927                 u32 base;
1928                 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1929                 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1930                 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1931                                 vid, did, (pdev >> 16) & 0xff,
1932                                 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1933                 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1934                 printf("OHCI regs address 0x%08x\n", base);
1935                 gohci.regs = (struct ohci_regs *)base;
1936         } else
1937                 return -1;
1938 #else
1939         gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
1940 #endif
1941
1942         gohci.flags = 0;
1943         gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
1944
1945         if (hc_reset (&gohci) < 0) {
1946                 hc_release_ohci (&gohci);
1947                 err ("can't reset usb-%s", gohci.slot_name);
1948 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1949                 /* board dependant cleanup */
1950                 board_usb_cleanup(index, USB_INIT_HOST);
1951 #endif
1952
1953 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1954                 /* cpu dependant cleanup */
1955                 usb_cpu_init_fail();
1956 #endif
1957                 return -1;
1958         }
1959
1960         if (hc_start(&gohci) < 0) {
1961                 err("can't start usb-%s", gohci.slot_name);
1962                 hc_release_ohci(&gohci);
1963                 /* Initialization failed */
1964 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1965                 /* board dependant cleanup */
1966                 usb_board_stop();
1967 #endif
1968
1969 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1970                 /* cpu dependant cleanup */
1971                 usb_cpu_stop();
1972 #endif
1973                 return -1;
1974         }
1975
1976 #ifdef  DEBUG
1977         ohci_dump(&gohci, 1);
1978 #else
1979         mdelay(1);
1980 #endif
1981         ohci_inited = 1;
1982         return 0;
1983 }
1984
1985 int usb_lowlevel_stop(int index)
1986 {
1987         /* this gets called really early - before the controller has */
1988         /* even been initialized! */
1989         if (!ohci_inited)
1990                 return 0;
1991         /* TODO release any interrupts, etc. */
1992         /* call hc_release_ohci() here ? */
1993         hc_reset(&gohci);
1994
1995 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1996         /* board dependant cleanup */
1997         if (usb_board_stop())
1998                 return -1;
1999 #endif
2000
2001 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2002         /* cpu dependant cleanup */
2003         if (usb_cpu_stop())
2004                 return -1;
2005 #endif
2006         /* This driver is no longer initialised. It needs a new low-level
2007          * init (board/cpu) before it can be used again. */
2008         ohci_inited = 0;
2009         return 0;
2010 }
2011
2012 int submit_control_msg(struct usb_device *dev, unsigned long pipe,
2013         void *buffer, int transfer_len, struct devrequest *setup)
2014 {
2015         return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
2016                                         transfer_len, setup);
2017 }