drivers/video/da8xx-fb.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2011
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   6  *
   7  * Copyright (C) 2008-2009 MontaVista Software Inc.
   8  * Copyright (C) 2008-2009 Texas Instruments Inc
   9  *
  10  * Based on the LCD driver for TI Avalanche processors written by
  11  * Ajay Singh and Shalom Hai.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option)any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <malloc.h>
  30 #include <video_fb.h>
  31 #include <linux/list.h>
  32 #include <linux/fb.h>
  33 #include <lcd.h>
  34
  35 #include <asm/errno.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/hardware.h>
  38
  39 #include "videomodes.h"
  40 #include <asm/arch/da8xx-fb.h>
  41
  42 #define DRIVER_NAME "da8xx_lcdc"
  43
  44 #define LCD_VERSION_1   1
  45 #define LCD_VERSION_2   2
  46
  47 #define BIT(x)  (1 << (x))
  48
  49 /* LCD Status Register */
  50 #define LCD_END_OF_FRAME1               BIT(9)
  51 #define LCD_END_OF_FRAME0               BIT(8)
  52 #define LCD_PL_LOAD_DONE                BIT(6)
  53 #define LCD_FIFO_UNDERFLOW              BIT(5)
  54 #define LCD_SYNC_LOST                   BIT(2)
  55
  56 /* LCD DMA Control Register */
  57 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  58 #define LCD_DMA_BURST_SIZE_MASK         (0x7 << 4)
  59 #define LCD_DMA_BURST_1                 0x0
  60 #define LCD_DMA_BURST_2                 0x1
  61 #define LCD_DMA_BURST_4                 0x2
  62 #define LCD_DMA_BURST_8                 0x3
  63 #define LCD_DMA_BURST_16                0x4
  64 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  65 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  66 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  67 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  68
  69 /* LCD Control Register */
  70 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  71 #define LCD_RASTER_MODE                 0x01
  72
  73 /* LCD Raster Control Register */
  74 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  75 #define PALETTE_AND_DATA                0x00
  76 #define PALETTE_ONLY                    0x01
  77 #define DATA_ONLY                       0x02
  78
  79 #define LCD_MONO_8BIT_MODE              BIT(9)
  80 #define LCD_RASTER_ORDER                BIT(8)
  81 #define LCD_TFT_MODE                    BIT(7)
  82 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  83 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  84 #define LCD_V1_PL_INT_ENA               BIT(4)
  85 #define LCD_V2_PL_INT_ENA               BIT(6)
  86 #define LCD_MONOCHROME_MODE             BIT(1)
  87 #define LCD_RASTER_ENABLE               BIT(0)
  88 #define LCD_TFT_ALT_ENABLE              BIT(23)
  89 #define LCD_STN_565_ENABLE              BIT(24)
  90 #define LCD_TFT24                       BIT(25)
  91 #define LCD_TFT24_UNPACKED              BIT(26)
  92 #define LCD_V2_DMA_CLK_EN               BIT(2)
  93 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  94 #define LCD_V2_CORE_CLK_EN              BIT(0)
  95 #define LCD_V2_LPP_B10                  26
  96
  97 /* LCD Raster Timing 2 Register */
  98 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  99 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
 100 #define LCD_SYNC_CTRL                           BIT(25)
 101 #define LCD_SYNC_EDGE                           BIT(24)
 102 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
 103 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
 104 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
 105
 106 /* Clock reset register */
 107 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 108
 109 /* LCD Block */
 110 struct da8xx_lcd_regs {
 111         u32     revid;                          /* 0x00 */
 112         u32     ctrl;                           /* 0x04 */
 113         u32     stat;                           /* 0x08 */
 114         u32     lidd_ctrl;                      /* 0x0c */
 115         u32     lidd_cs0_conf;                  /* 0x10 */
 116         u32     lidd_cs0_addr;                  /* 0x14 */
 117         u32     lidd_cs0_data;                  /* 0x18 */
 118         u32     lidd_cs1_conf;                  /* 0x1c */
 119         u32     lidd_cs1_addr;                  /* 0x20 */
 120         u32     lidd_cs1_data;                  /* 0x24 */
 121         u32     raster_ctrl;                    /* 0x28 */
 122         u32     raster_timing_0;                /* 0x2c */
 123         u32     raster_timing_1;                /* 0x30 */
 124         u32     raster_timing_2;                /* 0x34 */
 125         u32     raster_subpanel;                /* 0x38 */
 126         u32     reserved;                       /* 0x3c */
 127         u32     dma_ctrl;                       /* 0x40 */
 128         u32     dma_frm_buf_base_addr_0;        /* 0x44 */
 129         u32     dma_frm_buf_ceiling_addr_0;     /* 0x48 */
 130         u32     dma_frm_buf_base_addr_1;        /* 0x4c */
 131         u32     dma_frm_buf_ceiling_addr_1;     /* 0x50 */
 132         u32     rsrvd1;                         /* 0x54 */
 133         u32     raw_stat;                       /* 0x58 */
 134         u32     masked_stat;                    /* 0x5c */
 135         u32     int_enable_set;                 /* 0x60 */
 136         u32     int_enable_clr;                 /* 0x64 */
 137         u32     end_of_int_ind;                 /* 0x68 */
 138         u32     clk_enable;                     /* 0x6c */
 139         u32     clk_reset;                      /* 0x70 */
 140 };
 141
 142 #define LCD_NUM_BUFFERS 1
 143
 144 #define WSI_TIMEOUT     50
 145 #define PALETTE_SIZE    256
 146 #define LEFT_MARGIN     64
 147 #define RIGHT_MARGIN    64
 148 #define UPPER_MARGIN    32
 149 #define LOWER_MARGIN    32
 150
 151 DECLARE_GLOBAL_DATA_PTR;
 152
 153 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
 154 static unsigned int lcd_revision;
 155
 156 /* graphics setup */
 157 static GraphicDevice gpanel;
 158 static const struct da8xx_panel *lcd_panel;
 159 static struct fb_info *da8xx_fb_info;
 160 static int bits_x_pixel;
 161 static u32 (*lcdc_irq_handler)(void);
 162
 163 static inline unsigned int lcdc_read(u32 *addr)
 164 {
 165         return readl(addr);
 166 }
 167
 168 static inline void lcdc_write(unsigned int val, u32 *addr)
 169 {
 170         writel(val, addr);
 171 }
 172
 173 struct da8xx_fb_par {
 174         unsigned long           p_palette_base;
 175         void                    *v_palette_base;
 176         dma_addr_t              vram_phys;
 177         unsigned long           vram_size;
 178         void                    *vram_virt;
 179         unsigned int            dma_start;
 180         unsigned int            dma_end;
 181         struct clk *lcdc_clk;
 182         int irq;
 183         unsigned short pseudo_palette[16];
 184         unsigned int palette_sz;
 185         unsigned int pxl_clk;
 186         int blank;
 187         int                     vsync_flag;
 188         int                     vsync_timeout;
 189 };
 190
 191 /* Variable Screen Information */
 192 static struct fb_var_screeninfo da8xx_fb_var = {
 193         .xoffset = 0,
 194         .yoffset = 0,
 195         .transp = {0, 0, 0},
 196         .nonstd = 0,
 197         .activate = 0,
 198         .height = -1,
 199         .width = -1,
 200         .pixclock = 46666,      /* 46us - AUO display */
 201         .accel_flags = 0,
 202         .left_margin = LEFT_MARGIN,
 203         .right_margin = RIGHT_MARGIN,
 204         .upper_margin = UPPER_MARGIN,
 205         .lower_margin = LOWER_MARGIN,
 206         .sync = 0,
 207         .vmode = FB_VMODE_NONINTERLACED
 208 };
 209
 210 static struct fb_fix_screeninfo da8xx_fb_fix = {
 211         .id = "DA8xx FB Drv",
 212         .type = FB_TYPE_PACKED_PIXELS,
 213         .type_aux = 0,
 214         .visual = FB_VISUAL_PSEUDOCOLOR,
 215         .xpanstep = 0,
 216         .ypanstep = 1,
 217         .ywrapstep = 0,
 218         .accel = FB_ACCEL_NONE
 219 };
 220
 221 static const struct display_panel disp_panel = {
 222         .panel_type = QVGA,
 223         .max_bpp = 24,
 224         .min_bpp = 16,
 225         .panel_shade = COLOR_ACTIVE,
 226 };
 227
 228 static const struct lcd_ctrl_config lcd_cfg = {
 229         &disp_panel,
 230         .ac_bias                = 255,
 231         .ac_bias_intrpt         = 0,
 232         .dma_burst_sz           = 16,
 233         .bpp                    = 1 << LCD_BPP,
 234         .fdd                    = 255,
 235         .tft_alt_mode           = 0,
 236         .stn_565_mode           = 0,
 237         .mono_8bit_mode         = 0,
 238         .invert_line_clock      = 1,
 239         .invert_frm_clock       = 1,
 240         .sync_edge              = 0,
 241         .sync_ctrl              = 1,
 242         .raster_order           = 0,
 243 };
 244
 245 /* Enable the Raster Engine of the LCD Controller */
 246 static inline void lcd_enable_raster(void)
 247 {
 248         u32 reg;
 249
 250         /* Bring LCDC out of reset */
 251         if (lcd_revision == LCD_VERSION_2)
 252                 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
 253
 254         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 255         if (!(reg & LCD_RASTER_ENABLE))
 256                 lcdc_write(reg | LCD_RASTER_ENABLE,
 257                         &da8xx_fb_reg_base->raster_ctrl);
 258 }
 259
 260 /* Disable the Raster Engine of the LCD Controller */
 261 static inline void lcd_disable_raster(void)
 262 {
 263         u32 reg;
 264
 265         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 266         if (reg & LCD_RASTER_ENABLE)
 267                 lcdc_write(reg & ~LCD_RASTER_ENABLE,
 268                         &da8xx_fb_reg_base->raster_ctrl);
 269         if (lcd_revision == LCD_VERSION_2)
 270                 /* Write 1 to reset LCDC */
 271                 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
 272 }
 273
 274 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 275 {
 276         u32 start;
 277         u32 end;
 278         u32 reg_ras;
 279         u32 reg_dma;
 280         u32 reg_int;
 281
 282         /* init reg to clear PLM (loading mode) fields */
 283         reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 284         reg_ras &= ~(3 << 20);
 285
 286         reg_dma  = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
 287
 288         if (load_mode == LOAD_DATA) {
 289                 start    = par->dma_start;
 290                 end      = par->dma_end;
 291
 292                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 293                 if (lcd_revision == LCD_VERSION_1) {
 294                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 295                 } else {
 296                         reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
 297                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 298                                 LCD_V2_END_OF_FRAME1_INT_ENA;
 299                         lcdc_write(reg_int,
 300                                 &da8xx_fb_reg_base->int_enable_set);
 301                 }
 302 #if (LCD_NUM_BUFFERS == 2)
 303                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 304                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 305                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 306                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 307                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 308 #else
 309                 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
 310                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 311                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 312                 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 313                 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 314 #endif
 315         } else if (load_mode == LOAD_PALETTE) {
 316                 start    = par->p_palette_base;
 317                 end      = start + par->palette_sz - 1;
 318
 319                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 320
 321                 if (lcd_revision == LCD_VERSION_1) {
 322                         reg_ras |= LCD_V1_PL_INT_ENA;
 323                 } else {
 324                         reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
 325                                 LCD_V2_PL_INT_ENA;
 326                         lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set);
 327                 }
 328                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 329                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 330         }
 331
 332         lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
 333         lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
 334
 335         /*
 336          * The Raster enable bit must be set after all other control fields are
 337          * set.
 338          */
 339         lcd_enable_raster();
 340 }
 341
 342 /* Configure the Burst Size of DMA */
 343 static int lcd_cfg_dma(int burst_size)
 344 {
 345         u32 reg;
 346
 347         reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
 348         reg &= ~LCD_DMA_BURST_SIZE_MASK;
 349         switch (burst_size) {
 350         case 1:
 351                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 352                 break;
 353         case 2:
 354                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 355                 break;
 356         case 4:
 357                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 358                 break;
 359         case 8:
 360                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 361                 break;
 362         case 16:
 363                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 364                 break;
 365         default:
 366                 return -EINVAL;
 367         }
 368         lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
 369
 370         return 0;
 371 }
 372
 373 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 374 {
 375         u32 reg;
 376
 377         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 378         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
 379         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 380                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 381         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 382 }
 383
 384 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 385                 int front_porch)
 386 {
 387         u32 reg;
 388
 389         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
 390         reg |= ((back_porch & 0xff) << 24)
 391             | ((front_porch & 0xff) << 16)
 392             | ((pulse_width & 0x3f) << 10);
 393         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
 394 }
 395
 396 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 397                 int front_porch)
 398 {
 399         u32 reg;
 400
 401         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
 402         reg |= ((back_porch & 0xff) << 24)
 403             | ((front_porch & 0xff) << 16)
 404             | ((pulse_width & 0x3f) << 10);
 405         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
 406 }
 407
 408 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 409 {
 410         u32 reg;
 411         u32 reg_int;
 412
 413         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
 414                                                 LCD_MONO_8BIT_MODE |
 415                                                 LCD_MONOCHROME_MODE |
 416                                                 LCD_TFT24 |
 417                                                 LCD_TFT24_UNPACKED);
 418
 419         switch (cfg->p_disp_panel->panel_shade) {
 420         case MONOCHROME:
 421                 reg |= LCD_MONOCHROME_MODE;
 422                 if (cfg->mono_8bit_mode)
 423                         reg |= LCD_MONO_8BIT_MODE;
 424                 break;
 425         case COLOR_ACTIVE:
 426                 reg |= LCD_TFT_MODE;
 427                 if (cfg->tft_alt_mode)
 428                         reg |= LCD_TFT_ALT_ENABLE;
 429                 break;
 430
 431         case COLOR_PASSIVE:
 432                 if (cfg->stn_565_mode)
 433                         reg |= LCD_STN_565_ENABLE;
 434                 break;
 435
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         /* enable additional interrupts here */
 441         if (lcd_revision == LCD_VERSION_1) {
 442                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 443         } else {
 444                 if (bits_x_pixel >= 24)
 445                         reg |= LCD_TFT24;
 446                 if (cfg->bpp == 32)
 447                         reg |= LCD_TFT24_UNPACKED;
 448                 reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
 449                         LCD_V2_UNDERFLOW_INT_ENA;
 450                 lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set);
 451         }
 452
 453         lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
 454
 455         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
 456
 457         if (cfg->sync_ctrl)
 458                 reg |= LCD_SYNC_CTRL;
 459         else
 460                 reg &= ~LCD_SYNC_CTRL;
 461
 462         if (cfg->sync_edge)
 463                 reg |= LCD_SYNC_EDGE;
 464         else
 465                 reg &= ~LCD_SYNC_EDGE;
 466
 467         if (cfg->invert_line_clock)
 468                 reg |= LCD_INVERT_LINE_CLOCK;
 469         else
 470                 reg &= ~LCD_INVERT_LINE_CLOCK;
 471
 472         if (cfg->invert_frm_clock)
 473                 reg |= LCD_INVERT_FRAME_CLOCK;
 474         else
 475                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 476
 477         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 478
 479         return 0;
 480 }
 481
 482 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 483                 u32 bpp, u32 raster_order)
 484 {
 485         u32 reg;
 486
 487         /* Set the Panel Width */
 488         /* Pixels per line = (PPL + 1)*16 */
 489         /* Pixels per line = (PPL + 1)*16 */
 490         if (lcd_revision == LCD_VERSION_1) {
 491                 /*
 492                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 493                  * pixels.
 494                  */
 495                 width &= 0x3f0;
 496         } else {
 497                 /*
 498                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 499                  * pixels.
 500                  */
 501                 width &= 0x7f0;
 502         }
 503
 504         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
 505         reg &= 0xfffffc00;
 506         if (lcd_revision == LCD_VERSION_1) {
 507                 reg |= ((width >> 4) - 1) << 4;
 508         } else {
 509                 width = (width >> 4) - 1;
 510                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 511         }
 512         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
 513
 514         /* Set the Panel Height */
 515         /* Set bits 9:0 of Lines Per Pixel */
 516         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
 517         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 518         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
 519
 520         /* Set bit 10 of Lines Per Pixel */
 521         if (lcd_revision == LCD_VERSION_2) {
 522                 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
 523                 reg |= ((height - 1) & 0x400) << 16;
 524                 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 525         }
 526
 527         /* Set the Raster Order of the Frame Buffer */
 528         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
 529         if (raster_order)
 530                 reg |= LCD_RASTER_ORDER;
 531         lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
 532
 533         switch (bpp) {
 534         case 1:
 535         case 2:
 536         case 4:
 537         case 16:
 538         case 24:
 539                 par->palette_sz = 16 * 2;
 540                 break;
 541
 542         case 8:
 543                 par->palette_sz = 256 * 2;
 544                 break;
 545
 546         default:
 547                 return -EINVAL;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 554                               unsigned blue, unsigned transp,
 555                               struct fb_info *info)
 556 {
 557         struct da8xx_fb_par *par = info->par;
 558         unsigned short *palette = par->v_palette_base;
 559         u_short pal;
 560         int update_hw = 0;
 561
 562         if (regno > 255)
 563                 return 1;
 564
 565         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 566                 return 1;
 567
 568         if (info->var.bits_per_pixel == 8) {
 569                 red >>= 4;
 570                 green >>= 8;
 571                 blue >>= 12;
 572
 573                 pal = (red & 0x0f00);
 574                 pal |= (green & 0x00f0);
 575                 pal |= (blue & 0x000f);
 576
 577                 if (palette[regno] != pal) {
 578                         update_hw = 1;
 579                         palette[regno] = pal;
 580                 }
 581         } else if ((info->var.bits_per_pixel >= 16) && regno < 16) {
 582                 red >>= (16 - info->var.red.length);
 583                 red <<= info->var.red.offset;
 584
 585                 green >>= (16 - info->var.green.length);
 586                 green <<= info->var.green.offset;
 587
 588                 blue >>= (16 - info->var.blue.length);
 589                 blue <<= info->var.blue.offset;
 590
 591                 par->pseudo_palette[regno] = red | green | blue;
 592
 593                 if (palette[0] != 0x4000) {
 594                         update_hw = 1;
 595                         palette[0] = 0x4000;
 596                 }
 597         }
 598
 599         /* Update the palette in the h/w as needed. */
 600         if (update_hw)
 601                 lcd_blit(LOAD_PALETTE, par);
 602
 603         return 0;
 604 }
 605
 606 static void lcd_reset(struct da8xx_fb_par *par)
 607 {
 608         /* Disable the Raster if previously Enabled */
 609         lcd_disable_raster();
 610
 611         /* DMA has to be disabled */
 612         lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
 613         lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
 614
 615         if (lcd_revision == LCD_VERSION_2) {
 616                 lcdc_write(0, &da8xx_fb_reg_base->int_enable_set);
 617                 /* Write 1 to reset */
 618                 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
 619                 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
 620         }
 621 }
 622
 623 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 624 {
 625         unsigned int lcd_clk, div;
 626
 627 #ifndef CONFIG_AM33XX
 628         /* Get clock from sysclk2 */
 629         lcd_clk = clk_get(2);
 630 #else
 631         lcd_clk = lcdc_clk_rate();
 632 #endif
 633         /* calculate divisor so that the resulting clock is rounded down */
 634         div = (lcd_clk + par->pxl_clk - 1)/ par->pxl_clk;
 635         if (div > 255)
 636                 div = 255;
 637         if (div < 2)
 638                 div = 2;
 639
 640         debug("LCD Clock: %u.%03uMHz Divider: 0x%08x PixClk requested: %u.%03uMHz actual: %u.%03uMHz\n",
 641                 lcd_clk / 1000000, lcd_clk / 1000 % 1000, div,
 642                 par->pxl_clk / 1000000, par->pxl_clk / 1000 % 1000,
 643                 lcd_clk / div / 1000000, lcd_clk / div / 1000 % 1000);
 644
 645         /* Configure the LCD clock divisor. */
 646         lcdc_write(LCD_CLK_DIVISOR(div) | LCD_RASTER_MODE,
 647                 &da8xx_fb_reg_base->ctrl);
 648
 649         if (lcd_revision == LCD_VERSION_2)
 650                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 651                                 LCD_V2_CORE_CLK_EN, &da8xx_fb_reg_base->clk_enable);
 652
 653 }
 654
 655 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 656                 const struct da8xx_panel *panel)
 657 {
 658         u32 bpp;
 659         int ret = 0;
 660
 661         lcd_reset(par);
 662
 663         /* Calculate the divider */
 664         lcd_calc_clk_divider(par);
 665
 666         if (panel->invert_pxl_clk)
 667                 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
 668                         LCD_INVERT_PIXEL_CLOCK),
 669                          &da8xx_fb_reg_base->raster_timing_2);
 670         else
 671                 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
 672                         ~LCD_INVERT_PIXEL_CLOCK),
 673                         &da8xx_fb_reg_base->raster_timing_2);
 674
 675         /* Configure the DMA burst size. */
 676         ret = lcd_cfg_dma(cfg->dma_burst_sz);
 677         if (ret < 0)
 678                 return ret;
 679
 680         /* Configure the AC bias properties. */
 681         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 682
 683         /* Configure the vertical and horizontal sync properties. */
 684         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 685         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 686
 687         /* Configure for display */
 688         ret = lcd_cfg_display(cfg);
 689         if (ret < 0)
 690                 return ret;
 691
 692         if (QVGA != cfg->p_disp_panel->panel_type)
 693                 return -EINVAL;
 694
 695         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 696             cfg->bpp >= cfg->p_disp_panel->min_bpp)
 697                 bpp = cfg->bpp;
 698         else
 699                 bpp = cfg->p_disp_panel->max_bpp;
 700         if (bpp == 12)
 701                 bpp = 16;
 702         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 703                                 (unsigned int)panel->height, bpp,
 704                                 cfg->raster_order);
 705         if (ret < 0)
 706                 return ret;
 707
 708         /* Configure FDD */
 709         lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
 710                        (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
 711
 712         return 0;
 713 }
 714
 715 static void lcdc_dma_start(void)
 716 {
 717         struct da8xx_fb_par *par = da8xx_fb_info->par;
 718         lcdc_write(par->dma_start,
 719                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 720         lcdc_write(par->dma_end,
 721                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 722         lcdc_write(0,
 723                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 724         lcdc_write(0,
 725                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 726 }
 727
 728 /* IRQ handler for version 2 of LCDC */
 729 static u32 lcdc_irq_handler_rev02(void)
 730 {
 731         u32 ret = 0;
 732         struct da8xx_fb_par *par = da8xx_fb_info->par;
 733         u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
 734
 735         debug("%s: stat=%08x\n", __func__, stat);
 736
 737         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 738                 debug("LCD_SYNC_LOST\n");
 739                 lcd_disable_raster();
 740                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 741                 lcd_enable_raster();
 742                 ret = LCD_SYNC_LOST;
 743         } else if (stat & LCD_PL_LOAD_DONE) {
 744                 debug("LCD_PL_LOAD_DONE\n");
 745                 /*
 746                  * Must disable raster before changing state of any control bit.
 747                  * And also must be disabled before clearing the PL loading
 748                  * interrupt via the following write to the status register. If
 749                  * this is done after then one gets multiple PL done interrupts.
 750                  */
 751                 lcd_disable_raster();
 752
 753                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 754
 755                 /* Disable PL completion inerrupt */
 756                 lcdc_write(LCD_V2_PL_INT_ENA,
 757                         &da8xx_fb_reg_base->int_enable_clr);
 758
 759                 /* Setup and start data loading mode */
 760                 lcd_blit(LOAD_DATA, par);
 761                 ret = LCD_PL_LOAD_DONE;
 762         } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
 763                 par->vsync_flag = 1;
 764                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 765
 766                 if (stat & LCD_END_OF_FRAME0) {
 767                         debug("LCD_END_OF_FRAME0\n");
 768
 769                         lcdc_write(par->dma_start,
 770                                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 771                         lcdc_write(par->dma_end,
 772                                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 773                 }
 774                 if (stat & LCD_END_OF_FRAME1) {
 775                         debug("LCD_END_OF_FRAME1\n");
 776                         lcdc_write(par->dma_start,
 777                                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 778                         lcdc_write(par->dma_end,
 779                                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 780                         par->vsync_flag = 1;
 781                 }
 782                 ret = (stat & LCD_END_OF_FRAME0) ?
 783                         LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
 784         }
 785         lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
 786         return ret;
 787 }
 788
 789 static u32 lcdc_irq_handler_rev01(void)
 790 {
 791         struct da8xx_fb_par *par = da8xx_fb_info->par;
 792         u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
 793         u32 reg_ras;
 794
 795         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 796                 debug("LCD_SYNC_LOST\n");
 797                 lcd_disable_raster();
 798                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 799                 lcd_enable_raster();
 800                 return LCD_SYNC_LOST;
 801         } else if (stat & LCD_PL_LOAD_DONE) {
 802                 debug("LCD_PL_LOAD_DONE\n");
 803                 /*
 804                  * Must disable raster before changing state of any control bit.
 805                  * And also must be disabled before clearing the PL loading
 806                  * interrupt via the following write to the status register. If
 807                  * this is done after then one gets multiple PL done interrupts.
 808                  */
 809                 lcd_disable_raster();
 810
 811                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 812
 813                 /* Disable PL completion inerrupt */
 814                 reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 815                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 816                 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
 817
 818                 /* Setup and start data loading mode */
 819                 lcd_blit(LOAD_DATA, par);
 820                 return LCD_PL_LOAD_DONE;
 821         } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
 822                 par->vsync_flag = 1;
 823                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 824
 825                 if (stat & LCD_END_OF_FRAME0) {
 826                         debug("LCD_END_OF_FRAME0\n");
 827
 828                         lcdc_write(par->dma_start,
 829                                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 830                         lcdc_write(par->dma_end,
 831                                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 832                 }
 833
 834                 if (stat & LCD_END_OF_FRAME1) {
 835                         debug("LCD_END_OF_FRAME1\n");
 836                         lcdc_write(par->dma_start,
 837                                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 838                         lcdc_write(par->dma_end,
 839                                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 840                 }
 841
 842                 return (stat & LCD_END_OF_FRAME0) ?
 843                         LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
 844         }
 845         return stat;
 846 }
 847
 848 static u32 wait_for_event(u32 event)
 849 {
 850         int timeout = 100;
 851         u32 ret;
 852
 853         do {
 854                 ret = lcdc_irq_handler();
 855                 if (ret & event)
 856                         break;
 857                 udelay(1000);
 858         } while (--timeout > 0);
 859
 860         if (timeout <= 0) {
 861                 printf("%s: event %d not hit\n", __func__, event);
 862                 return -1;
 863         }
 864
 865         return 0;
 866
 867 }
 868
 869 void *video_hw_init(void)
 870 {
 871         struct da8xx_fb_par *par;
 872         u32 size;
 873         char *p;
 874
 875         if (!lcd_panel) {
 876                 printf("Display not initialized\n");
 877                 return NULL;
 878         }
 879
 880         gpanel.winSizeX = lcd_panel->width;
 881         gpanel.winSizeY = lcd_panel->height;
 882         gpanel.plnSizeX = lcd_panel->width;
 883         gpanel.plnSizeY = lcd_panel->height;
 884
 885         switch (bits_x_pixel) {
 886         case 24:
 887                 gpanel.gdfBytesPP = 4;
 888                 gpanel.gdfIndex = GDF_32BIT_X888RGB;
 889                 break;
 890         case 16:
 891                 gpanel.gdfBytesPP = 2;
 892                 gpanel.gdfIndex = GDF_16BIT_565RGB;
 893                 break;
 894         default:
 895                 gpanel.gdfBytesPP = 1;
 896                 gpanel.gdfIndex = GDF__8BIT_INDEX;
 897         }
 898
 899         da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
 900
 901         /* Determine LCD IP Version */
 902
 903         lcd_revision = lcdc_read(&da8xx_fb_reg_base->revid);
 904         switch (lcd_revision & 0xfff00000) {
 905         case 0x4C100000:
 906                 lcd_revision = LCD_VERSION_1;
 907                 break;
 908
 909         case 0x4F200000:
 910                 lcd_revision = LCD_VERSION_2;
 911                 break;
 912
 913         default:
 914                 printf("Unknown PID Reg value 0x%08x, defaulting to LCD revision 1\n",
 915                                 lcd_revision);
 916                 lcd_revision = LCD_VERSION_1;
 917         }
 918
 919         debug("Resolution: %dx%d %d\n",
 920                 gpanel.winSizeX,
 921                 gpanel.winSizeY,
 922                 lcd_cfg.bpp);
 923
 924         size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
 925         da8xx_fb_info = malloc(size);
 926         debug("da8xx_fb_info at %p\n", da8xx_fb_info);
 927
 928         if (!da8xx_fb_info) {
 929                 printf("Memory allocation failed for fb_info\n");
 930                 return NULL;
 931         }
 932         memset(da8xx_fb_info, 0, size);
 933         p = (char *)da8xx_fb_info;
 934         da8xx_fb_info->par = p +  sizeof(struct fb_info);
 935         debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
 936
 937         par = da8xx_fb_info->par;
 938         par->pxl_clk = lcd_panel->pxl_clk;
 939
 940         if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
 941                 printf("lcd_init failed\n");
 942                 goto err_release_fb;
 943         }
 944
 945         /* allocate frame buffer */
 946         par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
 947         par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
 948
 949 #ifdef CONFIG_LCD
 950         par->vram_virt = lcd_base;
 951 #else
 952         par->vram_virt = malloc(par->vram_size);
 953 #endif
 954         par->vram_phys = (dma_addr_t) par->vram_virt;
 955         debug("Requesting 0x%lx bytes for framebuffer at 0x%p\n",
 956                 par->vram_size, par->vram_virt);
 957         if (!par->vram_virt) {
 958                 printf("GLCD: malloc for frame buffer failed\n");
 959                 goto err_release_fb;
 960         }
 961
 962         gpanel.frameAdrs = (unsigned int)par->vram_virt;
 963         da8xx_fb_info->screen_base = par->vram_virt;
 964         da8xx_fb_fix.smem_start = gpanel.frameAdrs;
 965         da8xx_fb_fix.smem_len = par->vram_size;
 966         da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
 967         debug("%s: vram_virt: %p size %ux%u=%lu bpp %u\n", __func__,
 968                 par->vram_virt, lcd_panel->width, lcd_panel->height,
 969                 par->vram_size, lcd_cfg.bpp);
 970         par->dma_start = par->vram_phys;
 971         par->dma_end   = par->dma_start + lcd_panel->height *
 972                 da8xx_fb_fix.line_length - 1;
 973
 974         /* allocate palette buffer */
 975         par->v_palette_base = malloc(PALETTE_SIZE);
 976         if (!par->v_palette_base) {
 977                 printf("GLCD: malloc for palette buffer failed\n");
 978                 goto err_release_fb_mem;
 979         }
 980         memset(par->v_palette_base, 0, PALETTE_SIZE);
 981         par->p_palette_base = (unsigned long)par->v_palette_base;
 982
 983         /* Initialize var */
 984         da8xx_fb_var.xres = lcd_panel->width;
 985         da8xx_fb_var.xres_virtual = lcd_panel->width;
 986
 987         da8xx_fb_var.yres         = lcd_panel->height;
 988         da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
 989
 990         da8xx_fb_var.grayscale =
 991             lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
 992         da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
 993
 994         da8xx_fb_var.hsync_len = lcd_panel->hsw;
 995         da8xx_fb_var.vsync_len = lcd_panel->vsw;
 996
 997         /* Initialize fbinfo */
 998         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
 999         da8xx_fb_info->fix = da8xx_fb_fix;
1000         da8xx_fb_info->var = da8xx_fb_var;
1001         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1002         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1003                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1004
1005         if (lcd_revision == LCD_VERSION_1)
1006                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1007         else
1008                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1009
1010         /* Clear interrupt */
1011         memset(par->vram_virt, 0, par->vram_size);
1012         lcd_disable_raster();
1013         lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1014         debug("Palette at 0x%08lx size %u\n", par->p_palette_base,
1015                 par->palette_sz);
1016         lcdc_dma_start();
1017
1018         /* Load a default palette */
1019         fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1020
1021         /* Check that the palette is loaded */
1022         wait_for_event(LCD_PL_LOAD_DONE);
1023
1024         /* Wait until DMA is working */
1025         wait_for_event(LCD_END_OF_FRAME0);
1026
1027         return &gpanel;
1028
1029 err_release_fb_mem:
1030 #ifndef CONFIG_LCD
1031         free(par->vram_virt);
1032 #endif
1033
1034 err_release_fb:
1035         free(da8xx_fb_info);
1036
1037         return NULL;
1038 }
1039
1040 void da8xx_fb_disable(void)
1041 {
1042         lcd_reset(da8xx_fb_info->par);
1043 }
1044
1045 void video_set_lut(unsigned int index,  /* color number */
1046                     unsigned char r,    /* red */
1047                     unsigned char g,    /* green */
1048                     unsigned char b     /* blue */
1049                     )
1050 {
1051 }
1052
1053 void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
1054 {
1055         lcd_panel = panel;
1056         bits_x_pixel = bits_pixel;
1057 }