drivers/video/exynos_fimd.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <config.h>
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <lcd.h>
  27 #include <div64.h>
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/cpu.h>
  31 #include "exynos_fb.h"
  32
  33 static unsigned long *lcd_base_addr;
  34 static vidinfo_t *pvid;
  35
  36 void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
  37                 u_long palette_size)
  38 {
  39         lcd_base_addr = (unsigned long *)screen_base;
  40 }
  41
  42 static void exynos_fimd_set_dualrgb(unsigned int enabled)
  43 {
  44         struct exynos4_fb *fimd_ctrl =
  45                 (struct exynos4_fb *)samsung_get_base_fimd();
  46         unsigned int cfg = 0;
  47
  48         if (enabled) {
  49                 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
  50                         EXYNOS_DUALRGB_VDEN_EN_ENABLE;
  51
  52                 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
  53                 cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
  54                         EXYNOS_DUALRGB_MAIN_CNT(0);
  55         }
  56
  57         writel(cfg, &fimd_ctrl->dualrgb);
  58 }
  59
  60 static void exynos_fimd_set_par(unsigned int win_id)
  61 {
  62         unsigned int cfg = 0;
  63         struct exynos4_fb *fimd_ctrl =
  64                 (struct exynos4_fb *)samsung_get_base_fimd();
  65
  66         /* set window control */
  67         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
  68                         EXYNOS_WINCON(win_id));
  69
  70         cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
  71                 EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
  72                 EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
  73                 EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
  74
  75         /* DATAPATH is DMA */
  76         cfg |= EXYNOS_WINCON_DATAPATH_DMA;
  77
  78         /* bpp is 32 */
  79         cfg |= EXYNOS_WINCON_WSWP_ENABLE;
  80
  81         /* dma burst is 16 */
  82         cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
  83
  84         /* pixel format is unpacked RGB888 */
  85         cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
  86
  87         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
  88                         EXYNOS_WINCON(win_id));
  89
  90         /* set window position to x=0, y=0*/
  91         cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
  92         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
  93                         EXYNOS_VIDOSD(win_id));
  94
  95         cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
  96                 EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
  97         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
  98                         EXYNOS_VIDOSD(win_id));
  99
 100         /* set window size for window0*/
 101         cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
 102         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
 103                         EXYNOS_VIDOSD(win_id));
 104 }
 105
 106 static void exynos_fimd_set_buffer_address(unsigned int win_id)
 107 {
 108         unsigned long start_addr, end_addr;
 109         struct exynos4_fb *fimd_ctrl =
 110                 (struct exynos4_fb *)samsung_get_base_fimd();
 111
 112         start_addr = (unsigned long)lcd_base_addr;
 113         end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
 114                                 pvid->vl_row);
 115
 116         writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
 117                         EXYNOS_BUFFER_OFFSET(win_id));
 118         writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
 119                         EXYNOS_BUFFER_OFFSET(win_id));
 120 }
 121
 122 static void exynos_fimd_set_clock(vidinfo_t *pvid)
 123 {
 124         unsigned int cfg = 0, div = 0, remainder, remainder_div;
 125         unsigned long pixel_clock;
 126         unsigned long long src_clock;
 127         struct exynos4_fb *fimd_ctrl =
 128                 (struct exynos4_fb *)samsung_get_base_fimd();
 129
 130         if (pvid->dual_lcd_enabled) {
 131                 pixel_clock = pvid->vl_freq *
 132                                 (pvid->vl_hspw + pvid->vl_hfpd +
 133                                  pvid->vl_hbpd + pvid->vl_col / 2) *
 134                                 (pvid->vl_vspw + pvid->vl_vfpd +
 135                                  pvid->vl_vbpd + pvid->vl_row);
 136         } else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
 137                 pixel_clock = pvid->vl_freq *
 138                                 pvid->vl_width * pvid->vl_height *
 139                                 (pvid->cs_setup + pvid->wr_setup +
 140                                  pvid->wr_act + pvid->wr_hold + 1);
 141         } else {
 142                 pixel_clock = pvid->vl_freq *
 143                                 (pvid->vl_hspw + pvid->vl_hfpd +
 144                                  pvid->vl_hbpd + pvid->vl_col) *
 145                                 (pvid->vl_vspw + pvid->vl_vfpd +
 146                                  pvid->vl_vbpd + pvid->vl_row);
 147         }
 148
 149         cfg = readl(&fimd_ctrl->vidcon0);
 150         cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
 151                 EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
 152                 EXYNOS_VIDCON0_CLKDIR_MASK);
 153         cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
 154                 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
 155
 156         if (pixel_clock > MAX_CLOCK)
 157                 pixel_clock = MAX_CLOCK;
 158
 159         src_clock = (unsigned long long) get_lcd_clk();
 160
 161         /* get quotient and remainder. */
 162         remainder = do_div(src_clock, pixel_clock);
 163         div = src_clock;
 164
 165         remainder *= 10;
 166         remainder_div = remainder / pixel_clock;
 167
 168         /* round about one places of decimals. */
 169         if (remainder_div >= 5)
 170                 div++;
 171
 172         /* in case of dual lcd mode. */
 173         if (pvid->dual_lcd_enabled)
 174                 div--;
 175
 176         cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
 177         writel(cfg, &fimd_ctrl->vidcon0);
 178 }
 179
 180 void exynos_set_trigger(void)
 181 {
 182         unsigned int cfg = 0;
 183         struct exynos4_fb *fimd_ctrl =
 184                 (struct exynos4_fb *)samsung_get_base_fimd();
 185
 186         cfg = readl(&fimd_ctrl->trigcon);
 187
 188         cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
 189
 190         writel(cfg, &fimd_ctrl->trigcon);
 191 }
 192
 193 int exynos_is_i80_frame_done(void)
 194 {
 195         unsigned int cfg = 0;
 196         int status;
 197         struct exynos4_fb *fimd_ctrl =
 198                 (struct exynos4_fb *)samsung_get_base_fimd();
 199
 200         cfg = readl(&fimd_ctrl->trigcon);
 201
 202         /* frame done func is valid only when TRIMODE[0] is set to 1. */
 203         status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
 204                         EXYNOS_I80STATUS_TRIG_DONE;
 205
 206         return status;
 207 }
 208
 209 static void exynos_fimd_lcd_on(void)
 210 {
 211         unsigned int cfg = 0;
 212         struct exynos4_fb *fimd_ctrl =
 213                 (struct exynos4_fb *)samsung_get_base_fimd();
 214
 215         /* display on */
 216         cfg = readl(&fimd_ctrl->vidcon0);
 217         cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
 218         writel(cfg, &fimd_ctrl->vidcon0);
 219 }
 220
 221 static void exynos_fimd_window_on(unsigned int win_id)
 222 {
 223         unsigned int cfg = 0;
 224         struct exynos4_fb *fimd_ctrl =
 225                 (struct exynos4_fb *)samsung_get_base_fimd();
 226
 227         /* enable window */
 228         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
 229                         EXYNOS_WINCON(win_id));
 230         cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
 231         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 232                         EXYNOS_WINCON(win_id));
 233
 234         cfg = readl(&fimd_ctrl->winshmap);
 235         cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
 236         writel(cfg, &fimd_ctrl->winshmap);
 237 }
 238
 239 void exynos_fimd_lcd_off(void)
 240 {
 241         unsigned int cfg = 0;
 242         struct exynos4_fb *fimd_ctrl =
 243                 (struct exynos4_fb *)samsung_get_base_fimd();
 244
 245         cfg = readl(&fimd_ctrl->vidcon0);
 246         cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
 247         writel(cfg, &fimd_ctrl->vidcon0);
 248 }
 249
 250 void exynos_fimd_window_off(unsigned int win_id)
 251 {
 252         unsigned int cfg = 0;
 253         struct exynos4_fb *fimd_ctrl =
 254                 (struct exynos4_fb *)samsung_get_base_fimd();
 255
 256         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
 257                         EXYNOS_WINCON(win_id));
 258         cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
 259         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 260                         EXYNOS_WINCON(win_id));
 261
 262         cfg = readl(&fimd_ctrl->winshmap);
 263         cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
 264         writel(cfg, &fimd_ctrl->winshmap);
 265 }
 266
 267 void exynos_fimd_lcd_init(vidinfo_t *vid)
 268 {
 269         unsigned int cfg = 0, rgb_mode;
 270         struct exynos4_fb *fimd_ctrl =
 271                 (struct exynos4_fb *)samsung_get_base_fimd();
 272
 273         /* store panel info to global variable */
 274         pvid = vid;
 275
 276         rgb_mode = MODE_RGB_P;
 277
 278         if (vid->interface_mode == FIMD_RGB_INTERFACE) {
 279                 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
 280                 writel(cfg, &fimd_ctrl->vidcon0);
 281
 282                 cfg = readl(&fimd_ctrl->vidcon2);
 283                 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
 284                         EXYNOS_VIDCON2_TVFORMATSEL_MASK |
 285                         EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
 286                 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
 287                 writel(cfg, &fimd_ctrl->vidcon2);
 288
 289                 /* set polarity */
 290                 cfg = 0;
 291                 if (!pvid->vl_clkp)
 292                         cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
 293                 if (!pvid->vl_hsp)
 294                         cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
 295                 if (!pvid->vl_vsp)
 296                         cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
 297                 if (!pvid->vl_dp)
 298                         cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
 299
 300                 writel(cfg, &fimd_ctrl->vidcon1);
 301
 302                 /* set timing */
 303                 cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
 304                 cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
 305                 cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
 306                 writel(cfg, &fimd_ctrl->vidtcon0);
 307
 308                 cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
 309                 cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
 310                 cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
 311
 312                 writel(cfg, &fimd_ctrl->vidtcon1);
 313
 314                 /* set lcd size */
 315                 cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1);
 316                 cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1);
 317
 318                 writel(cfg, &fimd_ctrl->vidtcon2);
 319         }
 320
 321         /* set display mode */
 322         cfg = readl(&fimd_ctrl->vidcon0);
 323         cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
 324         cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
 325         writel(cfg, &fimd_ctrl->vidcon0);
 326
 327         /* set par */
 328         exynos_fimd_set_par(pvid->win_id);
 329
 330         /* set memory address */
 331         exynos_fimd_set_buffer_address(pvid->win_id);
 332
 333         /* set buffer size */
 334         cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8);
 335         writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
 336                                         EXYNOS_BUFFER_SIZE(pvid->win_id));
 337
 338         /* set clock */
 339         exynos_fimd_set_clock(pvid);
 340
 341         /* set rgb mode to dual lcd. */
 342         exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
 343
 344         /* display on */
 345         exynos_fimd_lcd_on();
 346
 347         /* window on */
 348         exynos_fimd_window_on(pvid->win_id);
 349 }
 350
 351 unsigned long exynos_fimd_calc_fbsize(void)
 352 {
 353         return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
 354 }