drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /* #define DEBUG */
  15 #include <common.h>
  16 #include <ipu.h>
  17 #include <linux/types.h>
  18 #include <linux/err.h>
  19 #include <asm/io.h>
  20 #include <asm/errno.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/arch/clock.h>
  24
  25 #include "ipu_regs.h"
  26
  27 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
  28
  29 struct ipu_ch_param_word {
  30         uint32_t data[5];
  31         uint32_t res[3];
  32 };
  33
  34 struct ipu_ch_param {
  35         struct ipu_ch_param_word word[2];
  36 };
  37
  38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  39
  40 #define _param_word(base, w) \
  41         (((struct ipu_ch_param *)(base))->word[w].data)
  42
  43 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
  44         int i = (bit) / 32;                                             \
  45         int off = (bit) % 32;                                           \
  46         _param_word(base, w)[i] |= (v) << off;                          \
  47         if (((bit) + (size) - 1) / 32 > i) {                            \
  48                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  49         }                                                               \
  50 }
  51
  52 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
  53         int i = (bit) / 32;                                     \
  54         int off = (bit) % 32;                                   \
  55         u32 mask = (1UL << size) - 1;                           \
  56         u32 temp = _param_word(base, w)[i];                     \
  57         temp &= ~(mask << off);                                 \
  58         _param_word(base, w)[i] = temp | (v) << off;            \
  59         if (((bit) + (size) - 1) / 32 > i) {                    \
  60                 temp = _param_word(base, w)[i + 1];             \
  61                 temp &= ~(mask >> (32 - off));                  \
  62                 _param_word(base, w)[i + 1] =                   \
  63                         temp | ((v) >> (off ? (32 - off) : 0)); \
  64         }                                                       \
  65 }
  66
  67 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
  68         u32 temp2;                                              \
  69         int i = (bit) / 32;                                     \
  70         int off = (bit) % 32;                                   \
  71         u32 mask = (1UL << size) - 1;                           \
  72         u32 temp1 = _param_word(base, w)[i];                    \
  73         temp1 = mask & (temp1 >> off);                          \
  74         if (((bit)+(size) - 1) / 32 > i) {                      \
  75                 temp2 = _param_word(base, w)[i + 1];            \
  76                 temp2 &= mask >> (off ? (32 - off) : 0);        \
  77                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
  78         }                                                       \
  79         temp1;                                                  \
  80 })
  81
  82 #define IPU_SW_RST_TOUT_USEC    (10000)
  83
  84 static int clk_ipu_enable(struct clk *clk)
  85 {
  86         ipu_clk_enable();
  87         return 0;
  88 }
  89
  90 static void clk_ipu_disable(struct clk *clk)
  91 {
  92         ipu_clk_disable();
  93 }
  94
  95 static struct clk ipu_clk = {
  96         .name = "ipu_clk",
  97         .rate = CONFIG_IPUV3_CLK,
  98 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  99         .enable_reg = (u32 *)(CCM_BASE_ADDR +
 100                 offsetof(struct mxc_ccm_reg, CCGR5)),
 101         .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 102 #else
 103         .enable_reg = (u32 *)(CCM_BASE_ADDR +
 104                 offsetof(struct mxc_ccm_reg, CCGR3)),
 105         .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
 106 #endif
 107         .enable = clk_ipu_enable,
 108         .disable = clk_ipu_disable,
 109 };
 110
 111 static struct clk ldb_clk = {
 112         .name = "ldb_clk",
 113         .rate = 65000000,
 114 };
 115
 116 /* Globals */
 117 struct clk *g_ipu_clk;
 118 struct clk *g_ldb_clk;
 119 struct clk *g_di_clk[2];
 120 struct clk *g_pixel_clk[2];
 121 unsigned char g_dc_di_assignment[10];
 122 int g_ipu_clk_enabled;
 123 u32 *ipu_dc_tmpl_reg;
 124
 125 static uint32_t g_channel_init_mask;
 126 static uint32_t g_channel_enable_mask;
 127 static int ipu_dc_use_count;
 128 static int ipu_dp_use_count;
 129 static int ipu_dmfc_use_count;
 130 static int ipu_di_use_count[2];
 131
 132 static u32 *ipu_cpmem_base;
 133
 134 /* Static functions */
 135
 136 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 137 {
 138         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 139 };
 140
 141 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 142 {
 143         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 144 };
 145
 146 /* Either DP BG or DP FG can be graphic window */
 147 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 148 {
 149         return (dma_chan == 23 || dma_chan == 27);
 150 }
 151
 152 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 153 {
 154         return ((dma_chan >= 23) && (dma_chan <= 29));
 155 }
 156
 157
 158 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 159                                             dma_addr_t phyaddr)
 160 {
 161         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 162                                phyaddr / 8);
 163 };
 164
 165 #define idma_is_valid(ch)       (ch != NO_DMA)
 166 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 167 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 168
 169 static void ipu_pixel_clk_recalc(struct clk *clk)
 170 {
 171         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 172         if (div == 0)
 173                 clk->rate = 0;
 174         else
 175                 clk->rate = (clk->parent->rate * 16) / div;
 176 }
 177
 178 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 179         unsigned long rate)
 180 {
 181         u32 div, div1;
 182         u64 tmp;
 183         /*
 184          * Calculate divider
 185          * Fractional part is 4 bits,
 186          * so simply multiply by 2^4 to get fractional part.
 187          */
 188         tmp = (u64)clk->parent->rate * 16;
 189         div = tmp / rate;
 190
 191         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 192                 div = 0x10;
 193         if (div & ~0xFEF)
 194                 div &= 0xFF8;
 195         else {
 196                 div1 = div & 0xFE0;
 197                 if ((tmp/div1 - tmp/div) < rate / 4)
 198                         div = div1;
 199                 else
 200                         div &= 0xFF8;
 201         }
 202         tmp /= div;
 203 #if 1
 204         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
 205                 rate / 1000000, rate / 1000 % 1000,
 206                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 207                 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
 208 #endif
 209         return tmp;
 210 }
 211
 212 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 213 {
 214         u32 div = ((u64)clk->parent->rate * 16) / rate;
 215
 216         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
 217                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 218                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
 219
 220         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 221
 222         /* Setup pixel clock timing */
 223         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 224
 225         clk->rate = ((u64)clk->parent->rate * 16) / div;
 226         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
 227                 clk->rate / 1000000, clk->rate / 1000 % 1000);
 228         return 0;
 229 }
 230
 231 static int ipu_pixel_clk_enable(struct clk *clk)
 232 {
 233         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 234         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 235         __raw_writel(disp_gen, IPU_DISP_GEN);
 236
 237         return 0;
 238 }
 239
 240 static void ipu_pixel_clk_disable(struct clk *clk)
 241 {
 242         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 243         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 244         __raw_writel(disp_gen, IPU_DISP_GEN);
 245 }
 246
 247 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 248 {
 249         int ret;
 250         u32 di_gen;
 251
 252         ret = clk_enable(clk);
 253         if (ret)
 254                 return ret;
 255
 256         di_gen = __raw_readl(DI_GENERAL(clk->id));
 257
 258         if (parent == g_ipu_clk)
 259                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 260         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
 261                 di_gen |= DI_GEN_DI_CLK_EXT;
 262         else
 263                 goto err;
 264
 265         ret = clk_enable(parent);
 266         if (ret)
 267                 goto err;
 268         __raw_writel(di_gen, DI_GENERAL(clk->id));
 269         ipu_pixel_clk_recalc(clk);
 270         clk->disable(clk->parent);
 271         clk->parent = parent;
 272 err:
 273         clk_disable(clk);
 274         return ret;
 275 }
 276
 277 static struct clk pixel_clk[] = {
 278         {
 279                 .name = "pixel_clk",
 280                 .id = 0,
 281                 .recalc = ipu_pixel_clk_recalc,
 282                 .set_rate = ipu_pixel_clk_set_rate,
 283                 .round_rate = ipu_pixel_clk_round_rate,
 284                 .set_parent = ipu_pixel_clk_set_parent,
 285                 .enable = ipu_pixel_clk_enable,
 286                 .disable = ipu_pixel_clk_disable,
 287         },
 288         {
 289                 .name = "pixel_clk",
 290                 .id = 1,
 291                 .recalc = ipu_pixel_clk_recalc,
 292                 .set_rate = ipu_pixel_clk_set_rate,
 293                 .round_rate = ipu_pixel_clk_round_rate,
 294                 .set_parent = ipu_pixel_clk_set_parent,
 295                 .enable = ipu_pixel_clk_enable,
 296                 .disable = ipu_pixel_clk_disable,
 297         },
 298 };
 299
 300 static struct clk di_clk[] = {
 301         {
 302                 .name = "ipu_di_clk",
 303                 .id = 0,
 304         },
 305         {
 306                 .name = "ipu_di_clk",
 307                 .id = 1,
 308         },
 309 };
 310
 311 /*
 312  * This function resets IPU
 313  */
 314 void ipu_reset(void)
 315 {
 316         u32 *reg;
 317         u32 value;
 318         int timeout = IPU_SW_RST_TOUT_USEC;
 319
 320         reg = (u32 *)SRC_BASE_ADDR;
 321         value = __raw_readl(reg);
 322         value = value | SW_IPU_RST;
 323         __raw_writel(value, reg);
 324
 325         while (__raw_readl(reg) & SW_IPU_RST) {
 326                 udelay(1);
 327                 if (!(timeout--)) {
 328                         printf("ipu software reset timeout\n");
 329                         break;
 330                 }
 331         };
 332 }
 333
 334 /*
 335  * This function is called by the driver framework to initialize the IPU
 336  * hardware.
 337  *
 338  * @param       dev     The device structure for the IPU passed in by the
 339  *                      driver framework.
 340  *
 341  * @return      Returns 0 on success or negative error code on error
 342  */
 343 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
 344 {
 345         int ret;
 346         void *ipu_base;
 347         unsigned long start;
 348 #if defined CONFIG_MX51
 349         u32 temp;
 350         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 351         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 352
 353          __raw_writel(0xF00, reg_hsc_mcd);
 354
 355         /* CSI mode reserved */
 356         temp = __raw_readl(reg_hsc_mxt_conf);
 357          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 358
 359         temp = __raw_readl(reg_hsc_mxt_conf);
 360         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 361 #endif
 362         ipu_base = (void *)IPU_SOC_BASE_ADDR;
 363         /* base fixup */
 364         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
 365                 ipu_base += IPUV3H_REG_BASE;
 366         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
 367                 ipu_base += IPUV3M_REG_BASE;
 368         else                    /* IPUv3D, v3E, v3EX */
 369                 ipu_base += IPUV3DEX_REG_BASE;
 370         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
 371         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
 372
 373         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
 374
 375         g_pixel_clk[0] = &pixel_clk[0];
 376         g_pixel_clk[1] = &pixel_clk[1];
 377
 378         g_di_clk[0] = &di_clk[0];
 379         g_di_clk[1] = &di_clk[1];
 380         g_di_clk[di]->rate = di_clk_val;
 381
 382         g_ipu_clk = &ipu_clk;
 383         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 384
 385         g_ldb_clk = &ldb_clk;
 386         debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
 387
 388         ret = clk_enable(g_ipu_clk);
 389         if (ret)
 390                 return ret;
 391         ipu_reset();
 392
 393         if (di_clk_parent == DI_PCLK_LDB) {
 394                 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
 395         } else {
 396                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 397                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 398         }
 399
 400         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 401         start = get_timer_masked();
 402         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
 403                 if (get_timer(start) > CONFIG_SYS_HZ)
 404                         return -ETIME;
 405         }
 406
 407         ipu_init_dc_mappings();
 408
 409         __raw_writel(0, IPU_INT_CTRL(5));
 410         __raw_writel(0, IPU_INT_CTRL(6));
 411         __raw_writel(0, IPU_INT_CTRL(9));
 412         __raw_writel(0, IPU_INT_CTRL(10));
 413
 414         /* DMFC Init */
 415         ipu_dmfc_init(DMFC_NORMAL, 1);
 416
 417         /* Set sync refresh channels as high priority */
 418         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 419
 420         /* Set MCU_T to divide MCU access window into 2 */
 421         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 422
 423         clk_disable(g_ipu_clk);
 424
 425         return 0;
 426 }
 427
 428 void ipu_dump_registers(void)
 429 {
 430         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
 431         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
 432         debug("IDMAC_CHA_EN1        0x%08X\n",
 433                __raw_readl(IDMAC_CHA_EN(0)));
 434         debug("IDMAC_CHA_EN2        0x%08X\n",
 435                __raw_readl(IDMAC_CHA_EN(32)));
 436         debug("IDMAC_CHA_PRI1       0x%08X\n",
 437                __raw_readl(IDMAC_CHA_PRI(0)));
 438         debug("IDMAC_CHA_PRI2       0x%08X\n",
 439                __raw_readl(IDMAC_CHA_PRI(32)));
 440         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
 441                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 442         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
 443                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 444         debug("DMFC_WR_CHAN         0x%08X\n",
 445                __raw_readl(DMFC_WR_CHAN));
 446         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
 447                __raw_readl(DMFC_WR_CHAN_DEF));
 448         debug("DMFC_DP_CHAN         0x%08X\n",
 449                __raw_readl(DMFC_DP_CHAN));
 450         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
 451                __raw_readl(DMFC_DP_CHAN_DEF));
 452         debug("DMFC_IC_CTRL         0x%08X\n",
 453                __raw_readl(DMFC_IC_CTRL));
 454         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
 455                __raw_readl(IPU_FS_PROC_FLOW1));
 456         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
 457                __raw_readl(IPU_FS_PROC_FLOW2));
 458         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
 459                __raw_readl(IPU_FS_PROC_FLOW3));
 460         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
 461                __raw_readl(IPU_FS_DISP_FLOW1));
 462 }
 463
 464 /*
 465  * This function is called to initialize a logical IPU channel.
 466  *
 467  * @param       channel Input parameter for the logical channel ID to init.
 468  *
 469  * @param       params  Input parameter containing union of channel
 470  *                      initialization parameters.
 471  *
 472  * @return      Returns 0 on success or negative error code on fail
 473  */
 474 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 475 {
 476         int ret = 0;
 477         uint32_t ipu_conf;
 478
 479         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 480
 481         if (g_ipu_clk_enabled == 0) {
 482                 g_ipu_clk_enabled = 1;
 483                 clk_enable(g_ipu_clk);
 484         }
 485
 486
 487         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 488                 printf("Warning: channel already initialized %d\n",
 489                         IPU_CHAN_ID(channel));
 490         }
 491
 492         ipu_conf = __raw_readl(IPU_CONF);
 493
 494         switch (channel) {
 495         case MEM_DC_SYNC:
 496                 if (params->mem_dc_sync.di > 1) {
 497                         ret = -EINVAL;
 498                         goto err;
 499                 }
 500
 501                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 502                 ipu_dc_init(1, params->mem_dc_sync.di,
 503                              params->mem_dc_sync.interlaced);
 504                 ipu_di_use_count[params->mem_dc_sync.di]++;
 505                 ipu_dc_use_count++;
 506                 ipu_dmfc_use_count++;
 507                 break;
 508         case MEM_BG_SYNC:
 509                 if (params->mem_dp_bg_sync.di > 1) {
 510                         ret = -EINVAL;
 511                         goto err;
 512                 }
 513
 514                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 515                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 516                              params->mem_dp_bg_sync.out_pixel_fmt);
 517                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 518                              params->mem_dp_bg_sync.interlaced);
 519                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 520                 ipu_dc_use_count++;
 521                 ipu_dp_use_count++;
 522                 ipu_dmfc_use_count++;
 523                 break;
 524         case MEM_FG_SYNC:
 525                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 526                              params->mem_dp_fg_sync.out_pixel_fmt);
 527
 528                 ipu_dc_use_count++;
 529                 ipu_dp_use_count++;
 530                 ipu_dmfc_use_count++;
 531                 break;
 532         default:
 533                 printf("Missing channel initialization\n");
 534         }
 535
 536         /* Enable IPU sub module */
 537         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 538         if (ipu_dc_use_count == 1)
 539                 ipu_conf |= IPU_CONF_DC_EN;
 540         if (ipu_dp_use_count == 1)
 541                 ipu_conf |= IPU_CONF_DP_EN;
 542         if (ipu_dmfc_use_count == 1)
 543                 ipu_conf |= IPU_CONF_DMFC_EN;
 544         if (ipu_di_use_count[0] == 1) {
 545                 ipu_conf |= IPU_CONF_DI0_EN;
 546         }
 547         if (ipu_di_use_count[1] == 1) {
 548                 ipu_conf |= IPU_CONF_DI1_EN;
 549         }
 550
 551         __raw_writel(ipu_conf, IPU_CONF);
 552
 553 err:
 554         return ret;
 555 }
 556
 557 /*
 558  * This function is called to uninitialize a logical IPU channel.
 559  *
 560  * @param       channel Input parameter for the logical channel ID to uninit.
 561  */
 562 void ipu_uninit_channel(ipu_channel_t channel)
 563 {
 564         uint32_t reg;
 565         uint32_t in_dma, out_dma = 0;
 566         uint32_t ipu_conf;
 567
 568         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 569                 debug("Channel already uninitialized %d\n",
 570                         IPU_CHAN_ID(channel));
 571                 return;
 572         }
 573
 574         /*
 575          * Make sure channel is disabled
 576          * Get input and output dma channels
 577          */
 578         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 579         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 580
 581         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 582             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 583                 printf("Channel %d is not disabled, disable first\n",
 584                         IPU_CHAN_ID(channel));
 585                 return;
 586         }
 587
 588         ipu_conf = __raw_readl(IPU_CONF);
 589
 590         /* Reset the double buffer */
 591         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 592         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 593         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 594         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 595
 596         switch (channel) {
 597         case MEM_DC_SYNC:
 598                 ipu_dc_uninit(1);
 599                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 600                 ipu_dc_use_count--;
 601                 ipu_dmfc_use_count--;
 602                 break;
 603         case MEM_BG_SYNC:
 604                 ipu_dp_uninit(channel);
 605                 ipu_dc_uninit(5);
 606                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 607                 ipu_dc_use_count--;
 608                 ipu_dp_use_count--;
 609                 ipu_dmfc_use_count--;
 610                 break;
 611         case MEM_FG_SYNC:
 612                 ipu_dp_uninit(channel);
 613                 ipu_dc_use_count--;
 614                 ipu_dp_use_count--;
 615                 ipu_dmfc_use_count--;
 616                 break;
 617         default:
 618                 break;
 619         }
 620
 621         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 622
 623         if (ipu_dc_use_count == 0)
 624                 ipu_conf &= ~IPU_CONF_DC_EN;
 625         if (ipu_dp_use_count == 0)
 626                 ipu_conf &= ~IPU_CONF_DP_EN;
 627         if (ipu_dmfc_use_count == 0)
 628                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 629         if (ipu_di_use_count[0] == 0) {
 630                 ipu_conf &= ~IPU_CONF_DI0_EN;
 631         }
 632         if (ipu_di_use_count[1] == 0) {
 633                 ipu_conf &= ~IPU_CONF_DI1_EN;
 634         }
 635
 636         __raw_writel(ipu_conf, IPU_CONF);
 637
 638         /* clear interrupt status */
 639         __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
 640
 641         if (ipu_conf == 0) {
 642                 clk_disable(g_ipu_clk);
 643                 g_ipu_clk_enabled = 0;
 644         }
 645 }
 646
 647 static inline void ipu_ch_param_dump(int ch)
 648 {
 649 #ifdef DEBUG
 650         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 651         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 652                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 653                  p->word[0].data[3], p->word[0].data[4]);
 654         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 655                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 656                  p->word[1].data[3], p->word[1].data[4]);
 657         debug("PFS 0x%x, ",
 658                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 659         debug("BPP 0x%x, ",
 660                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 661         debug("NPB 0x%x\n",
 662                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 663
 664         debug("FW %d, ",
 665                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 666         debug("FH %d, ",
 667                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 668         debug("Stride %d\n",
 669                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 670
 671         debug("Width0 %d+1, ",
 672                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 673         debug("Width1 %d+1, ",
 674                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 675         debug("Width2 %d+1, ",
 676                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 677         debug("Width3 %d+1, ",
 678                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 679         debug("Offset0 %d, ",
 680                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 681         debug("Offset1 %d, ",
 682                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 683         debug("Offset2 %d, ",
 684                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 685         debug("Offset3 %d\n",
 686                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 687 #endif
 688 }
 689
 690 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 691                                               int red_width, int red_offset,
 692                                               int green_width, int green_offset,
 693                                               int blue_width, int blue_offset,
 694                                               int alpha_width, int alpha_offset)
 695 {
 696         /* Setup red width and offset */
 697         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 698         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 699         /* Setup green width and offset */
 700         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 701         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 702         /* Setup blue width and offset */
 703         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 704         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 705         /* Setup alpha width and offset */
 706         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 707         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 708 }
 709
 710 static void ipu_ch_param_init(int ch,
 711                               uint32_t pixel_fmt, uint32_t width,
 712                               uint32_t height, uint32_t stride,
 713                               uint32_t u, uint32_t v,
 714                               uint32_t uv_stride, dma_addr_t addr0,
 715                               dma_addr_t addr1)
 716 {
 717         uint32_t u_offset = 0;
 718         uint32_t v_offset = 0;
 719
 720         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
 721
 722         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 723                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
 724                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
 725         } else {
 726                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
 727                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
 728         }
 729
 730         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
 731         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
 732
 733         switch (pixel_fmt) {
 734         case IPU_PIX_FMT_GENERIC:
 735                 /*Represents 8-bit Generic data */
 736                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
 737                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
 738                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
 739
 740                 break;
 741         case IPU_PIX_FMT_GENERIC_32:
 742                 /*Represents 32-bit Generic data */
 743                 break;
 744         case IPU_PIX_FMT_RGB565:
 745                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 746                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 747                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 748
 749                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
 750                 break;
 751         case IPU_PIX_FMT_BGR24:
 752                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 753                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 754                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 755
 756                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 757                 break;
 758         case IPU_PIX_FMT_RGB24:
 759         case IPU_PIX_FMT_YUV444:
 760                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 761                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 762                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 763
 764                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
 765                 break;
 766         case IPU_PIX_FMT_BGRA32:
 767         case IPU_PIX_FMT_BGR32:
 768                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 769                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 770                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 771
 772                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
 773                 break;
 774         case IPU_PIX_FMT_RGBA32:
 775         case IPU_PIX_FMT_RGB32:
 776                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 777                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 778                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 779
 780                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
 781                 break;
 782         case IPU_PIX_FMT_ABGR32:
 783                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 784                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 785
 786                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 787                 break;
 788         case IPU_PIX_FMT_UYVY:
 789                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 790                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
 791                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 792                 break;
 793         case IPU_PIX_FMT_YUYV:
 794                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 795                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
 796                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 797                 break;
 798         case IPU_PIX_FMT_YUV420P2:
 799         case IPU_PIX_FMT_YUV420P:
 800                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
 801
 802                 if (uv_stride < stride / 2)
 803                         uv_stride = stride / 2;
 804
 805                 u_offset = stride * height;
 806                 v_offset = u_offset + (uv_stride * height / 2);
 807                 /* burst size */
 808                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 809                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
 810                         uv_stride = uv_stride*2;
 811                 } else {
 812                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
 813                 }
 814                 break;
 815         case IPU_PIX_FMT_YVU422P:
 816                 /* BPP & pixel format */
 817                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 818                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 819
 820                 if (uv_stride < stride / 2)
 821                         uv_stride = stride / 2;
 822
 823                 v_offset = (v == 0) ? stride * height : v;
 824                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 825                 break;
 826         case IPU_PIX_FMT_YUV422P:
 827                 /* BPP & pixel format */
 828                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 829                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 830
 831                 if (uv_stride < stride / 2)
 832                         uv_stride = stride / 2;
 833
 834                 u_offset = (u == 0) ? stride * height : u;
 835                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 836                 break;
 837         case IPU_PIX_FMT_NV12:
 838                 /* BPP & pixel format */
 839                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
 840                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 841                 uv_stride = stride;
 842                 u_offset = (u == 0) ? stride * height : u;
 843                 break;
 844         default:
 845                 printf("mxc ipu: unimplemented pixel format: %08x\n",
 846                         pixel_fmt);
 847         }
 848
 849
 850         if (uv_stride)
 851                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
 852
 853         /* Get the uv offset from user when need cropping */
 854         if (u || v) {
 855                 u_offset = u;
 856                 v_offset = v;
 857         }
 858
 859         /* UBO and VBO are 22-bit */
 860         if (u_offset/8 > 0x3fffff)
 861                 puts("The value of U offset exceeds IPU limitation\n");
 862         if (v_offset/8 > 0x3fffff)
 863                 puts("The value of V offset exceeds IPU limitation\n");
 864
 865         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 866         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
 867
 868         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 869 };
 870
 871 /*
 872  * This function is called to initialize a buffer for logical IPU channel.
 873  *
 874  * @param       channel         Input parameter for the logical channel ID.
 875  *
 876  * @param       type            Input parameter which buffer to initialize.
 877  *
 878  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 879  *                              Pixel format is a FOURCC ASCII code.
 880  *
 881  * @param       width           Input parameter for width of buffer in pixels.
 882  *
 883  * @param       height          Input parameter for height of buffer in pixels.
 884  *
 885  * @param       stride          Input parameter for stride length of buffer
 886  *                              in pixels.
 887  *
 888  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 889  *
 890  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 891  *                              Setting this to a value other than NULL enables
 892  *                              double buffering mode.
 893  *
 894  * @param       u               private u offset for additional cropping,
 895  *                              zero if not used.
 896  *
 897  * @param       v               private v offset for additional cropping,
 898  *                              zero if not used.
 899  *
 900  * @return      Returns 0 on success or negative error code on fail
 901  */
 902 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 903                                 uint32_t pixel_fmt,
 904                                 uint16_t width, uint16_t height,
 905                                 uint32_t stride,
 906                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 907                                 uint32_t u, uint32_t v)
 908 {
 909         uint32_t reg;
 910         uint32_t dma_chan;
 911
 912         dma_chan = channel_2_dma(channel, type);
 913         if (!idma_is_valid(dma_chan))
 914                 return -EINVAL;
 915
 916         if (stride < width * bytes_per_pixel(pixel_fmt))
 917                 stride = width * bytes_per_pixel(pixel_fmt);
 918
 919         if (stride % 4) {
 920                 printf("Stride %d not 32-bit aligned\n", stride);
 921                 return -EINVAL;
 922         }
 923         /* Build parameter memory data for DMA channel */
 924         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 925                            phyaddr_0, phyaddr_1);
 926
 927         if (ipu_is_dmfc_chan(dma_chan)) {
 928                 ipu_dmfc_set_wait4eot(dma_chan, width);
 929         }
 930
 931         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 932                 ipu_ch_param_set_high_priority(dma_chan);
 933
 934         ipu_ch_param_dump(dma_chan);
 935
 936         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 937         if (phyaddr_1)
 938                 reg |= idma_mask(dma_chan);
 939         else
 940                 reg &= ~idma_mask(dma_chan);
 941         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 942
 943         /* Reset to buffer 0 */
 944         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * This function enables a logical channel.
 951  *
 952  * @param       channel         Input parameter for the logical channel ID.
 953  *
 954  * @return      This function returns 0 on success or negative error code on
 955  *              fail.
 956  */
 957 int32_t ipu_enable_channel(ipu_channel_t channel)
 958 {
 959         uint32_t reg;
 960         uint32_t in_dma;
 961         uint32_t out_dma;
 962
 963         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
 964                 printf("Warning: channel already enabled %d\n",
 965                         IPU_CHAN_ID(channel));
 966         }
 967
 968         /* Get input and output dma channels */
 969         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 970         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 971
 972         if (idma_is_valid(in_dma)) {
 973                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
 974                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
 975         }
 976         if (idma_is_valid(out_dma)) {
 977                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
 978                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
 979         }
 980
 981         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
 982             (channel == MEM_FG_SYNC)) {
 983                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
 984                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
 985
 986                 ipu_dp_dc_enable(channel);
 987         }
 988
 989         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
 990
 991         return 0;
 992 }
 993
 994 /*
 995  * This function clear buffer ready for a logical channel.
 996  *
 997  * @param       channel         Input parameter for the logical channel ID.
 998  *
 999  * @param       type            Input parameter which buffer to clear.
1000  *
1001  * @param       bufNum          Input parameter for which buffer number clear
1002  *                              ready state.
1003  *
1004  */
1005 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1006                 uint32_t bufNum)
1007 {
1008         uint32_t dma_ch = channel_2_dma(channel, type);
1009
1010         if (!idma_is_valid(dma_ch))
1011                 return;
1012
1013         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1014         if (bufNum == 0) {
1015                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1016                         __raw_writel(idma_mask(dma_ch),
1017                                         IPU_CHA_BUF0_RDY(dma_ch));
1018                 }
1019         } else {
1020                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1021                         __raw_writel(idma_mask(dma_ch),
1022                                         IPU_CHA_BUF1_RDY(dma_ch));
1023                 }
1024         }
1025         __raw_writel(0x0, IPU_GPR); /* write one to set */
1026 }
1027
1028 /*
1029  * This function disables a logical channel.
1030  *
1031  * @param       channel         Input parameter for the logical channel ID.
1032  *
1033  * @param       wait_for_stop   Flag to set whether to wait for channel end
1034  *                              of frame or return immediately.
1035  *
1036  * @return      This function returns 0 on success or negative error code on
1037  *              fail.
1038  */
1039 int32_t ipu_disable_channel(ipu_channel_t channel)
1040 {
1041         uint32_t reg;
1042         uint32_t in_dma;
1043         uint32_t out_dma;
1044
1045         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1046                 debug("Channel already disabled %d\n",
1047                         IPU_CHAN_ID(channel));
1048                 return 0;
1049         }
1050
1051         /* Get input and output dma channels */
1052         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1053         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1054
1055         if ((idma_is_valid(in_dma) &&
1056                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1057                 && (idma_is_valid(out_dma) &&
1058                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1059                 return -EINVAL;
1060
1061         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1062             (channel == MEM_DC_SYNC)) {
1063                 ipu_dp_dc_disable(channel, 0);
1064         }
1065
1066         /* Disable DMA channel(s) */
1067         if (idma_is_valid(in_dma)) {
1068                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1069                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1070                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1071         }
1072         if (idma_is_valid(out_dma)) {
1073                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1074                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1075                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1076         }
1077
1078         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1079
1080         /* Set channel buffers NOT to be ready */
1081         if (idma_is_valid(in_dma)) {
1082                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1083                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1084         }
1085         if (idma_is_valid(out_dma)) {
1086                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1087                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1088         }
1089
1090         return 0;
1091 }
1092
1093 uint32_t bytes_per_pixel(uint32_t fmt)
1094 {
1095         switch (fmt) {
1096         case IPU_PIX_FMT_GENERIC:       /* generic data */
1097         case IPU_PIX_FMT_RGB332:
1098         case IPU_PIX_FMT_YUV420P:
1099         case IPU_PIX_FMT_YUV422P:
1100                 return 1;
1101         case IPU_PIX_FMT_RGB565:
1102         case IPU_PIX_FMT_YUYV:
1103         case IPU_PIX_FMT_UYVY:
1104                 return 2;
1105         case IPU_PIX_FMT_BGR24:
1106         case IPU_PIX_FMT_RGB24:
1107                 return 3;
1108         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
1109         case IPU_PIX_FMT_BGR32:
1110         case IPU_PIX_FMT_BGRA32:
1111         case IPU_PIX_FMT_RGB32:
1112         case IPU_PIX_FMT_RGBA32:
1113         case IPU_PIX_FMT_ABGR32:
1114                 return 4;
1115         default:
1116                 return 1;
1117         }
1118         return 0;
1119 }
1120
1121 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1122 {
1123         switch (fmt) {
1124         case IPU_PIX_FMT_RGB666:
1125         case IPU_PIX_FMT_RGB565:
1126         case IPU_PIX_FMT_BGR24:
1127         case IPU_PIX_FMT_RGB24:
1128         case IPU_PIX_FMT_BGR32:
1129         case IPU_PIX_FMT_BGRA32:
1130         case IPU_PIX_FMT_RGB32:
1131         case IPU_PIX_FMT_RGBA32:
1132         case IPU_PIX_FMT_ABGR32:
1133         case IPU_PIX_FMT_LVDS666:
1134         case IPU_PIX_FMT_LVDS888:
1135                 return RGB;
1136
1137         default:
1138                 return YCbCr;
1139         }
1140         return RGB;
1141 }