drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* #define DEBUG */
  31 #include <common.h>
  32 #include <ipu.h>
  33 #include <linux/types.h>
  34 #include <linux/err.h>
  35 #include <asm/io.h>
  36 #include <asm/errno.h>
  37 #include <asm/arch/imx-regs.h>
  38 #include <asm/arch/crm_regs.h>
  39 #include <asm/arch/clock.h>
  40
  41 #include "ipu_regs.h"
  42
  43 struct ipu_ch_param_word {
  44         uint32_t data[5];
  45         uint32_t res[3];
  46 };
  47
  48 struct ipu_ch_param {
  49         struct ipu_ch_param_word word[2];
  50 };
  51
  52 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  53
  54 #define _param_word(base, w) \
  55         (((struct ipu_ch_param *)(base))->word[w].data)
  56
  57 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
  58         int i = (bit) / 32;                                             \
  59         int off = (bit) % 32;                                           \
  60         _param_word(base, w)[i] |= (v) << off;                          \
  61         if (((bit) + (size) - 1) / 32 > i) {                            \
  62                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  63         }                                                               \
  64 }
  65
  66 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
  67         int i = (bit) / 32;                                     \
  68         int off = (bit) % 32;                                   \
  69         u32 mask = (1UL << size) - 1;                           \
  70         u32 temp = _param_word(base, w)[i];                     \
  71         temp &= ~(mask << off);                                 \
  72         _param_word(base, w)[i] = temp | (v) << off;            \
  73         if (((bit) + (size) - 1) / 32 > i) {                    \
  74                 temp = _param_word(base, w)[i + 1];             \
  75                 temp &= ~(mask >> (32 - off));                  \
  76                 _param_word(base, w)[i + 1] =                   \
  77                         temp | ((v) >> (off ? (32 - off) : 0)); \
  78         }                                                       \
  79 }
  80
  81 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
  82         u32 temp2;                                              \
  83         int i = (bit) / 32;                                     \
  84         int off = (bit) % 32;                                   \
  85         u32 mask = (1UL << size) - 1;                           \
  86         u32 temp1 = _param_word(base, w)[i];                    \
  87         temp1 = mask & (temp1 >> off);                          \
  88         if (((bit)+(size) - 1) / 32 > i) {                      \
  89                 temp2 = _param_word(base, w)[i + 1];            \
  90                 temp2 &= mask >> (off ? (32 - off) : 0);        \
  91                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
  92         }                                                       \
  93         temp1;                                                  \
  94 })
  95
  96 int clk_get_usecount(struct clk *clk)
  97 {
  98         if (clk == NULL)
  99                 return 0;
 100
 101         return clk->usecount;
 102 }
 103
 104 u32 clk_get_rate(struct clk *clk)
 105 {
 106         if (!clk)
 107                 return 0;
 108
 109         return clk->rate;
 110 }
 111
 112 struct clk *clk_get_parent(struct clk *clk)
 113 {
 114         if (!clk)
 115                 return 0;
 116
 117         return clk->parent;
 118 }
 119
 120 int clk_set_rate(struct clk *clk, unsigned long rate)
 121 {
 122         if (clk && clk->set_rate)
 123                 clk->set_rate(clk, rate);
 124         return clk->rate;
 125 }
 126
 127 long clk_round_rate(struct clk *clk, unsigned long rate)
 128 {
 129         if (clk == NULL || !clk->round_rate)
 130                 return 0;
 131
 132         return clk->round_rate(clk, rate);
 133 }
 134
 135 int clk_set_parent(struct clk *clk, struct clk *parent)
 136 {
 137         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 138                 clk ? clk->parent : NULL);
 139
 140         if (!clk || clk == parent)
 141                 return 0;
 142
 143         if (clk->set_parent) {
 144                 int ret;
 145
 146                 ret = clk->set_parent(clk, parent);
 147                 if (ret)
 148                         return ret;
 149         }
 150         clk->parent = parent;
 151         return 0;
 152 }
 153
 154 static int clk_ipu_enable(struct clk *clk)
 155 {
 156         ipu_clk_enable();
 157         return 0;
 158 }
 159
 160 static void clk_ipu_disable(struct clk *clk)
 161 {
 162         ipu_clk_disable();
 163 }
 164
 165 static struct clk ipu_clk = {
 166         .name = "ipu_clk",
 167 #if defined(CONFIG_IPU_CLKRATE)
 168         .rate = CONFIG_IPU_CLKRATE,
 169 #endif
 170         .enable = clk_ipu_enable,
 171         .disable = clk_ipu_disable,
 172 };
 173
 174 /* Globals */
 175 struct clk *g_ipu_clk;
 176 struct clk *g_di_clk[2];
 177 struct clk *g_pixel_clk[2];
 178 unsigned char g_dc_di_assignment[10];
 179 int g_ipu_clk_enabled;
 180 u32 *ipu_dc_tmpl_reg;
 181
 182 static uint32_t g_channel_init_mask;
 183 static uint32_t g_channel_enable_mask;
 184 static int ipu_dc_use_count;
 185 static int ipu_dp_use_count;
 186 static int ipu_dmfc_use_count;
 187 static int ipu_di_use_count[2];
 188
 189 static u32 *ipu_cpmem_base;
 190
 191 /* Static functions */
 192
 193 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 194 {
 195         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 196 };
 197
 198 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 199 {
 200         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 201 };
 202
 203 /* Either DP BG or DP FG can be graphic window */
 204 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 205 {
 206         return (dma_chan == 23 || dma_chan == 27);
 207 }
 208
 209 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 210 {
 211         return ((dma_chan >= 23) && (dma_chan <= 29));
 212 }
 213
 214
 215 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 216                                             dma_addr_t phyaddr)
 217 {
 218         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 219                                phyaddr / 8);
 220 };
 221
 222 #define idma_is_valid(ch)       (ch != NO_DMA)
 223 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 224 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 225
 226 static void ipu_pixel_clk_recalc(struct clk *clk)
 227 {
 228         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 229         if (div == 0)
 230                 clk->rate = 0;
 231         else
 232                 clk->rate = (clk->parent->rate * 16) / div;
 233 }
 234
 235 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 236         unsigned long rate)
 237 {
 238         u32 div, div1;
 239         u64 tmp;
 240         /*
 241          * Calculate divider
 242          * Fractional part is 4 bits,
 243          * so simply multiply by 2^4 to get fractional part.
 244          */
 245         tmp = (u64)clk->parent->rate * 16;
 246         div = tmp / rate;
 247
 248         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 249                 div = 0x10;
 250         if (div & ~0xFEF)
 251                 div &= 0xFF8;
 252         else {
 253                 div1 = div & 0xFE0;
 254                 if ((tmp/div1 - tmp/div) < rate / 4)
 255                         div = div1;
 256                 else
 257                         div &= 0xFF8;
 258         }
 259         tmp /= div;
 260 #if 1
 261         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
 262                 rate / 1000000, rate / 1000 % 1000,
 263                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 264                 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
 265 #endif
 266         return tmp;
 267 }
 268
 269 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 270 {
 271         u32 div = ((u64)clk->parent->rate * 16) / rate;
 272
 273         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
 274                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 275                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
 276
 277         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 278
 279         /* Setup pixel clock timing */
 280         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 281
 282         clk->rate = ((u64)clk->parent->rate * 16) / div;
 283         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
 284                 clk->rate / 1000000, clk->rate / 1000 % 1000);
 285         return 0;
 286 }
 287
 288 static int ipu_pixel_clk_enable(struct clk *clk)
 289 {
 290         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 291         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 292         __raw_writel(disp_gen, IPU_DISP_GEN);
 293
 294         return 0;
 295 }
 296
 297 static void ipu_pixel_clk_disable(struct clk *clk)
 298 {
 299         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 300         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 301         __raw_writel(disp_gen, IPU_DISP_GEN);
 302 }
 303
 304 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 305 {
 306         int ret;
 307         u32 di_gen;
 308
 309         ret = clk_enable(clk);
 310         if (ret)
 311                 return ret;
 312
 313         di_gen = __raw_readl(DI_GENERAL(clk->id));
 314
 315         if (parent == g_ipu_clk)
 316                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 317         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
 318                 di_gen |= DI_GEN_DI_CLK_EXT;
 319         else
 320                 goto err;
 321
 322         ret = clk_enable(parent);
 323         if (ret)
 324                 goto err;
 325         __raw_writel(di_gen, DI_GENERAL(clk->id));
 326         ipu_pixel_clk_recalc(clk);
 327         clk->disable(clk->parent);
 328         clk->parent = parent;
 329 err:
 330         clk_disable(clk);
 331         return ret;
 332 }
 333
 334 static struct clk pixel_clk[] = {
 335         {
 336                 .name = "pixel_clk",
 337                 .id = 0,
 338                 .recalc = ipu_pixel_clk_recalc,
 339                 .set_rate = ipu_pixel_clk_set_rate,
 340                 .round_rate = ipu_pixel_clk_round_rate,
 341                 .set_parent = ipu_pixel_clk_set_parent,
 342                 .enable = ipu_pixel_clk_enable,
 343                 .disable = ipu_pixel_clk_disable,
 344         },
 345         {
 346                 .name = "pixel_clk",
 347                 .id = 1,
 348                 .recalc = ipu_pixel_clk_recalc,
 349                 .set_rate = ipu_pixel_clk_set_rate,
 350                 .round_rate = ipu_pixel_clk_round_rate,
 351                 .set_parent = ipu_pixel_clk_set_parent,
 352                 .enable = ipu_pixel_clk_enable,
 353                 .disable = ipu_pixel_clk_disable,
 354         },
 355 };
 356
 357 static struct clk di_clk[] = {
 358         {
 359                 .name = "ipu_di_clk",
 360                 .id = 0,
 361         },
 362         {
 363                 .name = "ipu_di_clk",
 364                 .id = 1,
 365         },
 366 };
 367
 368 /*
 369  * This function resets IPU
 370  */
 371 void ipu_reset(void)
 372 {
 373         u32 *reg;
 374         u32 value;
 375
 376         reg = (u32 *)SRC_BASE_ADDR;
 377         value = __raw_readl(reg);
 378         value = value | SW_IPU_RST;
 379         __raw_writel(value, reg);
 380 }
 381
 382 /*
 383  * This function is called by the driver framework to initialize the IPU
 384  * hardware.
 385  *
 386  * @param       dev     The device structure for the IPU passed in by the
 387  *                      driver framework.
 388  *
 389  * @return      Returns 0 on success or negative error code on error
 390  */
 391 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
 392 {
 393         int ret;
 394         void *ipu_base;
 395         unsigned long start;
 396
 397 #if defined(CONFIG_MXC_HSC)
 398         u32 temp;
 399         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 400         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 401
 402          __raw_writel(0xF00, reg_hsc_mcd);
 403
 404         /* CSI mode reserved */
 405         temp = __raw_readl(reg_hsc_mxt_conf);
 406          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 407
 408         temp = __raw_readl(reg_hsc_mxt_conf);
 409         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 410 #endif
 411         ipu_base = (void *)IPU_CTRL_BASE_ADDR;
 412         /* base fixup */
 413         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
 414                 ipu_base += IPUV3H_REG_BASE;
 415         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
 416                 ipu_base += IPUV3M_REG_BASE;
 417         else                    /* IPUv3D, v3E, v3EX */
 418                 ipu_base += IPUV3DEX_REG_BASE;
 419         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
 420         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
 421
 422         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
 423
 424         g_pixel_clk[0] = &pixel_clk[0];
 425         g_pixel_clk[1] = &pixel_clk[1];
 426
 427         g_di_clk[0] = &di_clk[0];
 428         g_di_clk[1] = &di_clk[1];
 429         g_di_clk[di]->rate = di_clk_val;
 430
 431         g_ipu_clk = &ipu_clk;
 432         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 433
 434         ret = clk_enable(g_ipu_clk);
 435         if (ret)
 436                 return ret;
 437         ipu_reset();
 438
 439         if (di_clk_parent == DI_PCLK_LDB) {
 440                 clk_set_parent(g_pixel_clk[di], g_di_clk[di]);
 441         } else {
 442                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 443                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 444         }
 445
 446         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 447         start = get_timer_masked();
 448         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
 449                 if (get_timer(start) > CONFIG_SYS_HZ)
 450                         return -ETIME;
 451         }
 452
 453         ipu_init_dc_mappings();
 454
 455         __raw_writel(0, IPU_INT_CTRL(5));
 456         __raw_writel(0, IPU_INT_CTRL(6));
 457         __raw_writel(0, IPU_INT_CTRL(9));
 458         __raw_writel(0, IPU_INT_CTRL(10));
 459
 460         /* DMFC Init */
 461         ipu_dmfc_init(DMFC_NORMAL, 1);
 462
 463         /* Set sync refresh channels as high priority */
 464         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 465
 466         /* Set MCU_T to divide MCU access window into 2 */
 467         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 468
 469         clk_disable(g_ipu_clk);
 470
 471         return 0;
 472 }
 473
 474 void ipu_dump_registers(void)
 475 {
 476         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
 477         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
 478         debug("IDMAC_CHA_EN1        0x%08X\n",
 479                __raw_readl(IDMAC_CHA_EN(0)));
 480         debug("IDMAC_CHA_EN2        0x%08X\n",
 481                __raw_readl(IDMAC_CHA_EN(32)));
 482         debug("IDMAC_CHA_PRI1       0x%08X\n",
 483                __raw_readl(IDMAC_CHA_PRI(0)));
 484         debug("IDMAC_CHA_PRI2       0x%08X\n",
 485                __raw_readl(IDMAC_CHA_PRI(32)));
 486         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
 487                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 488         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
 489                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 490         debug("DMFC_WR_CHAN         0x%08X\n",
 491                __raw_readl(DMFC_WR_CHAN));
 492         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
 493                __raw_readl(DMFC_WR_CHAN_DEF));
 494         debug("DMFC_DP_CHAN         0x%08X\n",
 495                __raw_readl(DMFC_DP_CHAN));
 496         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
 497                __raw_readl(DMFC_DP_CHAN_DEF));
 498         debug("DMFC_IC_CTRL         0x%08X\n",
 499                __raw_readl(DMFC_IC_CTRL));
 500         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
 501                __raw_readl(IPU_FS_PROC_FLOW1));
 502         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
 503                __raw_readl(IPU_FS_PROC_FLOW2));
 504         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
 505                __raw_readl(IPU_FS_PROC_FLOW3));
 506         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
 507                __raw_readl(IPU_FS_DISP_FLOW1));
 508 }
 509
 510 /*
 511  * This function is called to initialize a logical IPU channel.
 512  *
 513  * @param       channel Input parameter for the logical channel ID to init.
 514  *
 515  * @param       params  Input parameter containing union of channel
 516  *                      initialization parameters.
 517  *
 518  * @return      Returns 0 on success or negative error code on fail
 519  */
 520 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 521 {
 522         int ret = 0;
 523         uint32_t ipu_conf;
 524
 525         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 526
 527         if (g_ipu_clk_enabled == 0) {
 528                 g_ipu_clk_enabled = 1;
 529                 clk_enable(g_ipu_clk);
 530         }
 531
 532
 533         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 534                 printf("Warning: channel already initialized %d\n",
 535                         IPU_CHAN_ID(channel));
 536         }
 537
 538         ipu_conf = __raw_readl(IPU_CONF);
 539
 540         switch (channel) {
 541         case MEM_DC_SYNC:
 542                 if (params->mem_dc_sync.di > 1) {
 543                         ret = -EINVAL;
 544                         goto err;
 545                 }
 546
 547                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 548                 ipu_dc_init(1, params->mem_dc_sync.di,
 549                              params->mem_dc_sync.interlaced);
 550                 ipu_di_use_count[params->mem_dc_sync.di]++;
 551                 ipu_dc_use_count++;
 552                 ipu_dmfc_use_count++;
 553                 break;
 554         case MEM_BG_SYNC:
 555                 if (params->mem_dp_bg_sync.di > 1) {
 556                         ret = -EINVAL;
 557                         goto err;
 558                 }
 559
 560                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 561                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 562                              params->mem_dp_bg_sync.out_pixel_fmt);
 563                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 564                              params->mem_dp_bg_sync.interlaced);
 565                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 566                 ipu_dc_use_count++;
 567                 ipu_dp_use_count++;
 568                 ipu_dmfc_use_count++;
 569                 break;
 570         case MEM_FG_SYNC:
 571                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 572                              params->mem_dp_fg_sync.out_pixel_fmt);
 573
 574                 ipu_dc_use_count++;
 575                 ipu_dp_use_count++;
 576                 ipu_dmfc_use_count++;
 577                 break;
 578         default:
 579                 printf("Missing channel initialization\n");
 580         }
 581
 582         /* Enable IPU sub module */
 583         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 584         if (ipu_dc_use_count == 1)
 585                 ipu_conf |= IPU_CONF_DC_EN;
 586         if (ipu_dp_use_count == 1)
 587                 ipu_conf |= IPU_CONF_DP_EN;
 588         if (ipu_dmfc_use_count == 1)
 589                 ipu_conf |= IPU_CONF_DMFC_EN;
 590         if (ipu_di_use_count[0] == 1) {
 591                 ipu_conf |= IPU_CONF_DI0_EN;
 592         }
 593         if (ipu_di_use_count[1] == 1) {
 594                 ipu_conf |= IPU_CONF_DI1_EN;
 595         }
 596
 597         __raw_writel(ipu_conf, IPU_CONF);
 598
 599 err:
 600         return ret;
 601 }
 602
 603 /*
 604  * This function is called to uninitialize a logical IPU channel.
 605  *
 606  * @param       channel Input parameter for the logical channel ID to uninit.
 607  */
 608 void ipu_uninit_channel(ipu_channel_t channel)
 609 {
 610         uint32_t reg;
 611         uint32_t in_dma, out_dma = 0;
 612         uint32_t ipu_conf;
 613
 614         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 615                 debug("Channel already uninitialized %d\n",
 616                         IPU_CHAN_ID(channel));
 617                 return;
 618         }
 619
 620         /*
 621          * Make sure channel is disabled
 622          * Get input and output dma channels
 623          */
 624         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 625         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 626
 627         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 628             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 629                 printf("Channel %d is not disabled, disable first\n",
 630                         IPU_CHAN_ID(channel));
 631                 return;
 632         }
 633
 634         ipu_conf = __raw_readl(IPU_CONF);
 635
 636         /* Reset the double buffer */
 637         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 638         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 639         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 640         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 641
 642         switch (channel) {
 643         case MEM_DC_SYNC:
 644                 ipu_dc_uninit(1);
 645                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 646                 ipu_dc_use_count--;
 647                 ipu_dmfc_use_count--;
 648                 break;
 649         case MEM_BG_SYNC:
 650                 ipu_dp_uninit(channel);
 651                 ipu_dc_uninit(5);
 652                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 653                 ipu_dc_use_count--;
 654                 ipu_dp_use_count--;
 655                 ipu_dmfc_use_count--;
 656                 break;
 657         case MEM_FG_SYNC:
 658                 ipu_dp_uninit(channel);
 659                 ipu_dc_use_count--;
 660                 ipu_dp_use_count--;
 661                 ipu_dmfc_use_count--;
 662                 break;
 663         default:
 664                 break;
 665         }
 666
 667         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 668
 669         if (ipu_dc_use_count == 0)
 670                 ipu_conf &= ~IPU_CONF_DC_EN;
 671         if (ipu_dp_use_count == 0)
 672                 ipu_conf &= ~IPU_CONF_DP_EN;
 673         if (ipu_dmfc_use_count == 0)
 674                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 675         if (ipu_di_use_count[0] == 0) {
 676                 ipu_conf &= ~IPU_CONF_DI0_EN;
 677         }
 678         if (ipu_di_use_count[1] == 0) {
 679                 ipu_conf &= ~IPU_CONF_DI1_EN;
 680         }
 681
 682         __raw_writel(ipu_conf, IPU_CONF);
 683
 684         if (ipu_conf == 0) {
 685                 clk_disable(g_ipu_clk);
 686                 g_ipu_clk_enabled = 0;
 687         }
 688
 689 }
 690
 691 static inline void ipu_ch_param_dump(int ch)
 692 {
 693 #ifdef DEBUG
 694         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 695         printf("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 696                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 697                  p->word[0].data[3], p->word[0].data[4]);
 698         printf("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 699                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 700                  p->word[1].data[3], p->word[1].data[4]);
 701         printf("PFS 0x%x, ",
 702                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 703         printf("BPP 0x%x, ",
 704                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 705         printf("NPB 0x%x\n",
 706                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 707
 708         printf("FW %d, ",
 709                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 710         printf("FH %d, ",
 711                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 712         printf("Stride %d\n",
 713                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 714
 715         printf("Width0 %d+1, ",
 716                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 717         printf("Width1 %d+1, ",
 718                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 719         printf("Width2 %d+1, ",
 720                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 721         printf("Width3 %d+1, ",
 722                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 723         printf("Offset0 %d, ",
 724                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 725         printf("Offset1 %d, ",
 726                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 727         printf("Offset2 %d, ",
 728                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 729         printf("Offset3 %d\n",
 730                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 731 #endif
 732 }
 733
 734 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 735                                               int red_width, int red_offset,
 736                                               int green_width, int green_offset,
 737                                               int blue_width, int blue_offset,
 738                                               int alpha_width, int alpha_offset)
 739 {
 740         /* Setup red width and offset */
 741         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 742         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 743         /* Setup green width and offset */
 744         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 745         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 746         /* Setup blue width and offset */
 747         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 748         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 749         /* Setup alpha width and offset */
 750         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 751         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 752 }
 753
 754 static void ipu_ch_param_init(int ch,
 755                               uint32_t pixel_fmt, uint32_t width,
 756                               uint32_t height, uint32_t stride,
 757                               uint32_t u, uint32_t v,
 758                               uint32_t uv_stride, dma_addr_t addr0,
 759                               dma_addr_t addr1)
 760 {
 761         uint32_t u_offset = 0;
 762         uint32_t v_offset = 0;
 763
 764         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
 765
 766         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 767                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
 768                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
 769         } else {
 770                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
 771                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
 772         }
 773
 774         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
 775         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
 776
 777         switch (pixel_fmt) {
 778         case IPU_PIX_FMT_GENERIC:
 779                 /*Represents 8-bit Generic data */
 780                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
 781                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
 782                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
 783
 784                 break;
 785         case IPU_PIX_FMT_GENERIC_32:
 786                 /*Represents 32-bit Generic data */
 787                 break;
 788         case IPU_PIX_FMT_RGB565:
 789                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 790                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 791                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 792
 793                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
 794                 break;
 795         case IPU_PIX_FMT_BGR24:
 796                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 797                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 798                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 799
 800                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 801                 break;
 802         case IPU_PIX_FMT_RGB24:
 803         case IPU_PIX_FMT_YUV444:
 804                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 805                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 806                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 807
 808                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
 809                 break;
 810         case IPU_PIX_FMT_BGRA32:
 811         case IPU_PIX_FMT_BGR32:
 812                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 813                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 814                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 815
 816                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
 817                 break;
 818         case IPU_PIX_FMT_RGBA32:
 819         case IPU_PIX_FMT_RGB32:
 820                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 821                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 822                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 823
 824                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
 825                 break;
 826         case IPU_PIX_FMT_ABGR32:
 827                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 828                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 829
 830                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 831                 break;
 832         case IPU_PIX_FMT_UYVY:
 833                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 834                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
 835                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 836                 break;
 837         case IPU_PIX_FMT_YUYV:
 838                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 839                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
 840                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 841                 break;
 842         case IPU_PIX_FMT_YUV420P2:
 843         case IPU_PIX_FMT_YUV420P:
 844                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
 845
 846                 if (uv_stride < stride / 2)
 847                         uv_stride = stride / 2;
 848
 849                 u_offset = stride * height;
 850                 v_offset = u_offset + (uv_stride * height / 2);
 851                 /* burst size */
 852                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 853                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
 854                         uv_stride = uv_stride*2;
 855                 } else {
 856                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
 857                 }
 858                 break;
 859         case IPU_PIX_FMT_YVU422P:
 860                 /* BPP & pixel format */
 861                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 862                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 863
 864                 if (uv_stride < stride / 2)
 865                         uv_stride = stride / 2;
 866
 867                 v_offset = (v == 0) ? stride * height : v;
 868                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 869                 break;
 870         case IPU_PIX_FMT_YUV422P:
 871                 /* BPP & pixel format */
 872                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 873                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 874
 875                 if (uv_stride < stride / 2)
 876                         uv_stride = stride / 2;
 877
 878                 u_offset = (u == 0) ? stride * height : u;
 879                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 880                 break;
 881         case IPU_PIX_FMT_NV12:
 882                 /* BPP & pixel format */
 883                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
 884                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 885                 uv_stride = stride;
 886                 u_offset = (u == 0) ? stride * height : u;
 887                 break;
 888         default:
 889                 printf("mxc ipu: unimplemented pixel format: %08x\n",
 890                         pixel_fmt);
 891         }
 892
 893
 894         if (uv_stride)
 895                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
 896
 897         /* Get the uv offset from user when need cropping */
 898         if (u || v) {
 899                 u_offset = u;
 900                 v_offset = v;
 901         }
 902
 903         /* UBO and VBO are 22-bit */
 904         if (u_offset/8 > 0x3fffff)
 905                 puts("The value of U offset exceeds IPU limitation\n");
 906         if (v_offset/8 > 0x3fffff)
 907                 puts("The value of V offset exceeds IPU limitation\n");
 908
 909         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 910         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
 911
 912         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 913 };
 914
 915 /*
 916  * This function is called to initialize a buffer for logical IPU channel.
 917  *
 918  * @param       channel         Input parameter for the logical channel ID.
 919  *
 920  * @param       type            Input parameter which buffer to initialize.
 921  *
 922  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 923  *                              Pixel format is a FOURCC ASCII code.
 924  *
 925  * @param       width           Input parameter for width of buffer in pixels.
 926  *
 927  * @param       height          Input parameter for height of buffer in pixels.
 928  *
 929  * @param       stride          Input parameter for stride length of buffer
 930  *                              in pixels.
 931  *
 932  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 933  *
 934  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 935  *                              Setting this to a value other than NULL enables
 936  *                              double buffering mode.
 937  *
 938  * @param       u               private u offset for additional cropping,
 939  *                              zero if not used.
 940  *
 941  * @param       v               private v offset for additional cropping,
 942  *                              zero if not used.
 943  *
 944  * @return      Returns 0 on success or negative error code on fail
 945  */
 946 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 947                                 uint32_t pixel_fmt,
 948                                 uint16_t width, uint16_t height,
 949                                 uint32_t stride,
 950                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 951                                 uint32_t u, uint32_t v)
 952 {
 953         uint32_t reg;
 954         uint32_t dma_chan;
 955
 956         dma_chan = channel_2_dma(channel, type);
 957         if (!idma_is_valid(dma_chan))
 958                 return -EINVAL;
 959
 960         if (stride < width * bytes_per_pixel(pixel_fmt))
 961                 stride = width * bytes_per_pixel(pixel_fmt);
 962
 963         if (stride % 4) {
 964                 printf("Stride %d not 32-bit aligned\n", stride);
 965                 return -EINVAL;
 966         }
 967         /* Build parameter memory data for DMA channel */
 968         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 969                            phyaddr_0, phyaddr_1);
 970
 971         if (ipu_is_dmfc_chan(dma_chan)) {
 972                 ipu_dmfc_set_wait4eot(dma_chan, width);
 973         }
 974
 975         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 976                 ipu_ch_param_set_high_priority(dma_chan);
 977
 978         ipu_ch_param_dump(dma_chan);
 979
 980         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 981         if (phyaddr_1)
 982                 reg |= idma_mask(dma_chan);
 983         else
 984                 reg &= ~idma_mask(dma_chan);
 985         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 986
 987         /* Reset to buffer 0 */
 988         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 989
 990         return 0;
 991 }
 992
 993 /*
 994  * This function enables a logical channel.
 995  *
 996  * @param       channel         Input parameter for the logical channel ID.
 997  *
 998  * @return      This function returns 0 on success or negative error code on
 999  *              fail.
1000  */
1001 int32_t ipu_enable_channel(ipu_channel_t channel)
1002 {
1003         uint32_t reg;
1004         uint32_t in_dma;
1005         uint32_t out_dma;
1006
1007         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1008                 printf("Warning: channel already enabled %d\n",
1009                         IPU_CHAN_ID(channel));
1010         }
1011
1012         /* Get input and output dma channels */
1013         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1014         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1015
1016         if (idma_is_valid(in_dma)) {
1017                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1018                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1019         }
1020         if (idma_is_valid(out_dma)) {
1021                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1022                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1023         }
1024
1025         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1026             (channel == MEM_FG_SYNC)) {
1027                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1028                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1029
1030                 ipu_dp_dc_enable(channel);
1031         }
1032
1033         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1034
1035         return 0;
1036 }
1037
1038 /*
1039  * This function clear buffer ready for a logical channel.
1040  *
1041  * @param       channel         Input parameter for the logical channel ID.
1042  *
1043  * @param       type            Input parameter which buffer to clear.
1044  *
1045  * @param       bufNum          Input parameter for which buffer number clear
1046  *                              ready state.
1047  *
1048  */
1049 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1050                 uint32_t bufNum)
1051 {
1052         uint32_t dma_ch = channel_2_dma(channel, type);
1053
1054         if (!idma_is_valid(dma_ch))
1055                 return;
1056
1057         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1058         if (bufNum == 0) {
1059                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1060                         __raw_writel(idma_mask(dma_ch),
1061                                         IPU_CHA_BUF0_RDY(dma_ch));
1062                 }
1063         } else {
1064                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1065                         __raw_writel(idma_mask(dma_ch),
1066                                         IPU_CHA_BUF1_RDY(dma_ch));
1067                 }
1068         }
1069         __raw_writel(0x0, IPU_GPR); /* write one to set */
1070 }
1071
1072 /*
1073  * This function disables a logical channel.
1074  *
1075  * @param       channel         Input parameter for the logical channel ID.
1076  *
1077  * @param       wait_for_stop   Flag to set whether to wait for channel end
1078  *                              of frame or return immediately.
1079  *
1080  * @return      This function returns 0 on success or negative error code on
1081  *              fail.
1082  */
1083 int32_t ipu_disable_channel(ipu_channel_t channel)
1084 {
1085         uint32_t reg;
1086         uint32_t in_dma;
1087         uint32_t out_dma;
1088
1089         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1090                 debug("Channel already disabled %d\n",
1091                         IPU_CHAN_ID(channel));
1092                 return 0;
1093         }
1094
1095         /* Get input and output dma channels */
1096         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1097         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1098
1099         if ((idma_is_valid(in_dma) &&
1100                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1101                 && (idma_is_valid(out_dma) &&
1102                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1103                 return -EINVAL;
1104
1105         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1106             (channel == MEM_DC_SYNC)) {
1107                 ipu_dp_dc_disable(channel, 0);
1108         }
1109
1110         /* Disable DMA channel(s) */
1111         if (idma_is_valid(in_dma)) {
1112                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1113                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1114                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1115         }
1116         if (idma_is_valid(out_dma)) {
1117                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1118                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1119                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1120         }
1121
1122         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1123
1124         /* Set channel buffers NOT to be ready */
1125         if (idma_is_valid(in_dma)) {
1126                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1127                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1128         }
1129         if (idma_is_valid(out_dma)) {
1130                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1131                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1132         }
1133
1134         return 0;
1135 }
1136
1137 uint32_t bytes_per_pixel(uint32_t fmt)
1138 {
1139         switch (fmt) {
1140         case IPU_PIX_FMT_GENERIC:       /*generic data */
1141         case IPU_PIX_FMT_RGB332:
1142         case IPU_PIX_FMT_YUV420P:
1143         case IPU_PIX_FMT_YUV422P:
1144                 return 1;
1145         case IPU_PIX_FMT_RGB565:
1146         case IPU_PIX_FMT_YUYV:
1147         case IPU_PIX_FMT_UYVY:
1148                 return 2;
1149         case IPU_PIX_FMT_BGR24:
1150         case IPU_PIX_FMT_RGB24:
1151                 return 3;
1152         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
1153         case IPU_PIX_FMT_BGR32:
1154         case IPU_PIX_FMT_BGRA32:
1155         case IPU_PIX_FMT_RGB32:
1156         case IPU_PIX_FMT_RGBA32:
1157         case IPU_PIX_FMT_ABGR32:
1158                 return 4;
1159         default:
1160                 return 1;
1161         }
1162         return 0;
1163 }
1164
1165 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1166 {
1167         switch (fmt) {
1168         case IPU_PIX_FMT_RGB666:
1169         case IPU_PIX_FMT_RGB565:
1170         case IPU_PIX_FMT_BGR24:
1171         case IPU_PIX_FMT_RGB24:
1172         case IPU_PIX_FMT_BGR32:
1173         case IPU_PIX_FMT_BGRA32:
1174         case IPU_PIX_FMT_RGB32:
1175         case IPU_PIX_FMT_RGBA32:
1176         case IPU_PIX_FMT_ABGR32:
1177         case IPU_PIX_FMT_LVDS666:
1178         case IPU_PIX_FMT_LVDS888:
1179                 return RGB;
1180
1181         default:
1182                 return YCbCr;
1183         }
1184         return RGB;
1185 }