ecfec7755a7f8aac5301fe6488ff7da8e9e7994d
[karo-tx-uboot.git] / drivers / video / ipu_common.c
1 /*
2  * Porting to u-boot:
3  *
4  * (C) Copyright 2010
5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
6  *
7  * Linux IPU driver
8  *
9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 /* #define DEBUG */
15 #include <common.h>
16 #include <div64.h>
17 #include <ipu.h>
18 #include <linux/types.h>
19 #include <linux/err.h>
20 #include <asm/io.h>
21 #include <asm/errno.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/arch/clock.h>
25
26 #include "ipu_regs.h"
27
28 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
29
30 struct ipu_ch_param_word {
31         uint32_t data[5];
32         uint32_t res[3];
33 };
34
35 struct ipu_ch_param {
36         struct ipu_ch_param_word word[2];
37 };
38
39 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
40
41 #define _param_word(base, w) \
42         (((struct ipu_ch_param *)(base))->word[w].data)
43
44 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
45         int i = (bit) / 32;                                             \
46         int off = (bit) % 32;                                           \
47         _param_word(base, w)[i] |= (v) << off;                          \
48         if (((bit) + (size) - 1) / 32 > i) {                            \
49                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
50         }                                                               \
51 }
52
53 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
54         int i = (bit) / 32;                                     \
55         int off = (bit) % 32;                                   \
56         u32 mask = (1UL << size) - 1;                           \
57         u32 temp = _param_word(base, w)[i];                     \
58         temp &= ~(mask << off);                                 \
59         _param_word(base, w)[i] = temp | (v) << off;            \
60         if (((bit) + (size) - 1) / 32 > i) {                    \
61                 temp = _param_word(base, w)[i + 1];             \
62                 temp &= ~(mask >> (32 - off));                  \
63                 _param_word(base, w)[i + 1] =                   \
64                         temp | ((v) >> (off ? (32 - off) : 0)); \
65         }                                                       \
66 }
67
68 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
69         u32 temp2;                                              \
70         int i = (bit) / 32;                                     \
71         int off = (bit) % 32;                                   \
72         u32 mask = (1UL << size) - 1;                           \
73         u32 temp1 = _param_word(base, w)[i];                    \
74         temp1 = mask & (temp1 >> off);                          \
75         if (((bit)+(size) - 1) / 32 > i) {                      \
76                 temp2 = _param_word(base, w)[i + 1];            \
77                 temp2 &= mask >> (off ? (32 - off) : 0);        \
78                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
79         }                                                       \
80         temp1;                                                  \
81 })
82
83 #define IPU_SW_RST_TOUT_USEC    10000
84
85 static int clk_ipu_enable(struct clk *clk)
86 {
87         ipu_clk_enable();
88         return 0;
89 }
90
91 static void clk_ipu_disable(struct clk *clk)
92 {
93         ipu_clk_disable();
94 }
95
96 static struct clk ipu_clk = {
97         .name = "ipu_clk",
98         .rate = CONFIG_IPUV3_CLK,
99         .enable = clk_ipu_enable,
100         .disable = clk_ipu_disable,
101 };
102
103 static int clk_ldb_enable(struct clk *clk)
104 {
105         ldb_clk_enable(0);
106         ldb_clk_enable(1);
107         return 0;
108 }
109
110 static void clk_ldb_disable(struct clk *clk)
111 {
112         ldb_clk_disable(0);
113         ldb_clk_disable(1);
114 }
115
116 #if !defined CONFIG_SYS_LDB_CLOCK
117 #define CONFIG_SYS_LDB_CLOCK 65000000
118 #endif
119
120 static struct clk ldb_clk = {
121         .name = "ldb_clk",
122         .rate = CONFIG_SYS_LDB_CLOCK,
123         .enable = clk_ldb_enable,
124         .disable = clk_ldb_disable,
125 };
126
127 /* Globals */
128 struct clk *g_ipu_clk;
129 struct clk *g_ldb_clk;
130 struct clk *g_di_clk[2];
131 struct clk *g_pixel_clk[2];
132 unsigned char g_dc_di_assignment[10];
133 int g_ipu_clk_enabled;
134 u32 *ipu_dc_tmpl_reg;
135
136 static uint32_t g_channel_init_mask;
137 static uint32_t g_channel_enable_mask;
138 static int ipu_dc_use_count;
139 static int ipu_dp_use_count;
140 static int ipu_dmfc_use_count;
141 static int ipu_di_use_count[2];
142
143 static u32 *ipu_cpmem_base;
144
145 /* Static functions */
146
147 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
148 {
149         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
150 };
151
152 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
153 {
154         return ((uint32_t) ch >> (6 * type)) & 0x3F;
155 };
156
157 /* Either DP BG or DP FG can be graphic window */
158 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
159 {
160         return (dma_chan == 23 || dma_chan == 27);
161 }
162
163 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
164 {
165         return ((dma_chan >= 23) && (dma_chan <= 29));
166 }
167
168
169 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
170                                             dma_addr_t phyaddr)
171 {
172         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
173                                phyaddr / 8);
174 };
175
176 #define idma_is_valid(ch)       (ch != NO_DMA)
177 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
178 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
179
180 static void ipu_pixel_clk_recalc(struct clk *clk)
181 {
182         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
183         u64 parent_rate = (u64)clk->parent->rate * 16;
184
185         if (div == 0)
186                 clk->rate = 0;
187         else
188                 clk->rate = lldiv(parent_rate, div);
189 }
190
191 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
192         unsigned long rate)
193 {
194         u32 div, div1;
195         u64 tmp;
196
197         /*
198          * Calculate divider
199          * Fractional part is 4 bits,
200          * so simply multiply by 2^4 to get fractional part.
201          */
202         tmp = (u64)clk->parent->rate * 16;
203         div = lldiv(tmp, rate);
204
205         if (div < 0x10)            /* Min DI disp clock divider is 1 */
206                 div = 0x10;
207         if (div & ~0xFEF) {
208                 div &= 0xFF8;
209         } else {
210                 div1 = div & 0xFE0;
211
212                 if ((lldiv(tmp, div1) - lldiv(tmp, div)) < rate / 4)
213                         div = div1;
214                 else
215                         div &= 0xFF8;
216         }
217         do_div(tmp, div);
218 #if 1
219         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
220                 rate / 1000000, rate / 1000 % 1000,
221                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
222                 lldiv(tmp, 1000000), lldiv(tmp, 1000) % 1000, div / 16, div % 16);
223 #endif
224         return tmp;
225 }
226
227 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
228 {
229         u64 parent_rate = (u64)clk->parent->rate * 16;
230         u32 div = lldiv(parent_rate, rate);
231
232         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
233                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
234                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
235
236         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
237
238         /* Setup pixel clock timing */
239         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
240         clk->rate = lldiv(parent_rate, div);
241         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
242                 clk->rate / 1000000, clk->rate / 1000 % 1000);
243         return 0;
244 }
245
246 static int ipu_pixel_clk_enable(struct clk *clk)
247 {
248         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
249         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
250         __raw_writel(disp_gen, IPU_DISP_GEN);
251
252         return 0;
253 }
254
255 static void ipu_pixel_clk_disable(struct clk *clk)
256 {
257         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
258         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
259         __raw_writel(disp_gen, IPU_DISP_GEN);
260 }
261
262 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
263 {
264         int ret;
265         u32 di_gen;
266
267         ret = clk_enable(clk);
268         if (ret)
269                 return ret;
270
271         di_gen = __raw_readl(DI_GENERAL(clk->id));
272
273         if (parent == g_ipu_clk)
274                 di_gen &= ~DI_GEN_DI_CLK_EXT;
275         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
276                 di_gen |= DI_GEN_DI_CLK_EXT;
277         else
278                 goto err;
279
280         ret = clk_enable(parent);
281         if (ret)
282                 goto err;
283         __raw_writel(di_gen, DI_GENERAL(clk->id));
284         ipu_pixel_clk_recalc(clk);
285         clk->disable(clk->parent);
286         clk->parent = parent;
287 err:
288         clk_disable(clk);
289         return ret;
290 }
291
292 static struct clk pixel_clk[] = {
293         {
294                 .name = "pixel_clk",
295                 .id = 0,
296                 .recalc = ipu_pixel_clk_recalc,
297                 .set_rate = ipu_pixel_clk_set_rate,
298                 .round_rate = ipu_pixel_clk_round_rate,
299                 .set_parent = ipu_pixel_clk_set_parent,
300                 .enable = ipu_pixel_clk_enable,
301                 .disable = ipu_pixel_clk_disable,
302         },
303         {
304                 .name = "pixel_clk",
305                 .id = 1,
306                 .recalc = ipu_pixel_clk_recalc,
307                 .set_rate = ipu_pixel_clk_set_rate,
308                 .round_rate = ipu_pixel_clk_round_rate,
309                 .set_parent = ipu_pixel_clk_set_parent,
310                 .enable = ipu_pixel_clk_enable,
311                 .disable = ipu_pixel_clk_disable,
312         },
313 };
314
315 static int clk_ipu_di_enable(struct clk *clk)
316 {
317         ipu_di_clk_enable(clk->id);
318         return 0;
319 }
320
321 static void clk_ipu_di_disable(struct clk *clk)
322 {
323         ipu_di_clk_disable(clk->id);
324 }
325
326 static struct clk di_clk[] = {
327         {
328                 .name = "ipu_di_clk",
329                 .id = 0,
330                 .enable = clk_ipu_di_enable,
331                 .disable = clk_ipu_di_disable,
332         },
333         {
334                 .name = "ipu_di_clk",
335                 .id = 1,
336                 .enable = clk_ipu_di_enable,
337                 .disable = clk_ipu_di_disable,
338         },
339 };
340
341 /*
342  * This function resets IPU
343  */
344 static void ipu_reset(void)
345 {
346         u32 *reg;
347         u32 value;
348         int timeout = IPU_SW_RST_TOUT_USEC;
349
350         reg = (u32 *)SRC_BASE_ADDR;
351         value = __raw_readl(reg);
352         value = value | SW_IPU_RST;
353         __raw_writel(value, reg);
354
355         while (__raw_readl(reg) & SW_IPU_RST) {
356                 udelay(1);
357                 if (!(timeout--)) {
358                         printf("ipu software reset timeout\n");
359                         break;
360                 }
361         };
362 }
363
364 /*
365  * This function is called by the driver framework to initialize the IPU
366  * hardware.
367  *
368  * @param       dev     The device structure for the IPU passed in by the
369  *                      driver framework.
370  *
371  * @return      Returns 0 on success or negative error code on error
372  */
373 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
374 {
375         int ret;
376         void *ipu_base;
377         unsigned long start;
378 #if defined CONFIG_SOC_MX51
379         u32 temp;
380         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
381         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
382
383          __raw_writel(0xF00, reg_hsc_mcd);
384
385         /* CSI mode reserved */
386         temp = __raw_readl(reg_hsc_mxt_conf);
387          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
388
389         temp = __raw_readl(reg_hsc_mxt_conf);
390         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
391 #endif
392         ipu_base = (void *)IPU_SOC_BASE_ADDR;
393         /* base fixup */
394         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
395                 ipu_base += IPUV3H_REG_BASE;
396         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
397                 ipu_base += IPUV3M_REG_BASE;
398         else                    /* IPUv3D, v3E, v3EX */
399                 ipu_base += IPUV3DEX_REG_BASE;
400         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
401         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
402
403         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
404
405         g_pixel_clk[0] = &pixel_clk[0];
406         g_pixel_clk[1] = &pixel_clk[1];
407
408         g_di_clk[0] = &di_clk[0];
409         g_di_clk[1] = &di_clk[1];
410         g_di_clk[di]->rate = di_clk_val;
411
412         g_ipu_clk = &ipu_clk;
413         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
414
415         g_ldb_clk = &ldb_clk;
416         debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
417
418         ret = clk_enable(g_ipu_clk);
419         if (ret)
420                 return ret;
421         ipu_reset();
422
423         if (di_clk_parent == DI_PCLK_LDB) {
424                 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
425         } else {
426                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
427                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
428         }
429
430         __raw_writel(0x807FFFFF, IPU_MEM_RST);
431         start = get_timer_masked();
432         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
433                 if (get_timer(start) > CONFIG_SYS_HZ)
434                         return -ETIME;
435         }
436
437         ipu_init_dc_mappings();
438
439         __raw_writel(0, IPU_INT_CTRL(5));
440         __raw_writel(0, IPU_INT_CTRL(6));
441         __raw_writel(0, IPU_INT_CTRL(9));
442         __raw_writel(0, IPU_INT_CTRL(10));
443
444         /* DMFC Init */
445         ipu_dmfc_init(DMFC_NORMAL, 1);
446
447         /* Set sync refresh channels as high priority */
448         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
449
450         /* Set MCU_T to divide MCU access window into 2 */
451         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
452
453         clk_disable(g_ipu_clk);
454
455         return 0;
456 }
457
458 void ipu_dump_registers(void)
459 {
460         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
461         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
462         debug("IDMAC_CHA_EN1        0x%08X\n",
463                __raw_readl(IDMAC_CHA_EN(0)));
464         debug("IDMAC_CHA_EN2        0x%08X\n",
465                __raw_readl(IDMAC_CHA_EN(32)));
466         debug("IDMAC_CHA_PRI1       0x%08X\n",
467                __raw_readl(IDMAC_CHA_PRI(0)));
468         debug("IDMAC_CHA_PRI2       0x%08X\n",
469                __raw_readl(IDMAC_CHA_PRI(32)));
470         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
471                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
472         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
473                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
474         debug("DMFC_WR_CHAN         0x%08X\n",
475                __raw_readl(DMFC_WR_CHAN));
476         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
477                __raw_readl(DMFC_WR_CHAN_DEF));
478         debug("DMFC_DP_CHAN         0x%08X\n",
479                __raw_readl(DMFC_DP_CHAN));
480         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
481                __raw_readl(DMFC_DP_CHAN_DEF));
482         debug("DMFC_IC_CTRL         0x%08X\n",
483                __raw_readl(DMFC_IC_CTRL));
484         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
485                __raw_readl(IPU_FS_PROC_FLOW1));
486         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
487                __raw_readl(IPU_FS_PROC_FLOW2));
488         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
489                __raw_readl(IPU_FS_PROC_FLOW3));
490         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
491                __raw_readl(IPU_FS_DISP_FLOW1));
492 }
493
494 /*
495  * This function is called to initialize a logical IPU channel.
496  *
497  * @param       channel Input parameter for the logical channel ID to init.
498  *
499  * @param       params  Input parameter containing union of channel
500  *                      initialization parameters.
501  *
502  * @return      Returns 0 on success or negative error code on fail
503  */
504 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
505 {
506         int ret = 0;
507         uint32_t ipu_conf;
508
509         debug("init channel = %d\n", IPU_CHAN_ID(channel));
510
511         if (g_ipu_clk_enabled == 0) {
512                 g_ipu_clk_enabled = 1;
513                 clk_enable(g_ipu_clk);
514         }
515
516
517         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
518                 printf("Warning: channel already initialized %d\n",
519                         IPU_CHAN_ID(channel));
520         }
521
522         ipu_conf = __raw_readl(IPU_CONF);
523
524         switch (channel) {
525         case MEM_DC_SYNC:
526                 if (params->mem_dc_sync.di > 1) {
527                         ret = -EINVAL;
528                         goto err;
529                 }
530
531                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
532                 ipu_dc_init(1, params->mem_dc_sync.di,
533                              params->mem_dc_sync.interlaced);
534                 ipu_di_use_count[params->mem_dc_sync.di]++;
535                 ipu_dc_use_count++;
536                 ipu_dmfc_use_count++;
537                 break;
538         case MEM_BG_SYNC:
539                 if (params->mem_dp_bg_sync.di > 1) {
540                         ret = -EINVAL;
541                         goto err;
542                 }
543
544                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
545                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
546                              params->mem_dp_bg_sync.out_pixel_fmt);
547                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
548                              params->mem_dp_bg_sync.interlaced);
549                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
550                 ipu_dc_use_count++;
551                 ipu_dp_use_count++;
552                 ipu_dmfc_use_count++;
553                 break;
554         case MEM_FG_SYNC:
555                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
556                              params->mem_dp_fg_sync.out_pixel_fmt);
557
558                 ipu_dc_use_count++;
559                 ipu_dp_use_count++;
560                 ipu_dmfc_use_count++;
561                 break;
562         default:
563                 printf("Missing channel initialization\n");
564         }
565
566         /* Enable IPU sub module */
567         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
568         if (ipu_dc_use_count == 1)
569                 ipu_conf |= IPU_CONF_DC_EN;
570         if (ipu_dp_use_count == 1)
571                 ipu_conf |= IPU_CONF_DP_EN;
572         if (ipu_dmfc_use_count == 1)
573                 ipu_conf |= IPU_CONF_DMFC_EN;
574         if (ipu_di_use_count[0] == 1) {
575                 ipu_conf |= IPU_CONF_DI0_EN;
576                 clk_enable(g_di_clk[0]);
577         }
578         if (ipu_di_use_count[1] == 1) {
579                 ipu_conf |= IPU_CONF_DI1_EN;
580                 clk_enable(g_di_clk[1]);
581         }
582
583         __raw_writel(ipu_conf, IPU_CONF);
584
585 err:
586         return ret;
587 }
588
589 /*
590  * This function is called to uninitialize a logical IPU channel.
591  *
592  * @param       channel Input parameter for the logical channel ID to uninit.
593  */
594 void ipu_uninit_channel(ipu_channel_t channel)
595 {
596         uint32_t reg;
597         uint32_t in_dma, out_dma = 0;
598         uint32_t ipu_conf;
599
600         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
601                 debug("Channel already uninitialized %d\n",
602                         IPU_CHAN_ID(channel));
603                 return;
604         }
605
606         /*
607          * Make sure channel is disabled
608          * Get input and output dma channels
609          */
610         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
611         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
612
613         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
614             idma_is_set(IDMAC_CHA_EN, out_dma)) {
615                 printf("Channel %d is not disabled, disable first\n",
616                         IPU_CHAN_ID(channel));
617                 return;
618         }
619
620         ipu_conf = __raw_readl(IPU_CONF);
621
622         /* Reset the double buffer */
623         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
624         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
625         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
626         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
627
628         switch (channel) {
629         case MEM_DC_SYNC:
630                 ipu_dc_uninit(1);
631                 ipu_di_use_count[g_dc_di_assignment[1]]--;
632                 ipu_dc_use_count--;
633                 ipu_dmfc_use_count--;
634                 break;
635         case MEM_BG_SYNC:
636                 ipu_dp_uninit(channel);
637                 ipu_dc_uninit(5);
638                 ipu_di_use_count[g_dc_di_assignment[5]]--;
639                 ipu_dc_use_count--;
640                 ipu_dp_use_count--;
641                 ipu_dmfc_use_count--;
642                 break;
643         case MEM_FG_SYNC:
644                 ipu_dp_uninit(channel);
645                 ipu_dc_use_count--;
646                 ipu_dp_use_count--;
647                 ipu_dmfc_use_count--;
648                 break;
649         default:
650                 break;
651         }
652
653         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
654
655         if (ipu_dc_use_count == 0)
656                 ipu_conf &= ~IPU_CONF_DC_EN;
657         if (ipu_dp_use_count == 0)
658                 ipu_conf &= ~IPU_CONF_DP_EN;
659         if (ipu_dmfc_use_count == 0)
660                 ipu_conf &= ~IPU_CONF_DMFC_EN;
661         if (ipu_di_use_count[0] == 0 && ipu_conf & IPU_CONF_DI0_EN) {
662                 ipu_conf &= ~IPU_CONF_DI0_EN;
663                 clk_disable(g_di_clk[0]);
664         }
665         if (ipu_di_use_count[1] == 0 && ipu_conf & IPU_CONF_DI1_EN) {
666                 ipu_conf &= ~IPU_CONF_DI1_EN;
667                 clk_disable(g_di_clk[1]);
668         }
669
670         __raw_writel(ipu_conf, IPU_CONF);
671
672         /* clear interrupt status */
673         __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
674
675         if (ipu_conf == 0) {
676                 clk_disable(g_ipu_clk);
677                 g_ipu_clk_enabled = 0;
678         }
679 }
680
681 static inline void ipu_ch_param_dump(int ch)
682 {
683 #ifdef DEBUG
684         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
685         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
686                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
687                  p->word[0].data[3], p->word[0].data[4]);
688         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
689                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
690                  p->word[1].data[3], p->word[1].data[4]);
691         debug("PFS 0x%x, ",
692                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
693         debug("BPP 0x%x, ",
694                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
695         debug("NPB 0x%x\n",
696                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
697
698         debug("FW %d, ",
699                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
700         debug("FH %d, ",
701                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
702         debug("Stride %d\n",
703                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
704
705         debug("Width0 %d+1, ",
706                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
707         debug("Width1 %d+1, ",
708                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
709         debug("Width2 %d+1, ",
710                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
711         debug("Width3 %d+1, ",
712                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
713         debug("Offset0 %d, ",
714                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
715         debug("Offset1 %d, ",
716                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
717         debug("Offset2 %d, ",
718                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
719         debug("Offset3 %d\n",
720                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
721 #endif
722 }
723
724 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
725                                               int red_width, int red_offset,
726                                               int green_width, int green_offset,
727                                               int blue_width, int blue_offset,
728                                               int alpha_width, int alpha_offset)
729 {
730         /* Setup red width and offset */
731         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
732         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
733         /* Setup green width and offset */
734         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
735         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
736         /* Setup blue width and offset */
737         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
738         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
739         /* Setup alpha width and offset */
740         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
741         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
742 }
743
744 static void ipu_ch_param_init(int ch,
745                               uint32_t pixel_fmt, uint32_t width,
746                               uint32_t height, uint32_t stride,
747                               uint32_t u, uint32_t v,
748                               uint32_t uv_stride, dma_addr_t addr0,
749                               dma_addr_t addr1)
750 {
751         uint32_t u_offset = 0;
752         uint32_t v_offset = 0;
753
754         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
755
756         if ((ch == 8) || (ch == 9) || (ch == 10)) {
757                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
758                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
759         } else {
760                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
761                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
762         }
763
764         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
765         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
766
767         switch (pixel_fmt) {
768         case IPU_PIX_FMT_GENERIC:
769                 /*Represents 8-bit Generic data */
770                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
771                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
772                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
773
774                 break;
775         case IPU_PIX_FMT_GENERIC_32:
776                 /*Represents 32-bit Generic data */
777                 break;
778         case IPU_PIX_FMT_RGB565:
779                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
780                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
781                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
782
783                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
784                 break;
785         case IPU_PIX_FMT_BGR24:
786                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
787                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
788                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
789
790                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
791                 break;
792         case IPU_PIX_FMT_RGB24:
793         case IPU_PIX_FMT_YUV444:
794                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
795                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
796                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
797
798                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
799                 break;
800         case IPU_PIX_FMT_BGRA32:
801         case IPU_PIX_FMT_BGR32:
802                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
803                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
804                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
805
806                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
807                 break;
808         case IPU_PIX_FMT_RGBA32:
809         case IPU_PIX_FMT_RGB32:
810                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
811                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
812                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
813
814                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
815                 break;
816         case IPU_PIX_FMT_ABGR32:
817                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
818                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
819
820                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
821                 break;
822         case IPU_PIX_FMT_UYVY:
823                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
824                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
825                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
826                 break;
827         case IPU_PIX_FMT_YUYV:
828                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
829                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
830                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
831                 break;
832         case IPU_PIX_FMT_YUV420P2:
833         case IPU_PIX_FMT_YUV420P:
834                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
835
836                 if (uv_stride < stride / 2)
837                         uv_stride = stride / 2;
838
839                 u_offset = stride * height;
840                 v_offset = u_offset + (uv_stride * height / 2);
841                 /* burst size */
842                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
843                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
844                         uv_stride = uv_stride*2;
845                 } else {
846                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
847                 }
848                 break;
849         case IPU_PIX_FMT_YVU422P:
850                 /* BPP & pixel format */
851                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
852                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
853
854                 if (uv_stride < stride / 2)
855                         uv_stride = stride / 2;
856
857                 v_offset = (v == 0) ? stride * height : v;
858                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
859                 break;
860         case IPU_PIX_FMT_YUV422P:
861                 /* BPP & pixel format */
862                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
863                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
864
865                 if (uv_stride < stride / 2)
866                         uv_stride = stride / 2;
867
868                 u_offset = (u == 0) ? stride * height : u;
869                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
870                 break;
871         case IPU_PIX_FMT_NV12:
872                 /* BPP & pixel format */
873                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
874                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
875                 uv_stride = stride;
876                 u_offset = (u == 0) ? stride * height : u;
877                 break;
878         default:
879                 printf("mxc ipu: unimplemented pixel format: %08x\n",
880                         pixel_fmt);
881         }
882
883
884         if (uv_stride)
885                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
886
887         /* Get the uv offset from user when need cropping */
888         if (u || v) {
889                 u_offset = u;
890                 v_offset = v;
891         }
892
893         /* UBO and VBO are 22-bit */
894         if (u_offset/8 > 0x3fffff)
895                 puts("The value of U offset exceeds IPU limitation\n");
896         if (v_offset/8 > 0x3fffff)
897                 puts("The value of V offset exceeds IPU limitation\n");
898
899         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
900         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
901
902         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
903 };
904
905 /*
906  * This function is called to initialize a buffer for logical IPU channel.
907  *
908  * @param       channel         Input parameter for the logical channel ID.
909  *
910  * @param       type            Input parameter which buffer to initialize.
911  *
912  * @param       pixel_fmt       Input parameter for pixel format of buffer.
913  *                              Pixel format is a FOURCC ASCII code.
914  *
915  * @param       width           Input parameter for width of buffer in pixels.
916  *
917  * @param       height          Input parameter for height of buffer in pixels.
918  *
919  * @param       stride          Input parameter for stride length of buffer
920  *                              in pixels.
921  *
922  * @param       phyaddr_0       Input parameter buffer 0 physical address.
923  *
924  * @param       phyaddr_1       Input parameter buffer 1 physical address.
925  *                              Setting this to a value other than NULL enables
926  *                              double buffering mode.
927  *
928  * @param       u               private u offset for additional cropping,
929  *                              zero if not used.
930  *
931  * @param       v               private v offset for additional cropping,
932  *                              zero if not used.
933  *
934  * @return      Returns 0 on success or negative error code on fail
935  */
936 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
937                                 uint32_t pixel_fmt,
938                                 uint16_t width, uint16_t height,
939                                 uint32_t stride,
940                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
941                                 uint32_t u, uint32_t v)
942 {
943         uint32_t reg;
944         uint32_t dma_chan;
945
946         dma_chan = channel_2_dma(channel, type);
947         if (!idma_is_valid(dma_chan))
948                 return -EINVAL;
949
950         if (stride < width * bytes_per_pixel(pixel_fmt))
951                 stride = width * bytes_per_pixel(pixel_fmt);
952
953         if (stride % 4) {
954                 printf("Stride %d not 32-bit aligned\n", stride);
955                 return -EINVAL;
956         }
957         /* Build parameter memory data for DMA channel */
958         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
959                            phyaddr_0, phyaddr_1);
960
961         if (ipu_is_dmfc_chan(dma_chan)) {
962                 ipu_dmfc_set_wait4eot(dma_chan, width);
963         }
964
965         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
966                 ipu_ch_param_set_high_priority(dma_chan);
967
968         ipu_ch_param_dump(dma_chan);
969
970         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
971         if (phyaddr_1)
972                 reg |= idma_mask(dma_chan);
973         else
974                 reg &= ~idma_mask(dma_chan);
975         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
976
977         /* Reset to buffer 0 */
978         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
979
980         return 0;
981 }
982
983 /*
984  * This function enables a logical channel.
985  *
986  * @param       channel         Input parameter for the logical channel ID.
987  *
988  * @return      This function returns 0 on success or negative error code on
989  *              fail.
990  */
991 int32_t ipu_enable_channel(ipu_channel_t channel)
992 {
993         uint32_t reg;
994         uint32_t in_dma;
995         uint32_t out_dma;
996
997         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
998                 printf("Warning: channel already enabled %d\n",
999                         IPU_CHAN_ID(channel));
1000         }
1001
1002         /* Get input and output dma channels */
1003         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1004         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1005
1006         if (idma_is_valid(in_dma)) {
1007                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1008                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1009         }
1010         if (idma_is_valid(out_dma)) {
1011                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1012                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1013         }
1014
1015         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1016             (channel == MEM_FG_SYNC)) {
1017                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1018                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1019
1020                 ipu_dp_dc_enable(channel);
1021         }
1022
1023         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1024
1025         return 0;
1026 }
1027
1028 /*
1029  * This function clear buffer ready for a logical channel.
1030  *
1031  * @param       channel         Input parameter for the logical channel ID.
1032  *
1033  * @param       type            Input parameter which buffer to clear.
1034  *
1035  * @param       bufNum          Input parameter for which buffer number clear
1036  *                              ready state.
1037  *
1038  */
1039 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1040                 uint32_t bufNum)
1041 {
1042         uint32_t dma_ch = channel_2_dma(channel, type);
1043
1044         if (!idma_is_valid(dma_ch))
1045                 return;
1046
1047         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1048         if (bufNum == 0) {
1049                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1050                         __raw_writel(idma_mask(dma_ch),
1051                                         IPU_CHA_BUF0_RDY(dma_ch));
1052                 }
1053         } else {
1054                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1055                         __raw_writel(idma_mask(dma_ch),
1056                                         IPU_CHA_BUF1_RDY(dma_ch));
1057                 }
1058         }
1059         __raw_writel(0x0, IPU_GPR); /* write one to set */
1060 }
1061
1062 /*
1063  * This function disables a logical channel.
1064  *
1065  * @param       channel         Input parameter for the logical channel ID.
1066  *
1067  * @param       wait_for_stop   Flag to set whether to wait for channel end
1068  *                              of frame or return immediately.
1069  *
1070  * @return      This function returns 0 on success or negative error code on
1071  *              fail.
1072  */
1073 int32_t ipu_disable_channel(ipu_channel_t channel)
1074 {
1075         uint32_t reg;
1076         uint32_t in_dma;
1077         uint32_t out_dma;
1078
1079         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1080                 debug("Channel already disabled %d\n",
1081                         IPU_CHAN_ID(channel));
1082                 return 0;
1083         }
1084
1085         /* Get input and output dma channels */
1086         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1087         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1088
1089         if ((idma_is_valid(in_dma) &&
1090                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1091                 && (idma_is_valid(out_dma) &&
1092                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1093                 return -EINVAL;
1094
1095         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1096             (channel == MEM_DC_SYNC)) {
1097                 ipu_dp_dc_disable(channel, 0);
1098         }
1099
1100         /* Disable DMA channel(s) */
1101         if (idma_is_valid(in_dma)) {
1102                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1103                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1104                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1105         }
1106         if (idma_is_valid(out_dma)) {
1107                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1108                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1109                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1110         }
1111
1112         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1113
1114         /* Set channel buffers NOT to be ready */
1115         if (idma_is_valid(in_dma)) {
1116                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1117                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1118         }
1119         if (idma_is_valid(out_dma)) {
1120                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1121                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1122         }
1123
1124         return 0;
1125 }
1126
1127 uint32_t bytes_per_pixel(uint32_t fmt)
1128 {
1129         switch (fmt) {
1130         case IPU_PIX_FMT_GENERIC:       /* generic data */
1131         case IPU_PIX_FMT_RGB332:
1132         case IPU_PIX_FMT_YUV420P:
1133         case IPU_PIX_FMT_YUV422P:
1134                 return 1;
1135         case IPU_PIX_FMT_RGB565:
1136         case IPU_PIX_FMT_YUYV:
1137         case IPU_PIX_FMT_UYVY:
1138                 return 2;
1139         case IPU_PIX_FMT_BGR24:
1140         case IPU_PIX_FMT_RGB24:
1141                 return 3;
1142         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
1143         case IPU_PIX_FMT_BGR32:
1144         case IPU_PIX_FMT_BGRA32:
1145         case IPU_PIX_FMT_RGB32:
1146         case IPU_PIX_FMT_RGBA32:
1147         case IPU_PIX_FMT_ABGR32:
1148                 return 4;
1149         default:
1150                 return 1;
1151         }
1152         return 0;
1153 }
1154
1155 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1156 {
1157         switch (fmt) {
1158         case IPU_PIX_FMT_RGB666:
1159         case IPU_PIX_FMT_RGB565:
1160         case IPU_PIX_FMT_BGR24:
1161         case IPU_PIX_FMT_RGB24:
1162         case IPU_PIX_FMT_BGR32:
1163         case IPU_PIX_FMT_BGRA32:
1164         case IPU_PIX_FMT_RGB32:
1165         case IPU_PIX_FMT_RGBA32:
1166         case IPU_PIX_FMT_ABGR32:
1167         case IPU_PIX_FMT_LVDS666:
1168         case IPU_PIX_FMT_LVDS888:
1169                 return RGB;
1170
1171         default:
1172                 return YCbCr;
1173         }
1174         return RGB;
1175 }
1176
1177 /* should be removed when clk framework is availiable */
1178 int ipu_set_ldb_clock(int rate)
1179 {
1180         ldb_clk.rate = rate;
1181
1182         return 0;
1183 }