drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /* #define DEBUG */
  15 #include <common.h>
  16 #include <ipu.h>
  17 #include <linux/types.h>
  18 #include <linux/err.h>
  19 #include <asm/io.h>
  20 #include <asm/errno.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/arch/clock.h>
  24
  25 #include "ipu_regs.h"
  26
  27 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
  28
  29 struct ipu_ch_param_word {
  30         uint32_t data[5];
  31         uint32_t res[3];
  32 };
  33
  34 struct ipu_ch_param {
  35         struct ipu_ch_param_word word[2];
  36 };
  37
  38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  39
  40 #define _param_word(base, w) \
  41         (((struct ipu_ch_param *)(base))->word[w].data)
  42
  43 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
  44         int i = (bit) / 32;                                             \
  45         int off = (bit) % 32;                                           \
  46         _param_word(base, w)[i] |= (v) << off;                          \
  47         if (((bit) + (size) - 1) / 32 > i) {                            \
  48                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  49         }                                                               \
  50 }
  51
  52 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
  53         int i = (bit) / 32;                                     \
  54         int off = (bit) % 32;                                   \
  55         u32 mask = (1UL << size) - 1;                           \
  56         u32 temp = _param_word(base, w)[i];                     \
  57         temp &= ~(mask << off);                                 \
  58         _param_word(base, w)[i] = temp | (v) << off;            \
  59         if (((bit) + (size) - 1) / 32 > i) {                    \
  60                 temp = _param_word(base, w)[i + 1];             \
  61                 temp &= ~(mask >> (32 - off));                  \
  62                 _param_word(base, w)[i + 1] =                   \
  63                         temp | ((v) >> (off ? (32 - off) : 0)); \
  64         }                                                       \
  65 }
  66
  67 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
  68         u32 temp2;                                              \
  69         int i = (bit) / 32;                                     \
  70         int off = (bit) % 32;                                   \
  71         u32 mask = (1UL << size) - 1;                           \
  72         u32 temp1 = _param_word(base, w)[i];                    \
  73         temp1 = mask & (temp1 >> off);                          \
  74         if (((bit)+(size) - 1) / 32 > i) {                      \
  75                 temp2 = _param_word(base, w)[i + 1];            \
  76                 temp2 &= mask >> (off ? (32 - off) : 0);        \
  77                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
  78         }                                                       \
  79         temp1;                                                  \
  80 })
  81
  82 #define IPU_SW_RST_TOUT_USEC    10000
  83
  84 static int clk_ipu_enable(struct clk *clk)
  85 {
  86         ipu_clk_enable();
  87         return 0;
  88 }
  89
  90 static void clk_ipu_disable(struct clk *clk)
  91 {
  92         ipu_clk_disable();
  93 }
  94
  95 static struct clk ipu_clk = {
  96         .name = "ipu_clk",
  97         .rate = CONFIG_IPUV3_CLK,
  98         .enable = clk_ipu_enable,
  99         .disable = clk_ipu_disable,
 100 };
 101
 102 static int clk_ldb_enable(struct clk *clk)
 103 {
 104         ldb_clk_enable(0);
 105         ldb_clk_enable(1);
 106         return 0;
 107 }
 108
 109 static void clk_ldb_disable(struct clk *clk)
 110 {
 111         ldb_clk_disable(0);
 112         ldb_clk_disable(1);
 113 }
 114
 115 static struct clk ldb_clk = {
 116         .name = "ldb_clk",
 117         .rate = 65000000,
 118         .enable = clk_ldb_enable,
 119         .disable = clk_ldb_disable,
 120 };
 121
 122 /* Globals */
 123 struct clk *g_ipu_clk;
 124 struct clk *g_ldb_clk;
 125 struct clk *g_di_clk[2];
 126 struct clk *g_pixel_clk[2];
 127 unsigned char g_dc_di_assignment[10];
 128 int g_ipu_clk_enabled;
 129 u32 *ipu_dc_tmpl_reg;
 130
 131 static uint32_t g_channel_init_mask;
 132 static uint32_t g_channel_enable_mask;
 133 static int ipu_dc_use_count;
 134 static int ipu_dp_use_count;
 135 static int ipu_dmfc_use_count;
 136 static int ipu_di_use_count[2];
 137
 138 static u32 *ipu_cpmem_base;
 139
 140 /* Static functions */
 141
 142 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 143 {
 144         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 145 };
 146
 147 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 148 {
 149         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 150 };
 151
 152 /* Either DP BG or DP FG can be graphic window */
 153 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 154 {
 155         return (dma_chan == 23 || dma_chan == 27);
 156 }
 157
 158 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 159 {
 160         return ((dma_chan >= 23) && (dma_chan <= 29));
 161 }
 162
 163
 164 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 165                                             dma_addr_t phyaddr)
 166 {
 167         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 168                                phyaddr / 8);
 169 };
 170
 171 #define idma_is_valid(ch)       (ch != NO_DMA)
 172 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 173 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 174
 175 static void ipu_pixel_clk_recalc(struct clk *clk)
 176 {
 177         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 178         if (div == 0)
 179                 clk->rate = 0;
 180         else
 181                 clk->rate = (clk->parent->rate * 16) / div;
 182 }
 183
 184 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 185         unsigned long rate)
 186 {
 187         u32 div, div1;
 188         u64 tmp;
 189         /*
 190          * Calculate divider
 191          * Fractional part is 4 bits,
 192          * so simply multiply by 2^4 to get fractional part.
 193          */
 194         tmp = (u64)clk->parent->rate * 16;
 195         div = tmp / rate;
 196
 197         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 198                 div = 0x10;
 199         if (div & ~0xFEF)
 200                 div &= 0xFF8;
 201         else {
 202                 div1 = div & 0xFE0;
 203                 if ((tmp/div1 - tmp/div) < rate / 4)
 204                         div = div1;
 205                 else
 206                         div &= 0xFF8;
 207         }
 208         tmp /= div;
 209 #if 1
 210         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
 211                 rate / 1000000, rate / 1000 % 1000,
 212                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 213                 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
 214 #endif
 215         return tmp;
 216 }
 217
 218 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 219 {
 220         u32 div = ((u64)clk->parent->rate * 16) / rate;
 221
 222         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
 223                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 224                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
 225
 226         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 227
 228         /* Setup pixel clock timing */
 229         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 230
 231         clk->rate = ((u64)clk->parent->rate * 16) / div;
 232         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
 233                 clk->rate / 1000000, clk->rate / 1000 % 1000);
 234         return 0;
 235 }
 236
 237 static int ipu_pixel_clk_enable(struct clk *clk)
 238 {
 239         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 240         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 241         __raw_writel(disp_gen, IPU_DISP_GEN);
 242
 243         return 0;
 244 }
 245
 246 static void ipu_pixel_clk_disable(struct clk *clk)
 247 {
 248         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 249         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 250         __raw_writel(disp_gen, IPU_DISP_GEN);
 251 }
 252
 253 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 254 {
 255         int ret;
 256         u32 di_gen;
 257
 258         ret = clk_enable(clk);
 259         if (ret)
 260                 return ret;
 261
 262         di_gen = __raw_readl(DI_GENERAL(clk->id));
 263
 264         if (parent == g_ipu_clk)
 265                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 266         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
 267                 di_gen |= DI_GEN_DI_CLK_EXT;
 268         else
 269                 goto err;
 270
 271         ret = clk_enable(parent);
 272         if (ret)
 273                 goto err;
 274         __raw_writel(di_gen, DI_GENERAL(clk->id));
 275         ipu_pixel_clk_recalc(clk);
 276         clk->disable(clk->parent);
 277         clk->parent = parent;
 278 err:
 279         clk_disable(clk);
 280         return ret;
 281 }
 282
 283 static struct clk pixel_clk[] = {
 284         {
 285                 .name = "pixel_clk",
 286                 .id = 0,
 287                 .recalc = ipu_pixel_clk_recalc,
 288                 .set_rate = ipu_pixel_clk_set_rate,
 289                 .round_rate = ipu_pixel_clk_round_rate,
 290                 .set_parent = ipu_pixel_clk_set_parent,
 291                 .enable = ipu_pixel_clk_enable,
 292                 .disable = ipu_pixel_clk_disable,
 293         },
 294         {
 295                 .name = "pixel_clk",
 296                 .id = 1,
 297                 .recalc = ipu_pixel_clk_recalc,
 298                 .set_rate = ipu_pixel_clk_set_rate,
 299                 .round_rate = ipu_pixel_clk_round_rate,
 300                 .set_parent = ipu_pixel_clk_set_parent,
 301                 .enable = ipu_pixel_clk_enable,
 302                 .disable = ipu_pixel_clk_disable,
 303         },
 304 };
 305
 306 static int clk_ipu_di_enable(struct clk *clk)
 307 {
 308         ipu_di_clk_enable(clk->id);
 309         return 0;
 310 }
 311
 312 static void clk_ipu_di_disable(struct clk *clk)
 313 {
 314         ipu_di_clk_disable(clk->id);
 315 }
 316
 317 static struct clk di_clk[] = {
 318         {
 319                 .name = "ipu_di_clk",
 320                 .id = 0,
 321                 .enable = clk_ipu_di_enable,
 322                 .disable = clk_ipu_di_disable,
 323         },
 324         {
 325                 .name = "ipu_di_clk",
 326                 .id = 1,
 327                 .enable = clk_ipu_di_enable,
 328                 .disable = clk_ipu_di_disable,
 329         },
 330 };
 331
 332 /*
 333  * This function resets IPU
 334  */
 335 static void ipu_reset(void)
 336 {
 337         u32 *reg;
 338         u32 value;
 339         int timeout = IPU_SW_RST_TOUT_USEC;
 340
 341         reg = (u32 *)SRC_BASE_ADDR;
 342         value = __raw_readl(reg);
 343         value = value | SW_IPU_RST;
 344         __raw_writel(value, reg);
 345
 346         while (__raw_readl(reg) & SW_IPU_RST) {
 347                 udelay(1);
 348                 if (!(timeout--)) {
 349                         printf("ipu software reset timeout\n");
 350                         break;
 351                 }
 352         };
 353 }
 354
 355 /*
 356  * This function is called by the driver framework to initialize the IPU
 357  * hardware.
 358  *
 359  * @param       dev     The device structure for the IPU passed in by the
 360  *                      driver framework.
 361  *
 362  * @return      Returns 0 on success or negative error code on error
 363  */
 364 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
 365 {
 366         int ret;
 367         void *ipu_base;
 368         unsigned long start;
 369 #if defined CONFIG_SOC_MX51
 370         u32 temp;
 371         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 372         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 373
 374          __raw_writel(0xF00, reg_hsc_mcd);
 375
 376         /* CSI mode reserved */
 377         temp = __raw_readl(reg_hsc_mxt_conf);
 378          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 379
 380         temp = __raw_readl(reg_hsc_mxt_conf);
 381         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 382 #endif
 383         ipu_base = (void *)IPU_SOC_BASE_ADDR;
 384         /* base fixup */
 385         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
 386                 ipu_base += IPUV3H_REG_BASE;
 387         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
 388                 ipu_base += IPUV3M_REG_BASE;
 389         else                    /* IPUv3D, v3E, v3EX */
 390                 ipu_base += IPUV3DEX_REG_BASE;
 391         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
 392         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
 393
 394         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
 395
 396         g_pixel_clk[0] = &pixel_clk[0];
 397         g_pixel_clk[1] = &pixel_clk[1];
 398
 399         g_di_clk[0] = &di_clk[0];
 400         g_di_clk[1] = &di_clk[1];
 401         g_di_clk[di]->rate = di_clk_val;
 402
 403         g_ipu_clk = &ipu_clk;
 404         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 405
 406         g_ldb_clk = &ldb_clk;
 407         debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
 408
 409         ret = clk_enable(g_ipu_clk);
 410         if (ret)
 411                 return ret;
 412         ipu_reset();
 413
 414         if (di_clk_parent == DI_PCLK_LDB) {
 415                 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
 416         } else {
 417                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 418                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 419         }
 420
 421         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 422         start = get_timer_masked();
 423         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
 424                 if (get_timer(start) > CONFIG_SYS_HZ)
 425                         return -ETIME;
 426         }
 427
 428         ipu_init_dc_mappings();
 429
 430         __raw_writel(0, IPU_INT_CTRL(5));
 431         __raw_writel(0, IPU_INT_CTRL(6));
 432         __raw_writel(0, IPU_INT_CTRL(9));
 433         __raw_writel(0, IPU_INT_CTRL(10));
 434
 435         /* DMFC Init */
 436         ipu_dmfc_init(DMFC_NORMAL, 1);
 437
 438         /* Set sync refresh channels as high priority */
 439         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 440
 441         /* Set MCU_T to divide MCU access window into 2 */
 442         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 443
 444         clk_disable(g_ipu_clk);
 445
 446         return 0;
 447 }
 448
 449 void ipu_dump_registers(void)
 450 {
 451         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
 452         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
 453         debug("IDMAC_CHA_EN1        0x%08X\n",
 454                __raw_readl(IDMAC_CHA_EN(0)));
 455         debug("IDMAC_CHA_EN2        0x%08X\n",
 456                __raw_readl(IDMAC_CHA_EN(32)));
 457         debug("IDMAC_CHA_PRI1       0x%08X\n",
 458                __raw_readl(IDMAC_CHA_PRI(0)));
 459         debug("IDMAC_CHA_PRI2       0x%08X\n",
 460                __raw_readl(IDMAC_CHA_PRI(32)));
 461         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
 462                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 463         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
 464                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 465         debug("DMFC_WR_CHAN         0x%08X\n",
 466                __raw_readl(DMFC_WR_CHAN));
 467         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
 468                __raw_readl(DMFC_WR_CHAN_DEF));
 469         debug("DMFC_DP_CHAN         0x%08X\n",
 470                __raw_readl(DMFC_DP_CHAN));
 471         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
 472                __raw_readl(DMFC_DP_CHAN_DEF));
 473         debug("DMFC_IC_CTRL         0x%08X\n",
 474                __raw_readl(DMFC_IC_CTRL));
 475         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
 476                __raw_readl(IPU_FS_PROC_FLOW1));
 477         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
 478                __raw_readl(IPU_FS_PROC_FLOW2));
 479         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
 480                __raw_readl(IPU_FS_PROC_FLOW3));
 481         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
 482                __raw_readl(IPU_FS_DISP_FLOW1));
 483 }
 484
 485 /*
 486  * This function is called to initialize a logical IPU channel.
 487  *
 488  * @param       channel Input parameter for the logical channel ID to init.
 489  *
 490  * @param       params  Input parameter containing union of channel
 491  *                      initialization parameters.
 492  *
 493  * @return      Returns 0 on success or negative error code on fail
 494  */
 495 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 496 {
 497         int ret = 0;
 498         uint32_t ipu_conf;
 499
 500         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 501
 502         if (g_ipu_clk_enabled == 0) {
 503                 g_ipu_clk_enabled = 1;
 504                 clk_enable(g_ipu_clk);
 505         }
 506
 507
 508         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 509                 printf("Warning: channel already initialized %d\n",
 510                         IPU_CHAN_ID(channel));
 511         }
 512
 513         ipu_conf = __raw_readl(IPU_CONF);
 514
 515         switch (channel) {
 516         case MEM_DC_SYNC:
 517                 if (params->mem_dc_sync.di > 1) {
 518                         ret = -EINVAL;
 519                         goto err;
 520                 }
 521
 522                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 523                 ipu_dc_init(1, params->mem_dc_sync.di,
 524                              params->mem_dc_sync.interlaced);
 525                 ipu_di_use_count[params->mem_dc_sync.di]++;
 526                 ipu_dc_use_count++;
 527                 ipu_dmfc_use_count++;
 528                 break;
 529         case MEM_BG_SYNC:
 530                 if (params->mem_dp_bg_sync.di > 1) {
 531                         ret = -EINVAL;
 532                         goto err;
 533                 }
 534
 535                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 536                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 537                              params->mem_dp_bg_sync.out_pixel_fmt);
 538                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 539                              params->mem_dp_bg_sync.interlaced);
 540                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 541                 ipu_dc_use_count++;
 542                 ipu_dp_use_count++;
 543                 ipu_dmfc_use_count++;
 544                 break;
 545         case MEM_FG_SYNC:
 546                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 547                              params->mem_dp_fg_sync.out_pixel_fmt);
 548
 549                 ipu_dc_use_count++;
 550                 ipu_dp_use_count++;
 551                 ipu_dmfc_use_count++;
 552                 break;
 553         default:
 554                 printf("Missing channel initialization\n");
 555         }
 556
 557         /* Enable IPU sub module */
 558         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 559         if (ipu_dc_use_count == 1)
 560                 ipu_conf |= IPU_CONF_DC_EN;
 561         if (ipu_dp_use_count == 1)
 562                 ipu_conf |= IPU_CONF_DP_EN;
 563         if (ipu_dmfc_use_count == 1)
 564                 ipu_conf |= IPU_CONF_DMFC_EN;
 565         if (ipu_di_use_count[0] == 1) {
 566                 ipu_conf |= IPU_CONF_DI0_EN;
 567                 clk_enable(g_di_clk[0]);
 568         }
 569         if (ipu_di_use_count[1] == 1) {
 570                 ipu_conf |= IPU_CONF_DI1_EN;
 571                 clk_enable(g_di_clk[1]);
 572         }
 573
 574         __raw_writel(ipu_conf, IPU_CONF);
 575
 576 err:
 577         return ret;
 578 }
 579
 580 /*
 581  * This function is called to uninitialize a logical IPU channel.
 582  *
 583  * @param       channel Input parameter for the logical channel ID to uninit.
 584  */
 585 void ipu_uninit_channel(ipu_channel_t channel)
 586 {
 587         uint32_t reg;
 588         uint32_t in_dma, out_dma = 0;
 589         uint32_t ipu_conf;
 590
 591         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 592                 debug("Channel already uninitialized %d\n",
 593                         IPU_CHAN_ID(channel));
 594                 return;
 595         }
 596
 597         /*
 598          * Make sure channel is disabled
 599          * Get input and output dma channels
 600          */
 601         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 602         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 603
 604         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 605             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 606                 printf("Channel %d is not disabled, disable first\n",
 607                         IPU_CHAN_ID(channel));
 608                 return;
 609         }
 610
 611         ipu_conf = __raw_readl(IPU_CONF);
 612
 613         /* Reset the double buffer */
 614         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 615         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 616         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 617         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 618
 619         switch (channel) {
 620         case MEM_DC_SYNC:
 621                 ipu_dc_uninit(1);
 622                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 623                 ipu_dc_use_count--;
 624                 ipu_dmfc_use_count--;
 625                 break;
 626         case MEM_BG_SYNC:
 627                 ipu_dp_uninit(channel);
 628                 ipu_dc_uninit(5);
 629                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 630                 ipu_dc_use_count--;
 631                 ipu_dp_use_count--;
 632                 ipu_dmfc_use_count--;
 633                 break;
 634         case MEM_FG_SYNC:
 635                 ipu_dp_uninit(channel);
 636                 ipu_dc_use_count--;
 637                 ipu_dp_use_count--;
 638                 ipu_dmfc_use_count--;
 639                 break;
 640         default:
 641                 break;
 642         }
 643
 644         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 645
 646         if (ipu_dc_use_count == 0)
 647                 ipu_conf &= ~IPU_CONF_DC_EN;
 648         if (ipu_dp_use_count == 0)
 649                 ipu_conf &= ~IPU_CONF_DP_EN;
 650         if (ipu_dmfc_use_count == 0)
 651                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 652         if (ipu_di_use_count[0] == 0 && ipu_conf & IPU_CONF_DI0_EN) {
 653                 ipu_conf &= ~IPU_CONF_DI0_EN;
 654                 clk_disable(g_di_clk[0]);
 655         }
 656         if (ipu_di_use_count[1] == 0 && ipu_conf & IPU_CONF_DI1_EN) {
 657                 ipu_conf &= ~IPU_CONF_DI1_EN;
 658                 clk_disable(g_di_clk[1]);
 659         }
 660
 661         __raw_writel(ipu_conf, IPU_CONF);
 662
 663         /* clear interrupt status */
 664         __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
 665
 666         if (ipu_conf == 0) {
 667                 clk_disable(g_ipu_clk);
 668                 g_ipu_clk_enabled = 0;
 669         }
 670 }
 671
 672 static inline void ipu_ch_param_dump(int ch)
 673 {
 674 #ifdef DEBUG
 675         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 676         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 677                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 678                  p->word[0].data[3], p->word[0].data[4]);
 679         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 680                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 681                  p->word[1].data[3], p->word[1].data[4]);
 682         debug("PFS 0x%x, ",
 683                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 684         debug("BPP 0x%x, ",
 685                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 686         debug("NPB 0x%x\n",
 687                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 688
 689         debug("FW %d, ",
 690                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 691         debug("FH %d, ",
 692                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 693         debug("Stride %d\n",
 694                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 695
 696         debug("Width0 %d+1, ",
 697                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 698         debug("Width1 %d+1, ",
 699                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 700         debug("Width2 %d+1, ",
 701                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 702         debug("Width3 %d+1, ",
 703                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 704         debug("Offset0 %d, ",
 705                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 706         debug("Offset1 %d, ",
 707                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 708         debug("Offset2 %d, ",
 709                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 710         debug("Offset3 %d\n",
 711                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 712 #endif
 713 }
 714
 715 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 716                                               int red_width, int red_offset,
 717                                               int green_width, int green_offset,
 718                                               int blue_width, int blue_offset,
 719                                               int alpha_width, int alpha_offset)
 720 {
 721         /* Setup red width and offset */
 722         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 723         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 724         /* Setup green width and offset */
 725         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 726         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 727         /* Setup blue width and offset */
 728         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 729         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 730         /* Setup alpha width and offset */
 731         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 732         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 733 }
 734
 735 static void ipu_ch_param_init(int ch,
 736                               uint32_t pixel_fmt, uint32_t width,
 737                               uint32_t height, uint32_t stride,
 738                               uint32_t u, uint32_t v,
 739                               uint32_t uv_stride, dma_addr_t addr0,
 740                               dma_addr_t addr1)
 741 {
 742         uint32_t u_offset = 0;
 743         uint32_t v_offset = 0;
 744
 745         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
 746
 747         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 748                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
 749                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
 750         } else {
 751                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
 752                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
 753         }
 754
 755         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
 756         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
 757
 758         switch (pixel_fmt) {
 759         case IPU_PIX_FMT_GENERIC:
 760                 /*Represents 8-bit Generic data */
 761                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
 762                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
 763                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
 764
 765                 break;
 766         case IPU_PIX_FMT_GENERIC_32:
 767                 /*Represents 32-bit Generic data */
 768                 break;
 769         case IPU_PIX_FMT_RGB565:
 770                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 771                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 772                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 773
 774                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
 775                 break;
 776         case IPU_PIX_FMT_BGR24:
 777                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 778                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 779                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 780
 781                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 782                 break;
 783         case IPU_PIX_FMT_RGB24:
 784         case IPU_PIX_FMT_YUV444:
 785                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 786                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 787                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 788
 789                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
 790                 break;
 791         case IPU_PIX_FMT_BGRA32:
 792         case IPU_PIX_FMT_BGR32:
 793                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 794                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 795                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 796
 797                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
 798                 break;
 799         case IPU_PIX_FMT_RGBA32:
 800         case IPU_PIX_FMT_RGB32:
 801                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 802                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 803                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 804
 805                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
 806                 break;
 807         case IPU_PIX_FMT_ABGR32:
 808                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 809                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 810
 811                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 812                 break;
 813         case IPU_PIX_FMT_UYVY:
 814                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 815                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
 816                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 817                 break;
 818         case IPU_PIX_FMT_YUYV:
 819                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 820                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
 821                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 822                 break;
 823         case IPU_PIX_FMT_YUV420P2:
 824         case IPU_PIX_FMT_YUV420P:
 825                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
 826
 827                 if (uv_stride < stride / 2)
 828                         uv_stride = stride / 2;
 829
 830                 u_offset = stride * height;
 831                 v_offset = u_offset + (uv_stride * height / 2);
 832                 /* burst size */
 833                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 834                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
 835                         uv_stride = uv_stride*2;
 836                 } else {
 837                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
 838                 }
 839                 break;
 840         case IPU_PIX_FMT_YVU422P:
 841                 /* BPP & pixel format */
 842                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 843                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 844
 845                 if (uv_stride < stride / 2)
 846                         uv_stride = stride / 2;
 847
 848                 v_offset = (v == 0) ? stride * height : v;
 849                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 850                 break;
 851         case IPU_PIX_FMT_YUV422P:
 852                 /* BPP & pixel format */
 853                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 854                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 855
 856                 if (uv_stride < stride / 2)
 857                         uv_stride = stride / 2;
 858
 859                 u_offset = (u == 0) ? stride * height : u;
 860                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 861                 break;
 862         case IPU_PIX_FMT_NV12:
 863                 /* BPP & pixel format */
 864                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
 865                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 866                 uv_stride = stride;
 867                 u_offset = (u == 0) ? stride * height : u;
 868                 break;
 869         default:
 870                 printf("mxc ipu: unimplemented pixel format: %08x\n",
 871                         pixel_fmt);
 872         }
 873
 874
 875         if (uv_stride)
 876                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
 877
 878         /* Get the uv offset from user when need cropping */
 879         if (u || v) {
 880                 u_offset = u;
 881                 v_offset = v;
 882         }
 883
 884         /* UBO and VBO are 22-bit */
 885         if (u_offset/8 > 0x3fffff)
 886                 puts("The value of U offset exceeds IPU limitation\n");
 887         if (v_offset/8 > 0x3fffff)
 888                 puts("The value of V offset exceeds IPU limitation\n");
 889
 890         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 891         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
 892
 893         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 894 };
 895
 896 /*
 897  * This function is called to initialize a buffer for logical IPU channel.
 898  *
 899  * @param       channel         Input parameter for the logical channel ID.
 900  *
 901  * @param       type            Input parameter which buffer to initialize.
 902  *
 903  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 904  *                              Pixel format is a FOURCC ASCII code.
 905  *
 906  * @param       width           Input parameter for width of buffer in pixels.
 907  *
 908  * @param       height          Input parameter for height of buffer in pixels.
 909  *
 910  * @param       stride          Input parameter for stride length of buffer
 911  *                              in pixels.
 912  *
 913  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 914  *
 915  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 916  *                              Setting this to a value other than NULL enables
 917  *                              double buffering mode.
 918  *
 919  * @param       u               private u offset for additional cropping,
 920  *                              zero if not used.
 921  *
 922  * @param       v               private v offset for additional cropping,
 923  *                              zero if not used.
 924  *
 925  * @return      Returns 0 on success or negative error code on fail
 926  */
 927 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 928                                 uint32_t pixel_fmt,
 929                                 uint16_t width, uint16_t height,
 930                                 uint32_t stride,
 931                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 932                                 uint32_t u, uint32_t v)
 933 {
 934         uint32_t reg;
 935         uint32_t dma_chan;
 936
 937         dma_chan = channel_2_dma(channel, type);
 938         if (!idma_is_valid(dma_chan))
 939                 return -EINVAL;
 940
 941         if (stride < width * bytes_per_pixel(pixel_fmt))
 942                 stride = width * bytes_per_pixel(pixel_fmt);
 943
 944         if (stride % 4) {
 945                 printf("Stride %d not 32-bit aligned\n", stride);
 946                 return -EINVAL;
 947         }
 948         /* Build parameter memory data for DMA channel */
 949         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 950                            phyaddr_0, phyaddr_1);
 951
 952         if (ipu_is_dmfc_chan(dma_chan)) {
 953                 ipu_dmfc_set_wait4eot(dma_chan, width);
 954         }
 955
 956         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 957                 ipu_ch_param_set_high_priority(dma_chan);
 958
 959         ipu_ch_param_dump(dma_chan);
 960
 961         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 962         if (phyaddr_1)
 963                 reg |= idma_mask(dma_chan);
 964         else
 965                 reg &= ~idma_mask(dma_chan);
 966         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 967
 968         /* Reset to buffer 0 */
 969         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 970
 971         return 0;
 972 }
 973
 974 /*
 975  * This function enables a logical channel.
 976  *
 977  * @param       channel         Input parameter for the logical channel ID.
 978  *
 979  * @return      This function returns 0 on success or negative error code on
 980  *              fail.
 981  */
 982 int32_t ipu_enable_channel(ipu_channel_t channel)
 983 {
 984         uint32_t reg;
 985         uint32_t in_dma;
 986         uint32_t out_dma;
 987
 988         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
 989                 printf("Warning: channel already enabled %d\n",
 990                         IPU_CHAN_ID(channel));
 991         }
 992
 993         /* Get input and output dma channels */
 994         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 995         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 996
 997         if (idma_is_valid(in_dma)) {
 998                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
 999                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1000         }
1001         if (idma_is_valid(out_dma)) {
1002                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1003                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1004         }
1005
1006         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1007             (channel == MEM_FG_SYNC)) {
1008                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1009                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1010
1011                 ipu_dp_dc_enable(channel);
1012         }
1013
1014         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1015
1016         return 0;
1017 }
1018
1019 /*
1020  * This function clear buffer ready for a logical channel.
1021  *
1022  * @param       channel         Input parameter for the logical channel ID.
1023  *
1024  * @param       type            Input parameter which buffer to clear.
1025  *
1026  * @param       bufNum          Input parameter for which buffer number clear
1027  *                              ready state.
1028  *
1029  */
1030 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1031                 uint32_t bufNum)
1032 {
1033         uint32_t dma_ch = channel_2_dma(channel, type);
1034
1035         if (!idma_is_valid(dma_ch))
1036                 return;
1037
1038         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1039         if (bufNum == 0) {
1040                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1041                         __raw_writel(idma_mask(dma_ch),
1042                                         IPU_CHA_BUF0_RDY(dma_ch));
1043                 }
1044         } else {
1045                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1046                         __raw_writel(idma_mask(dma_ch),
1047                                         IPU_CHA_BUF1_RDY(dma_ch));
1048                 }
1049         }
1050         __raw_writel(0x0, IPU_GPR); /* write one to set */
1051 }
1052
1053 /*
1054  * This function disables a logical channel.
1055  *
1056  * @param       channel         Input parameter for the logical channel ID.
1057  *
1058  * @param       wait_for_stop   Flag to set whether to wait for channel end
1059  *                              of frame or return immediately.
1060  *
1061  * @return      This function returns 0 on success or negative error code on
1062  *              fail.
1063  */
1064 int32_t ipu_disable_channel(ipu_channel_t channel)
1065 {
1066         uint32_t reg;
1067         uint32_t in_dma;
1068         uint32_t out_dma;
1069
1070         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1071                 debug("Channel already disabled %d\n",
1072                         IPU_CHAN_ID(channel));
1073                 return 0;
1074         }
1075
1076         /* Get input and output dma channels */
1077         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1078         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1079
1080         if ((idma_is_valid(in_dma) &&
1081                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1082                 && (idma_is_valid(out_dma) &&
1083                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1084                 return -EINVAL;
1085
1086         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1087             (channel == MEM_DC_SYNC)) {
1088                 ipu_dp_dc_disable(channel, 0);
1089         }
1090
1091         /* Disable DMA channel(s) */
1092         if (idma_is_valid(in_dma)) {
1093                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1094                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1095                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1096         }
1097         if (idma_is_valid(out_dma)) {
1098                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1099                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1100                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1101         }
1102
1103         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1104
1105         /* Set channel buffers NOT to be ready */
1106         if (idma_is_valid(in_dma)) {
1107                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1108                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1109         }
1110         if (idma_is_valid(out_dma)) {
1111                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1112                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1113         }
1114
1115         return 0;
1116 }
1117
1118 uint32_t bytes_per_pixel(uint32_t fmt)
1119 {
1120         switch (fmt) {
1121         case IPU_PIX_FMT_GENERIC:       /* generic data */
1122         case IPU_PIX_FMT_RGB332:
1123         case IPU_PIX_FMT_YUV420P:
1124         case IPU_PIX_FMT_YUV422P:
1125                 return 1;
1126         case IPU_PIX_FMT_RGB565:
1127         case IPU_PIX_FMT_YUYV:
1128         case IPU_PIX_FMT_UYVY:
1129                 return 2;
1130         case IPU_PIX_FMT_BGR24:
1131         case IPU_PIX_FMT_RGB24:
1132                 return 3;
1133         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
1134         case IPU_PIX_FMT_BGR32:
1135         case IPU_PIX_FMT_BGRA32:
1136         case IPU_PIX_FMT_RGB32:
1137         case IPU_PIX_FMT_RGBA32:
1138         case IPU_PIX_FMT_ABGR32:
1139                 return 4;
1140         default:
1141                 return 1;
1142         }
1143         return 0;
1144 }
1145
1146 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1147 {
1148         switch (fmt) {
1149         case IPU_PIX_FMT_RGB666:
1150         case IPU_PIX_FMT_RGB565:
1151         case IPU_PIX_FMT_BGR24:
1152         case IPU_PIX_FMT_RGB24:
1153         case IPU_PIX_FMT_BGR32:
1154         case IPU_PIX_FMT_BGRA32:
1155         case IPU_PIX_FMT_RGB32:
1156         case IPU_PIX_FMT_RGBA32:
1157         case IPU_PIX_FMT_ABGR32:
1158         case IPU_PIX_FMT_LVDS666:
1159         case IPU_PIX_FMT_LVDS888:
1160                 return RGB;
1161
1162         default:
1163                 return YCbCr;
1164         }
1165         return RGB;
1166 }