drivers/video/mxsfb.c

   1 /*
   2  * Freescale i.MX23/i.MX28 LCDIF driver
   3  *
   4  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21 #include <common.h>
  22 #include <malloc.h>
  23 #include <video_fb.h>
  24
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/errno.h>
  29 #include <asm/io.h>
  30
  31 #include "videomodes.h"
  32
  33 #define PS2KHZ(ps)      (1000000000UL / (ps))
  34
  35 static GraphicDevice panel;
  36
  37 /*
  38  * DENX M28EVK:
  39  * setenv videomode
  40  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  41  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  42  *
  43  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  44  * setenv videomode
  45  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  46  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  47  */
  48
  49 static void mxs_lcd_init(GraphicDevice *panel,
  50                         struct ctfb_res_modes *mode, int bpp)
  51 {
  52         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  53         uint32_t word_len = 0, bus_width = 0;
  54         uint8_t valid_data = 0;
  55
  56         /* Kick in the LCDIF clock */
  57         mxs_set_lcdclk(PS2KHZ(mode->pixclock));
  58
  59         /* Restart the LCDIF block */
  60         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  61
  62         switch (bpp) {
  63         case 24:
  64                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  65                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  66                 valid_data = 0x7;
  67                 break;
  68         case 18:
  69                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  70                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  71                 valid_data = 0x7;
  72                 break;
  73         case 16:
  74                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  75                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  76                 valid_data = 0xf;
  77                 break;
  78         case 8:
  79                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  80                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  81                 valid_data = 0xf;
  82                 break;
  83         }
  84
  85         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  86                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  87                 &regs->hw_lcdif_ctrl);
  88
  89         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  90                 &regs->hw_lcdif_ctrl1);
  91         writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
  92                 &regs->hw_lcdif_transfer_count);
  93
  94         writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
  95                 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
  96                 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
  97                 mode->vsync_len, &regs->hw_lcdif_vdctrl0);
  98         writel(mode->upper_margin + mode->lower_margin +
  99                 mode->vsync_len + mode->yres,
 100                 &regs->hw_lcdif_vdctrl1);
 101         writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 102                 (mode->left_margin + mode->right_margin +
 103                 mode->hsync_len + mode->xres),
 104                 &regs->hw_lcdif_vdctrl2);
 105         writel(((mode->left_margin + mode->hsync_len) <<
 106                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 107                 (mode->upper_margin + mode->vsync_len),
 108                 &regs->hw_lcdif_vdctrl3);
 109         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
 110                 &regs->hw_lcdif_vdctrl4);
 111
 112         writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
 113         writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
 114
 115         /* Flush FIFO first */
 116         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 117
 118         /* Sync signals ON */
 119         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 120
 121         /* FIFO cleared */
 122         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 123
 124         /* RUN! */
 125         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 126 }
 127
 128 void *video_hw_init(void)
 129 {
 130         int bpp = -1;
 131         char *penv;
 132         void *fb;
 133         struct ctfb_res_modes mode;
 134
 135         puts("Video: ");
 136
 137         /* Suck display configuration from "videomode" variable */
 138         penv = getenv("videomode");
 139         if (!penv) {
 140                 puts("MXSFB: 'videomode' variable not set!\n");
 141                 return NULL;
 142         }
 143
 144         bpp = video_get_params(&mode, penv);
 145
 146         /* fill in Graphic device struct */
 147         sprintf(panel.modeIdent, "%dx%dx%d",
 148                         mode.xres, mode.yres, bpp);
 149
 150         panel.winSizeX = mode.xres;
 151         panel.winSizeY = mode.yres;
 152         panel.plnSizeX = mode.xres;
 153         panel.plnSizeY = mode.yres;
 154
 155         switch (bpp) {
 156         case 24:
 157         case 18:
 158                 panel.gdfBytesPP = 4;
 159                 panel.gdfIndex = GDF_32BIT_X888RGB;
 160                 break;
 161         case 16:
 162                 panel.gdfBytesPP = 2;
 163                 panel.gdfIndex = GDF_16BIT_565RGB;
 164                 break;
 165         case 8:
 166                 panel.gdfBytesPP = 1;
 167                 panel.gdfIndex = GDF__8BIT_INDEX;
 168                 break;
 169         default:
 170                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 171                 return NULL;
 172         }
 173
 174         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 175
 176         /* Allocate framebuffer */
 177         fb = malloc(panel.memSize);
 178         if (!fb) {
 179                 printf("MXSFB: Error allocating framebuffer!\n");
 180                 return NULL;
 181         }
 182
 183         /* Wipe framebuffer */
 184         memset(fb, 0, panel.memSize);
 185
 186         panel.frameAdrs = (u32)fb;
 187
 188         printf("%s\n", panel.modeIdent);
 189
 190         /* Start framebuffer */
 191         mxs_lcd_init(&panel, &mode, bpp);
 192
 193         return (void *)&panel;
 194 }