drivers/video/pxa_lcd.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38 #include <asm/io.h>
  39
  40 /* #define DEBUG */
  41
  42 #ifdef CONFIG_LCD
  43
  44 /*----------------------------------------------------------------------*/
  45 /*
  46  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  47  * your display.
  48  */
  49
  50 #ifdef CONFIG_PXA_VGA
  51 /* LCD outputs connected to a video DAC  */
  52 # define LCD_BPP        LCD_COLOR8
  53
  54 /* you have to set lccr0 and lccr3 (including pcd) */
  55 # define REG_LCCR0      0x003008f8
  56 # define REG_LCCR3      0x0300FF01
  57
  58 /* 640x480x16 @ 61 Hz */
  59 vidinfo_t panel_info = {
  60         .vl_col         = 640,
  61         .vl_row         = 480,
  62         .vl_width       = 640,
  63         .vl_height      = 480,
  64         .vl_clkp        = CONFIG_SYS_HIGH,
  65         .vl_oep         = CONFIG_SYS_HIGH,
  66         .vl_hsp         = CONFIG_SYS_HIGH,
  67         .vl_vsp         = CONFIG_SYS_HIGH,
  68         .vl_dp          = CONFIG_SYS_HIGH,
  69         .vl_bpix        = LCD_BPP,
  70         .vl_lbw         = 0,
  71         .vl_splt        = 0,
  72         .vl_clor        = 0,
  73         .vl_tft         = 1,
  74         .vl_hpw         = 40,
  75         .vl_blw         = 56,
  76         .vl_elw         = 56,
  77         .vl_vpw         = 20,
  78         .vl_bfw         = 8,
  79         .vl_efw         = 8,
  80 };
  81 #endif /* CONFIG_PXA_VIDEO */
  82
  83 /*----------------------------------------------------------------------*/
  84 #ifdef CONFIG_SHARP_LM8V31
  85
  86 # define LCD_BPP        LCD_COLOR8
  87 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  88
  89 /* you have to set lccr0 and lccr3 (including pcd) */
  90 # define REG_LCCR0      0x0030087C
  91 # define REG_LCCR3      0x0340FF08
  92
  93 vidinfo_t panel_info = {
  94         .vl_col         = 640,
  95         .vl_row         = 480,
  96         .vl_width       = 157,
  97         .vl_height      = 118,
  98         .vl_clkp        = CONFIG_SYS_HIGH,
  99         .vl_oep         = CONFIG_SYS_HIGH,
 100         .vl_hsp         = CONFIG_SYS_HIGH,
 101         .vl_vsp         = CONFIG_SYS_HIGH,
 102         .vl_dp          = CONFIG_SYS_HIGH,
 103         .vl_bpix        = LCD_BPP,
 104         .vl_lbw         = 0,
 105         .vl_splt        = 1,
 106         .vl_clor        = 1,
 107         .vl_tft         = 0,
 108         .vl_hpw         = 1,
 109         .vl_blw         = 3,
 110         .vl_elw         = 3,
 111         .vl_vpw         = 1,
 112         .vl_bfw         = 0,
 113         .vl_efw         = 0,
 114 };
 115 #endif /* CONFIG_SHARP_LM8V31 */
 116 /*----------------------------------------------------------------------*/
 117 #ifdef CONFIG_VOIPAC_LCD
 118
 119 # define LCD_BPP        LCD_COLOR8
 120 # define LCD_INVERT_COLORS
 121
 122 /* you have to set lccr0 and lccr3 (including pcd) */
 123 # define REG_LCCR0      0x043008f8
 124 # define REG_LCCR3      0x0340FF08
 125
 126 vidinfo_t panel_info = {
 127         .vl_col         = 640,
 128         .vl_row         = 480,
 129         .vl_width       = 157,
 130         .vl_height      = 118,
 131         .vl_clkp        = CONFIG_SYS_HIGH,
 132         .vl_oep         = CONFIG_SYS_HIGH,
 133         .vl_hsp         = CONFIG_SYS_HIGH,
 134         .vl_vsp         = CONFIG_SYS_HIGH,
 135         .vl_dp          = CONFIG_SYS_HIGH,
 136         .vl_bpix        = LCD_BPP,
 137         .vl_lbw         = 0,
 138         .vl_splt        = 1,
 139         .vl_clor        = 1,
 140         .vl_tft         = 1,
 141         .vl_hpw         = 32,
 142         .vl_blw         = 144,
 143         .vl_elw         = 32,
 144         .vl_vpw         = 2,
 145         .vl_bfw         = 13,
 146         .vl_efw         = 30,
 147 };
 148 #endif /* CONFIG_VOIPAC_LCD */
 149
 150 /*----------------------------------------------------------------------*/
 151 #ifdef CONFIG_HITACHI_SX14
 152 /* Hitachi SX14Q004-ZZA color STN LCD */
 153 #define LCD_BPP         LCD_COLOR8
 154
 155 /* you have to set lccr0 and lccr3 (including pcd) */
 156 #define REG_LCCR0       0x00301079
 157 #define REG_LCCR3       0x0340FF20
 158
 159 vidinfo_t panel_info = {
 160         .vl_col         = 320,
 161         .vl_row         = 240,
 162         .vl_width       = 167,
 163         .vl_height      = 109,
 164         .vl_clkp        = CONFIG_SYS_HIGH,
 165         .vl_oep         = CONFIG_SYS_HIGH,
 166         .vl_hsp         = CONFIG_SYS_HIGH,
 167         .vl_vsp         = CONFIG_SYS_HIGH,
 168         .vl_dp          = CONFIG_SYS_HIGH,
 169         .vl_bpix        = LCD_BPP,
 170         .vl_lbw         = 1,
 171         .vl_splt        = 0,
 172         .vl_clor        = 1,
 173         .vl_tft         = 0,
 174         .vl_hpw         = 1,
 175         .vl_blw         = 1,
 176         .vl_elw         = 1,
 177         .vl_vpw         = 7,
 178         .vl_bfw         = 0,
 179         .vl_efw         = 0,
 180 };
 181 #endif /* CONFIG_HITACHI_SX14 */
 182
 183 /*----------------------------------------------------------------------*/
 184 #ifdef CONFIG_LMS283GF05
 185
 186 # define LCD_BPP        LCD_COLOR8
 187 /*# define LCD_INVERT_COLORS*/
 188
 189 /* you have to set lccr0 and lccr3 (including pcd) */
 190 # define REG_LCCR0      0x043008f8
 191 # define REG_LCCR3      0x03b00009
 192
 193 vidinfo_t panel_info = {
 194         .vl_col         = 240,
 195         .vl_row         = 320,
 196         .vl_width       = 240,
 197         .vl_height      = 320,
 198         .vl_clkp        = CONFIG_SYS_HIGH,
 199         .vl_oep         = CONFIG_SYS_LOW,
 200         .vl_hsp         = CONFIG_SYS_LOW,
 201         .vl_vsp         = CONFIG_SYS_LOW,
 202         .vl_dp          = CONFIG_SYS_HIGH,
 203         .vl_bpix        = LCD_BPP,
 204         .vl_lbw         = 0,
 205         .vl_splt        = 1,
 206         .vl_clor        = 1,
 207         .vl_tft         = 1,
 208         .vl_hpw         = 4,
 209         .vl_blw         = 4,
 210         .vl_elw         = 8,
 211         .vl_vpw         = 4,
 212         .vl_bfw         = 4,
 213         .vl_efw         = 8,
 214 };
 215 #endif /* CONFIG_LMS283GF05 */
 216
 217 /*----------------------------------------------------------------------*/
 218
 219 #ifdef CONFIG_ACX517AKN
 220
 221 # define LCD_BPP        LCD_COLOR8
 222
 223 /* you have to set lccr0 and lccr3 (including pcd) */
 224 # define REG_LCCR0      0x003008f9
 225 # define REG_LCCR3      0x03700006
 226
 227 vidinfo_t panel_info = {
 228         .vl_col         = 320,
 229         .vl_row         = 320,
 230         .vl_width       = 320,
 231         .vl_height      = 320,
 232         .vl_clkp        = CONFIG_SYS_HIGH,
 233         .vl_oep         = CONFIG_SYS_LOW,
 234         .vl_hsp         = CONFIG_SYS_LOW,
 235         .vl_vsp         = CONFIG_SYS_LOW,
 236         .vl_dp          = CONFIG_SYS_HIGH,
 237         .vl_bpix        = LCD_BPP,
 238         .vl_lbw         = 0,
 239         .vl_splt        = 1,
 240         .vl_clor        = 1,
 241         .vl_tft         = 1,
 242         .vl_hpw         = 0x04,
 243         .vl_blw         = 0x1c,
 244         .vl_elw         = 0x08,
 245         .vl_vpw         = 0x01,
 246         .vl_bfw         = 0x07,
 247         .vl_efw         = 0x08,
 248 };
 249 #endif /* CONFIG_ACX517AKN */
 250
 251 /*----------------------------------------------------------------------*/
 252
 253 #ifdef CONFIG_LQ038J7DH53
 254
 255 # define LCD_BPP        LCD_COLOR8
 256
 257 /* you have to set lccr0 and lccr3 (including pcd) */
 258 # define REG_LCCR0      0x003008f9
 259 # define REG_LCCR3      0x03700004
 260
 261 vidinfo_t panel_info = {
 262         .vl_col         = 320,
 263         .vl_row         = 480,
 264         .vl_width       = 320,
 265         .vl_height      = 480,
 266         .vl_clkp        = CONFIG_SYS_HIGH,
 267         .vl_oep         = CONFIG_SYS_LOW,
 268         .vl_hsp         = CONFIG_SYS_LOW,
 269         .vl_vsp         = CONFIG_SYS_LOW,
 270         .vl_dp          = CONFIG_SYS_HIGH,
 271         .vl_bpix        = LCD_BPP,
 272         .vl_lbw         = 0,
 273         .vl_splt        = 1,
 274         .vl_clor        = 1,
 275         .vl_tft         = 1,
 276         .vl_hpw         = 0x04,
 277         .vl_blw         = 0x20,
 278         .vl_elw         = 0x01,
 279         .vl_vpw         = 0x01,
 280         .vl_bfw         = 0x04,
 281         .vl_efw         = 0x01,
 282 };
 283 #endif /* CONFIG_ACX517AKN */
 284
 285 /*----------------------------------------------------------------------*/
 286
 287 #ifdef CONFIG_LITTLETON_LCD
 288 # define LCD_BPP        LCD_COLOR8
 289
 290 /* you have to set lccr0 and lccr3 (including pcd) */
 291 # define REG_LCCR0      0x003008f8
 292 # define REG_LCCR3      0x0300FF04
 293
 294 vidinfo_t panel_info = {
 295         .vl_col         = 480,
 296         .vl_row         = 640,
 297         .vl_width       = 480,
 298         .vl_height      = 640,
 299         .vl_clkp        = CONFIG_SYS_HIGH,
 300         .vl_oep         = CONFIG_SYS_HIGH,
 301         .vl_hsp         = CONFIG_SYS_HIGH,
 302         .vl_vsp         = CONFIG_SYS_HIGH,
 303         .vl_dp          = CONFIG_SYS_HIGH,
 304         .vl_bpix        = LCD_BPP,
 305         .vl_lbw         = 0,
 306         .vl_splt        = 0,
 307         .vl_clor        = 0,
 308         .vl_tft         = 1,
 309         .vl_hpw         = 9,
 310         .vl_blw         = 8,
 311         .vl_elw         = 24,
 312         .vl_vpw         = 2,
 313         .vl_bfw         = 2,
 314         .vl_efw         = 4,
 315 };
 316 #endif /* CONFIG_LITTLETON_LCD */
 317
 318 /*----------------------------------------------------------------------*/
 319
 320 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 321 static void pxafb_setup_gpio (vidinfo_t *vid);
 322 static void pxafb_enable_controller (vidinfo_t *vid);
 323 static int pxafb_init (vidinfo_t *vid);
 324
 325 /************************************************************************/
 326 /* ---------------  PXA chipset specific functions  ------------------- */
 327 /************************************************************************/
 328
 329 void lcd_ctrl_init (void *lcdbase)
 330 {
 331         pxafb_init_mem(lcdbase, &panel_info);
 332         pxafb_init(&panel_info);
 333         pxafb_setup_gpio(&panel_info);
 334         pxafb_enable_controller(&panel_info);
 335 }
 336
 337 /*----------------------------------------------------------------------*/
 338 #if LCD_BPP == LCD_COLOR8
 339 void
 340 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 341 {
 342         struct pxafb_info *fbi = &panel_info.pxa;
 343         unsigned short *palette = (unsigned short *)fbi->palette;
 344         u_int val;
 345
 346         if (regno < fbi->palette_size) {
 347                 val = ((red << 8) & 0xf800);
 348                 val |= ((green << 4) & 0x07e0);
 349                 val |= (blue & 0x001f);
 350
 351 #ifdef LCD_INVERT_COLORS
 352                 palette[regno] = ~val;
 353 #else
 354                 palette[regno] = val;
 355 #endif
 356         }
 357
 358         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 359                 regno, &palette[regno],
 360                 red, green, blue,
 361                 palette[regno]);
 362 }
 363 #endif /* LCD_COLOR8 */
 364
 365 /*----------------------------------------------------------------------*/
 366 #if LCD_BPP == LCD_MONOCHROME
 367 void lcd_initcolregs (void)
 368 {
 369         struct pxafb_info *fbi = &panel_info.pxa;
 370         cmap = (ushort *)fbi->palette;
 371         ushort regno;
 372
 373         for (regno = 0; regno < 16; regno++) {
 374                 cmap[regno * 2] = 0;
 375                 cmap[(regno * 2) + 1] = regno & 0x0f;
 376         }
 377 }
 378 #endif /* LCD_MONOCHROME */
 379
 380 /*----------------------------------------------------------------------*/
 381 void lcd_enable (void)
 382 {
 383 }
 384
 385 /************************************************************************/
 386 /* ** PXA255 specific routines                                          */
 387 /************************************************************************/
 388
 389 /*
 390  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 391  * descriptors and palette areas.
 392  */
 393 ulong calc_fbsize (void)
 394 {
 395         ulong size;
 396         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 397
 398         size = line_length * panel_info.vl_row;
 399         size += PAGE_SIZE;
 400
 401         return size;
 402 }
 403
 404 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 405 {
 406         u_long palette_mem_size;
 407         struct pxafb_info *fbi = &vid->pxa;
 408         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 409
 410         fbi->screen = (u_long)lcdbase;
 411
 412         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 413         palette_mem_size = fbi->palette_size * sizeof(u16);
 414
 415         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 416         /* locate palette and descs at end of page following fb */
 417         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 418
 419         return 0;
 420 }
 421 #ifdef  CONFIG_CPU_MONAHANS
 422 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 423 #else
 424 static void pxafb_setup_gpio (vidinfo_t *vid)
 425 {
 426         u_long lccr0;
 427
 428         /*
 429          * setup is based on type of panel supported
 430          */
 431
 432         lccr0 = vid->pxa.reg_lccr0;
 433
 434         /* 4 bit interface */
 435         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 436         {
 437                 debug("Setting GPIO for 4 bit data\n");
 438                 /* bits 58-61 */
 439                 writel(readl(GPDR1) | (0xf << 26), GPDR1);
 440                 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
 441                         GAFR1_U);
 442
 443                 /* bits 74-77 */
 444                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 445                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 446                         GAFR2_L);
 447         }
 448
 449         /* 8 bit interface */
 450         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 451                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 452         {
 453                 debug("Setting GPIO for 8 bit data\n");
 454                 /* bits 58-65 */
 455                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 456                 writel(readl(GPDR2) | (0x3), GPDR2);
 457
 458                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 459                         GAFR1_U);
 460                 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 461
 462                 /* bits 74-77 */
 463                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 464                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 465                         GAFR2_L);
 466         }
 467
 468         /* 16 bit interface */
 469         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 470         {
 471                 debug("Setting GPIO for 16 bit data\n");
 472                 /* bits 58-77 */
 473                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 474                 writel(readl(GPDR2) | 0x00003fff, GPDR2);
 475
 476                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 477                         GAFR1_U);
 478                 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 479         }
 480         else
 481         {
 482                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 483         }
 484 }
 485 #endif
 486
 487 static void pxafb_enable_controller (vidinfo_t *vid)
 488 {
 489         debug("Enabling LCD controller\n");
 490
 491         /* Sequence from 11.7.10 */
 492         writel(vid->pxa.reg_lccr3, LCCR3);
 493         writel(vid->pxa.reg_lccr2, LCCR2);
 494         writel(vid->pxa.reg_lccr1, LCCR1);
 495         writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
 496         writel(vid->pxa.fdadr0, FDADR0);
 497         writel(vid->pxa.fdadr1, FDADR1);
 498         writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 499
 500 #ifdef  CONFIG_CPU_MONAHANS
 501         writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 502 #else
 503         writel(readl(CKEN) | CKEN16_LCD, CKEN);
 504 #endif
 505
 506         debug("FDADR0 = 0x%08x\n", readl(FDADR0));
 507         debug("FDADR1 = 0x%08x\n", readl(FDADR1));
 508         debug("LCCR0 = 0x%08x\n", readl(LCCR0));
 509         debug("LCCR1 = 0x%08x\n", readl(LCCR1));
 510         debug("LCCR2 = 0x%08x\n", readl(LCCR2));
 511         debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 512 }
 513
 514 static int pxafb_init (vidinfo_t *vid)
 515 {
 516         struct pxafb_info *fbi = &vid->pxa;
 517
 518         debug("Configuring PXA LCD\n");
 519
 520         fbi->reg_lccr0 = REG_LCCR0;
 521         fbi->reg_lccr3 = REG_LCCR3;
 522
 523         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 524                 vid->vl_col, vid->vl_hpw,
 525                 vid->vl_blw, vid->vl_elw);
 526         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 527                 vid->vl_row, vid->vl_vpw,
 528                 vid->vl_bfw, vid->vl_efw);
 529
 530         fbi->reg_lccr1 =
 531                 LCCR1_DisWdth(vid->vl_col) +
 532                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 533                 LCCR1_BegLnDel(vid->vl_blw) +
 534                 LCCR1_EndLnDel(vid->vl_elw);
 535
 536         fbi->reg_lccr2 =
 537                 LCCR2_DisHght(vid->vl_row) +
 538                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 539                 LCCR2_BegFrmDel(vid->vl_bfw) +
 540                 LCCR2_EndFrmDel(vid->vl_efw);
 541
 542         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 543         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 544                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 545
 546
 547         /* setup dma descriptors */
 548         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 549         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 550         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 551
 552         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 553                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 554                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 555
 556         /* populate descriptors */
 557         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 558         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 559         fbi->dmadesc_fblow->fidr  = 0;
 560         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 561
 562         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 563
 564         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 565         fbi->dmadesc_fbhigh->fidr = 0;
 566         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 567
 568         fbi->dmadesc_palette->fsadr = fbi->palette;
 569         fbi->dmadesc_palette->fidr  = 0;
 570         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 571
 572         if( NBITS(vid->vl_bpix) < 12)
 573         {
 574                 /* assume any mode with <12 bpp is palette driven */
 575                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 576                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 577                 /* flips back and forth between pal and fbhigh */
 578                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 579         }
 580         else
 581         {
 582                 /* palette shouldn't be loaded in true-color mode */
 583                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 584                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 585         }
 586
 587         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 588         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 589         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 590
 591         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 592         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 593         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 594
 595         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 596         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 597         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 598
 599         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 600         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 601         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 602
 603         return 0;
 604 }
 605
 606 /************************************************************************/
 607 /************************************************************************/
 608
 609 #endif /* CONFIG_LCD */