2 * Freescale CLKCTRL Register Definitions
4 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * This file is created by xml file. Don't Edit it.
23 * Template revision: 26195
26 #ifndef __ARCH_ARM___CLKCTRL_H
27 #define __ARCH_ARM___CLKCTRL_H
30 #define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
31 #define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
32 #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
33 #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
35 #define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
36 #define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
37 #define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
38 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
39 #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
40 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
41 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
42 (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
43 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
44 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
45 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
46 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
47 #define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
48 #define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
49 #define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
50 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
51 #define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
52 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
53 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
54 (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
55 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
56 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
57 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
58 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
59 #define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
60 #define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
61 #define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
62 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
63 #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
64 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
65 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
66 (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
67 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
68 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
69 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
70 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
71 #define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
72 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
73 #define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
74 #define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
75 #define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
76 #define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
77 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
79 #define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
81 #define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
82 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
83 #define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
84 #define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
85 #define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
86 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
87 #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
88 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
89 #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
90 (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
92 #define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
93 #define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
94 #define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
95 #define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
97 #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
98 #define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
99 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
100 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
101 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
102 (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
103 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
104 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
105 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
106 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
107 #define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
108 #define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
109 #define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
110 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
111 #define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
112 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
113 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
114 (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
115 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
116 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
117 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
118 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
119 #define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
120 #define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
121 #define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
122 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
123 #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
124 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
125 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
126 (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
127 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
128 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
129 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
130 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
131 #define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
132 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
133 #define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
134 #define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
135 #define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
136 #define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
137 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
139 #define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
141 #define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
142 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
143 #define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
144 #define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
145 #define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
146 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
147 #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
148 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
149 #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
150 (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
152 #define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
153 #define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
154 #define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
155 #define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
157 #define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
158 #define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
159 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
160 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
161 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
162 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
163 #define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
164 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
165 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
166 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
167 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
168 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
169 #define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
170 #define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
171 #define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
172 #define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
173 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
175 #define HW_CLKCTRL_CPU (0x00000050)
176 #define HW_CLKCTRL_CPU_SET (0x00000054)
177 #define HW_CLKCTRL_CPU_CLR (0x00000058)
178 #define HW_CLKCTRL_CPU_TOG (0x0000005c)
180 #define BP_CLKCTRL_CPU_RSRVD5 30
181 #define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
182 #define BF_CLKCTRL_CPU_RSRVD5(v) \
183 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
184 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
185 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
186 #define BM_CLKCTRL_CPU_RSRVD4 0x08000000
187 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
188 #define BP_CLKCTRL_CPU_DIV_XTAL 16
189 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
190 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \
191 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
192 #define BP_CLKCTRL_CPU_RSRVD3 13
193 #define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
194 #define BF_CLKCTRL_CPU_RSRVD3(v) \
195 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
196 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
197 #define BM_CLKCTRL_CPU_RSRVD2 0x00000800
198 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
199 #define BP_CLKCTRL_CPU_RSRVD1 6
200 #define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
201 #define BF_CLKCTRL_CPU_RSRVD1(v) \
202 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
203 #define BP_CLKCTRL_CPU_DIV_CPU 0
204 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
205 #define BF_CLKCTRL_CPU_DIV_CPU(v) \
206 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
208 #define HW_CLKCTRL_HBUS (0x00000060)
209 #define HW_CLKCTRL_HBUS_SET (0x00000064)
210 #define HW_CLKCTRL_HBUS_CLR (0x00000068)
211 #define HW_CLKCTRL_HBUS_TOG (0x0000006c)
213 #define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
214 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
215 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
216 #define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
217 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
218 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
219 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
220 #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
221 #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
222 #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
223 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
224 #define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
225 #define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
226 #define BP_CLKCTRL_HBUS_SLOW_DIV 16
227 #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
228 #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
229 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
230 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
231 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
232 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
233 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
234 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
235 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
236 #define BP_CLKCTRL_HBUS_RSRVD1 6
237 #define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
238 #define BF_CLKCTRL_HBUS_RSRVD1(v) \
239 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
240 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
241 #define BP_CLKCTRL_HBUS_DIV 0
242 #define BM_CLKCTRL_HBUS_DIV 0x0000001F
243 #define BF_CLKCTRL_HBUS_DIV(v) \
244 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
246 #define HW_CLKCTRL_XBUS (0x00000070)
248 #define BM_CLKCTRL_XBUS_BUSY 0x80000000
249 #define BP_CLKCTRL_XBUS_RSRVD1 12
250 #define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
251 #define BF_CLKCTRL_XBUS_RSRVD1(v) \
252 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
253 #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
254 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
255 #define BP_CLKCTRL_XBUS_DIV 0
256 #define BM_CLKCTRL_XBUS_DIV 0x000003FF
257 #define BF_CLKCTRL_XBUS_DIV(v) \
258 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
260 #define HW_CLKCTRL_XTAL (0x00000080)
261 #define HW_CLKCTRL_XTAL_SET (0x00000084)
262 #define HW_CLKCTRL_XTAL_CLR (0x00000088)
263 #define HW_CLKCTRL_XTAL_TOG (0x0000008c)
265 #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266 #define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
268 #define BP_CLKCTRL_XTAL_RSRVD2 27
269 #define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
270 #define BF_CLKCTRL_XTAL_RSRVD2(v) \
271 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
272 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
273 #define BP_CLKCTRL_XTAL_RSRVD1 2
274 #define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
275 #define BF_CLKCTRL_XTAL_RSRVD1(v) \
276 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
277 #define BP_CLKCTRL_XTAL_DIV_UART 0
278 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
279 #define BF_CLKCTRL_XTAL_DIV_UART(v) \
280 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
282 #define HW_CLKCTRL_SSP0 (0x00000090)
284 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
285 #define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
286 #define BM_CLKCTRL_SSP0_BUSY 0x20000000
287 #define BP_CLKCTRL_SSP0_RSRVD1 10
288 #define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
289 #define BF_CLKCTRL_SSP0_RSRVD1(v) \
290 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
291 #define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
292 #define BP_CLKCTRL_SSP0_DIV 0
293 #define BM_CLKCTRL_SSP0_DIV 0x000001FF
294 #define BF_CLKCTRL_SSP0_DIV(v) \
295 (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
297 #define HW_CLKCTRL_SSP1 (0x000000a0)
299 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
300 #define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
301 #define BM_CLKCTRL_SSP1_BUSY 0x20000000
302 #define BP_CLKCTRL_SSP1_RSRVD1 10
303 #define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
304 #define BF_CLKCTRL_SSP1_RSRVD1(v) \
305 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
306 #define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
307 #define BP_CLKCTRL_SSP1_DIV 0
308 #define BM_CLKCTRL_SSP1_DIV 0x000001FF
309 #define BF_CLKCTRL_SSP1_DIV(v) \
310 (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
312 #define HW_CLKCTRL_SSP2 (0x000000b0)
314 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
315 #define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
316 #define BM_CLKCTRL_SSP2_BUSY 0x20000000
317 #define BP_CLKCTRL_SSP2_RSRVD1 10
318 #define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
319 #define BF_CLKCTRL_SSP2_RSRVD1(v) \
320 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
321 #define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
322 #define BP_CLKCTRL_SSP2_DIV 0
323 #define BM_CLKCTRL_SSP2_DIV 0x000001FF
324 #define BF_CLKCTRL_SSP2_DIV(v) \
325 (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
327 #define HW_CLKCTRL_SSP3 (0x000000c0)
329 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
330 #define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
331 #define BM_CLKCTRL_SSP3_BUSY 0x20000000
332 #define BP_CLKCTRL_SSP3_RSRVD1 10
333 #define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
334 #define BF_CLKCTRL_SSP3_RSRVD1(v) \
335 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
336 #define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
337 #define BP_CLKCTRL_SSP3_DIV 0
338 #define BM_CLKCTRL_SSP3_DIV 0x000001FF
339 #define BF_CLKCTRL_SSP3_DIV(v) \
340 (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
342 #define HW_CLKCTRL_GPMI (0x000000d0)
344 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
345 #define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
346 #define BM_CLKCTRL_GPMI_BUSY 0x20000000
347 #define BP_CLKCTRL_GPMI_RSRVD1 11
348 #define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
349 #define BF_CLKCTRL_GPMI_RSRVD1(v) \
350 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
351 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
352 #define BP_CLKCTRL_GPMI_DIV 0
353 #define BM_CLKCTRL_GPMI_DIV 0x000003FF
354 #define BF_CLKCTRL_GPMI_DIV(v) \
355 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
357 #define HW_CLKCTRL_SPDIF (0x000000e0)
359 #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
360 #define BP_CLKCTRL_SPDIF_RSRVD 0
361 #define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
362 #define BF_CLKCTRL_SPDIF_RSRVD(v) \
363 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
365 #define HW_CLKCTRL_EMI (0x000000f0)
367 #define BM_CLKCTRL_EMI_CLKGATE 0x80000000
368 #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
369 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
370 #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
371 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
372 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
373 #define BP_CLKCTRL_EMI_RSRVD3 18
374 #define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
375 #define BF_CLKCTRL_EMI_RSRVD3(v) \
376 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
377 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
378 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
379 #define BP_CLKCTRL_EMI_RSRVD2 12
380 #define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
381 #define BF_CLKCTRL_EMI_RSRVD2(v) \
382 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
383 #define BP_CLKCTRL_EMI_DIV_XTAL 8
384 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
385 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \
386 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
387 #define BP_CLKCTRL_EMI_RSRVD1 6
388 #define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
389 #define BF_CLKCTRL_EMI_RSRVD1(v) \
390 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
391 #define BP_CLKCTRL_EMI_DIV_EMI 0
392 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
393 #define BF_CLKCTRL_EMI_DIV_EMI(v) \
394 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
396 #define HW_CLKCTRL_SAIF0 (0x00000100)
398 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
399 #define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
400 #define BM_CLKCTRL_SAIF0_BUSY 0x20000000
401 #define BP_CLKCTRL_SAIF0_RSRVD1 17
402 #define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
403 #define BF_CLKCTRL_SAIF0_RSRVD1(v) \
404 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
405 #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
406 #define BP_CLKCTRL_SAIF0_DIV 0
407 #define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
408 #define BF_CLKCTRL_SAIF0_DIV(v) \
409 (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
411 #define HW_CLKCTRL_SAIF1 (0x00000110)
413 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
414 #define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
415 #define BM_CLKCTRL_SAIF1_BUSY 0x20000000
416 #define BP_CLKCTRL_SAIF1_RSRVD1 17
417 #define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
418 #define BF_CLKCTRL_SAIF1_RSRVD1(v) \
419 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
420 #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
421 #define BP_CLKCTRL_SAIF1_DIV 0
422 #define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
423 #define BF_CLKCTRL_SAIF1_DIV(v) \
424 (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
426 #define HW_CLKCTRL_DIS_LCDIF (0x00000120)
428 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
429 #define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
430 #define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
431 #define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
432 #define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
433 #define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
434 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
435 #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
436 #define BP_CLKCTRL_DIS_LCDIF_DIV 0
437 #define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
438 #define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
439 (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
441 #define HW_CLKCTRL_ETM (0x00000130)
443 #define BM_CLKCTRL_ETM_CLKGATE 0x80000000
444 #define BM_CLKCTRL_ETM_RSRVD2 0x40000000
445 #define BM_CLKCTRL_ETM_BUSY 0x20000000
446 #define BP_CLKCTRL_ETM_RSRVD1 8
447 #define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
448 #define BF_CLKCTRL_ETM_RSRVD1(v) \
449 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
450 #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
451 #define BP_CLKCTRL_ETM_DIV 0
452 #define BM_CLKCTRL_ETM_DIV 0x0000007F
453 #define BF_CLKCTRL_ETM_DIV(v) \
454 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
456 #define HW_CLKCTRL_ENET (0x00000140)
458 #define BM_CLKCTRL_ENET_SLEEP 0x80000000
459 #define BM_CLKCTRL_ENET_DISABLE 0x40000000
460 #define BM_CLKCTRL_ENET_STATUS 0x20000000
461 #define BM_CLKCTRL_ENET_RSRVD1 0x10000000
462 #define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
463 #define BP_CLKCTRL_ENET_DIV_TIME 21
464 #define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
465 #define BF_CLKCTRL_ENET_DIV_TIME(v) \
466 (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
467 #define BP_CLKCTRL_ENET_TIME_SEL 19
468 #define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
469 #define BF_CLKCTRL_ENET_TIME_SEL(v) \
470 (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
471 #define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
472 #define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
473 #define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
474 #define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
475 #define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
476 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
477 #define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
478 #define BP_CLKCTRL_ENET_RSRVD0 0
479 #define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
480 #define BF_CLKCTRL_ENET_RSRVD0(v) \
481 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
483 #define HW_CLKCTRL_HSADC (0x00000150)
485 #define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
486 #define BM_CLKCTRL_HSADC_RESETB 0x40000000
487 #define BP_CLKCTRL_HSADC_FREQDIV 28
488 #define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
489 #define BF_CLKCTRL_HSADC_FREQDIV(v) \
490 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
491 #define BP_CLKCTRL_HSADC_RSRVD1 0
492 #define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
493 #define BF_CLKCTRL_HSADC_RSRVD1(v) \
494 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
496 #define HW_CLKCTRL_FLEXCAN (0x00000160)
498 #define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
499 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
500 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
501 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
502 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
503 #define BP_CLKCTRL_FLEXCAN_RSRVD1 0
504 #define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
505 #define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
506 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
508 #define HW_CLKCTRL_FRAC0 (0x000001b0)
509 #define HW_CLKCTRL_FRAC0_SET (0x000001b4)
510 #define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
511 #define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
513 #define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
514 #define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
515 #define BP_CLKCTRL_FRAC0_IO0FRAC 24
516 #define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
517 #define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
518 (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
519 #define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
520 #define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
521 #define BP_CLKCTRL_FRAC0_IO1FRAC 16
522 #define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
523 #define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
524 (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
525 #define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
526 #define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
527 #define BP_CLKCTRL_FRAC0_EMIFRAC 8
528 #define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
529 #define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
530 (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
531 #define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
532 #define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
533 #define BP_CLKCTRL_FRAC0_CPUFRAC 0
534 #define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
535 #define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
536 (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
538 #define HW_CLKCTRL_FRAC1 (0x000001c0)
539 #define HW_CLKCTRL_FRAC1_SET (0x000001c4)
540 #define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
541 #define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
543 #define BP_CLKCTRL_FRAC1_RSRVD2 24
544 #define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
545 #define BF_CLKCTRL_FRAC1_RSRVD2(v) \
546 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
547 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
548 #define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
549 #define BP_CLKCTRL_FRAC1_GPMIFRAC 16
550 #define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
551 #define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
552 (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
553 #define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
554 #define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
555 #define BP_CLKCTRL_FRAC1_HSADCFRAC 8
556 #define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
557 #define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
558 (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
559 #define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
560 #define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
561 #define BP_CLKCTRL_FRAC1_PIXFRAC 0
562 #define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
563 #define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
564 (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
566 #define HW_CLKCTRL_CLKSEQ (0x000001d0)
567 #define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
568 #define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
569 #define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
571 #define BP_CLKCTRL_CLKSEQ_RSRVD0 19
572 #define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
573 #define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
574 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
575 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
576 #define BP_CLKCTRL_CLKSEQ_RSRVD1 15
577 #define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
578 #define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
579 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
580 #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
581 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
582 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
583 #define BP_CLKCTRL_CLKSEQ_RSRVD2 9
584 #define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
585 #define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
586 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
587 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
588 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
589 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
590 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
591 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
592 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
593 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
594 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
595 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
597 #define HW_CLKCTRL_RESET (0x000001e0)
599 #define BP_CLKCTRL_RESET_RSRVD 6
600 #define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
601 #define BF_CLKCTRL_RESET_RSRVD(v) \
602 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
603 #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
604 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
605 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
606 #define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
607 #define BM_CLKCTRL_RESET_CHIP 0x00000002
608 #define BM_CLKCTRL_RESET_DIG 0x00000001
610 #define HW_CLKCTRL_STATUS (0x000001f0)
612 #define BP_CLKCTRL_STATUS_CPU_LIMIT 30
613 #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
614 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
615 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
616 #define BP_CLKCTRL_STATUS_RSRVD 0
617 #define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
618 #define BF_CLKCTRL_STATUS_RSRVD(v) \
619 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
621 #define HW_CLKCTRL_VERSION (0x00000200)
623 #define BP_CLKCTRL_VERSION_MAJOR 24
624 #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
625 #define BF_CLKCTRL_VERSION_MAJOR(v) \
626 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
627 #define BP_CLKCTRL_VERSION_MINOR 16
628 #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
629 #define BF_CLKCTRL_VERSION_MINOR(v) \
630 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
631 #define BP_CLKCTRL_VERSION_STEP 0
632 #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
633 #define BF_CLKCTRL_VERSION_STEP(v) \
634 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
635 #endif /* __ARCH_ARM___CLKCTRL_H */