include/asm-arm/arch-mx28/regs-timrot.h

   1 /*
   2  * Freescale TIMROT Register Definitions
   3  *
   4  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  * This file is created by xml file. Don't Edit it.
  21  *
  22  * Xml Revision: 1.40
  23  * Template revision: 26195
  24  */
  25
  26 #ifndef __ARCH_ARM___TIMROT_H
  27 #define __ARCH_ARM___TIMROT_H
  28
  29
  30 #define HW_TIMROT_ROTCTRL       (0x00000000)
  31 #define HW_TIMROT_ROTCTRL_SET   (0x00000004)
  32 #define HW_TIMROT_ROTCTRL_CLR   (0x00000008)
  33 #define HW_TIMROT_ROTCTRL_TOG   (0x0000000c)
  34
  35 #define BM_TIMROT_ROTCTRL_SFTRST        0x80000000
  36 #define BM_TIMROT_ROTCTRL_CLKGATE       0x40000000
  37 #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
  38 #define BM_TIMROT_ROTCTRL_TIM3_PRESENT  0x10000000
  39 #define BM_TIMROT_ROTCTRL_TIM2_PRESENT  0x08000000
  40 #define BM_TIMROT_ROTCTRL_TIM1_PRESENT  0x04000000
  41 #define BM_TIMROT_ROTCTRL_TIM0_PRESENT  0x02000000
  42 #define BP_TIMROT_ROTCTRL_STATE 22
  43 #define BM_TIMROT_ROTCTRL_STATE 0x01C00000
  44 #define BF_TIMROT_ROTCTRL_STATE(v)  \
  45                 (((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
  46 #define BP_TIMROT_ROTCTRL_DIVIDER       16
  47 #define BM_TIMROT_ROTCTRL_DIVIDER       0x003F0000
  48 #define BF_TIMROT_ROTCTRL_DIVIDER(v)  \
  49                 (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
  50 #define BP_TIMROT_ROTCTRL_RSRVD3        13
  51 #define BM_TIMROT_ROTCTRL_RSRVD3        0x0000E000
  52 #define BF_TIMROT_ROTCTRL_RSRVD3(v)  \
  53                 (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3)
  54 #define BM_TIMROT_ROTCTRL_RELATIVE      0x00001000
  55 #define BP_TIMROT_ROTCTRL_OVERSAMPLE    10
  56 #define BM_TIMROT_ROTCTRL_OVERSAMPLE    0x00000C00
  57 #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)  \
  58                 (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
  59 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
  60 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
  61 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
  62 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
  63 #define BM_TIMROT_ROTCTRL_POLARITY_B    0x00000200
  64 #define BM_TIMROT_ROTCTRL_POLARITY_A    0x00000100
  65 #define BP_TIMROT_ROTCTRL_SELECT_B      4
  66 #define BM_TIMROT_ROTCTRL_SELECT_B      0x000000F0
  67 #define BF_TIMROT_ROTCTRL_SELECT_B(v)  \
  68                 (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
  69 #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
  70 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0       0x1
  71 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1       0x2
  72 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2       0x3
  73 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3       0x4
  74 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4       0x5
  75 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM5       0x6
  76 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM6       0x7
  77 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM7       0x8
  78 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA    0x9
  79 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB    0xA
  80 #define BP_TIMROT_ROTCTRL_SELECT_A      0
  81 #define BM_TIMROT_ROTCTRL_SELECT_A      0x0000000F
  82 #define BF_TIMROT_ROTCTRL_SELECT_A(v)  \
  83                 (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
  84 #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
  85 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0       0x1
  86 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1       0x2
  87 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2       0x3
  88 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3       0x4
  89 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4       0x5
  90 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM5       0x6
  91 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM6       0x7
  92 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM7       0x8
  93 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA    0x9
  94 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB    0xA
  95
  96 #define HW_TIMROT_ROTCOUNT      (0x00000010)
  97
  98 #define BP_TIMROT_ROTCOUNT_RSRVD1       16
  99 #define BM_TIMROT_ROTCOUNT_RSRVD1       0xFFFF0000
 100 #define BF_TIMROT_ROTCOUNT_RSRVD1(v) \
 101                 (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1)
 102 #define BP_TIMROT_ROTCOUNT_UPDOWN       0
 103 #define BM_TIMROT_ROTCOUNT_UPDOWN       0x0000FFFF
 104 #define BF_TIMROT_ROTCOUNT_UPDOWN(v)  \
 105                 (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
 106
 107 /*
 108  *  multi-register-define name HW_TIMROT_TIMCTRLn
 109  *              base 0x00000020
 110  *              count 3
 111  *              offset 0x40
 112  */
 113 #define HW_TIMROT_TIMCTRLn(n)   (0x00000020 + (n) * 0x40)
 114 #define HW_TIMROT_TIMCTRLn_SET(n)       (0x00000024 + (n) * 0x40)
 115 #define HW_TIMROT_TIMCTRLn_CLR(n)       (0x00000028 + (n) * 0x40)
 116 #define HW_TIMROT_TIMCTRLn_TOG(n)       (0x0000002c + (n) * 0x40)
 117 #define BP_TIMROT_TIMCTRLn_RSRVD3       16
 118 #define BM_TIMROT_TIMCTRLn_RSRVD3       0xFFFF0000
 119 #define BF_TIMROT_TIMCTRLn_RSRVD3(v) \
 120                 (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3)
 121 #define BM_TIMROT_TIMCTRLn_IRQ  0x00008000
 122 #define BM_TIMROT_TIMCTRLn_IRQ_EN       0x00004000
 123 #define BP_TIMROT_TIMCTRLn_RSRVD2       12
 124 #define BM_TIMROT_TIMCTRLn_RSRVD2       0x00003000
 125 #define BF_TIMROT_TIMCTRLn_RSRVD2(v)  \
 126                 (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2)
 127 #define BM_TIMROT_TIMCTRLn_MATCH_MODE   0x00000800
 128 #define BP_TIMROT_TIMCTRLn_RSRVD1       9
 129 #define BM_TIMROT_TIMCTRLn_RSRVD1       0x00000600
 130 #define BF_TIMROT_TIMCTRLn_RSRVD1(v)  \
 131                 (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1)
 132 #define BM_TIMROT_TIMCTRLn_POLARITY     0x00000100
 133 #define BM_TIMROT_TIMCTRLn_UPDATE       0x00000080
 134 #define BM_TIMROT_TIMCTRLn_RELOAD       0x00000040
 135 #define BP_TIMROT_TIMCTRLn_PRESCALE     4
 136 #define BM_TIMROT_TIMCTRLn_PRESCALE     0x00000030
 137 #define BF_TIMROT_TIMCTRLn_PRESCALE(v)  \
 138                 (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
 139 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
 140 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
 141 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
 142 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
 143 #define BP_TIMROT_TIMCTRLn_SELECT       0
 144 #define BM_TIMROT_TIMCTRLn_SELECT       0x0000000F
 145 #define BF_TIMROT_TIMCTRLn_SELECT(v)  \
 146                 (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
 147 #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK  0x0
 148 #define BV_TIMROT_TIMCTRLn_SELECT__PWM0        0x1
 149 #define BV_TIMROT_TIMCTRLn_SELECT__PWM1        0x2
 150 #define BV_TIMROT_TIMCTRLn_SELECT__PWM2        0x3
 151 #define BV_TIMROT_TIMCTRLn_SELECT__PWM3        0x4
 152 #define BV_TIMROT_TIMCTRLn_SELECT__PWM4        0x5
 153 #define BV_TIMROT_TIMCTRLn_SELECT__PWM5        0x6
 154 #define BV_TIMROT_TIMCTRLn_SELECT__PWM6        0x7
 155 #define BV_TIMROT_TIMCTRLn_SELECT__PWM7        0x8
 156 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA     0x9
 157 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB     0xA
 158 #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL  0xB
 159 #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL   0xC
 160 #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL   0xD
 161 #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL   0xE
 162 #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF
 163
 164 /*
 165  *  multi-register-define name HW_TIMROT_RUNNING_COUNTn
 166  *              base 0x00000030
 167  *              count 3
 168  *              offset 0x40
 169  */
 170 #define HW_TIMROT_RUNNING_COUNTn(n)     (0x00000030 + (n) * 0x40)
 171 #define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT  0
 172 #define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT  0xFFFFFFFF
 173 #define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v)       (v)
 174
 175 /*
 176  *  multi-register-define name HW_TIMROT_FIXED_COUNTn
 177  *              base 0x00000040
 178  *              count 3
 179  *              offset 0x40
 180  */
 181 #define HW_TIMROT_FIXED_COUNTn(n)       (0x00000040 + (n) * 0x40)
 182 #define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT      0
 183 #define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT      0xFFFFFFFF
 184 #define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v)   (v)
 185
 186 /*
 187  *  multi-register-define name HW_TIMROT_MATCH_COUNTn
 188  *              base 0x00000050
 189  *              count 4
 190  *              offset 0x40
 191  */
 192 #define HW_TIMROT_MATCH_COUNTn(n)       (0x00000050 + (n) * 0x40)
 193 #define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT      0
 194 #define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT      0xFFFFFFFF
 195 #define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v)   (v)
 196
 197 #define HW_TIMROT_TIMCTRL3      (0x000000e0)
 198 #define HW_TIMROT_TIMCTRL3_SET  (0x000000e4)
 199 #define HW_TIMROT_TIMCTRL3_CLR  (0x000000e8)
 200 #define HW_TIMROT_TIMCTRL3_TOG  (0x000000ec)
 201
 202 #define BP_TIMROT_TIMCTRL3_RSRVD2       20
 203 #define BM_TIMROT_TIMCTRL3_RSRVD2       0xFFF00000
 204 #define BF_TIMROT_TIMCTRL3_RSRVD2(v) \
 205                 (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2)
 206 #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL  16
 207 #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL  0x000F0000
 208 #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)  \
 209                 (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
 210 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
 211 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
 212 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
 213 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
 214 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
 215 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
 216 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5        0x6
 217 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6        0x7
 218 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7        0x8
 219 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x9
 220 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0xA
 221 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0xB
 222 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0xC
 223 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xD
 224 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xE
 225 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF
 226 #define BM_TIMROT_TIMCTRL3_IRQ  0x00008000
 227 #define BM_TIMROT_TIMCTRL3_IRQ_EN       0x00004000
 228 #define BP_TIMROT_TIMCTRL3_RSRVD1       12
 229 #define BM_TIMROT_TIMCTRL3_RSRVD1       0x00003000
 230 #define BF_TIMROT_TIMCTRL3_RSRVD1(v)  \
 231                 (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1)
 232 #define BM_TIMROT_TIMCTRL3_MATCH_MODE   0x00000800
 233 #define BM_TIMROT_TIMCTRL3_DUTY_VALID   0x00000400
 234 #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE   0x00000200
 235 #define BM_TIMROT_TIMCTRL3_POLARITY     0x00000100
 236 #define BM_TIMROT_TIMCTRL3_UPDATE       0x00000080
 237 #define BM_TIMROT_TIMCTRL3_RELOAD       0x00000040
 238 #define BP_TIMROT_TIMCTRL3_PRESCALE     4
 239 #define BM_TIMROT_TIMCTRL3_PRESCALE     0x00000030
 240 #define BF_TIMROT_TIMCTRL3_PRESCALE(v)  \
 241                 (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
 242 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
 243 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
 244 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
 245 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
 246 #define BP_TIMROT_TIMCTRL3_SELECT       0
 247 #define BM_TIMROT_TIMCTRL3_SELECT       0x0000000F
 248 #define BF_TIMROT_TIMCTRL3_SELECT(v)  \
 249                 (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
 250 #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK  0x0
 251 #define BV_TIMROT_TIMCTRL3_SELECT__PWM0        0x1
 252 #define BV_TIMROT_TIMCTRL3_SELECT__PWM1        0x2
 253 #define BV_TIMROT_TIMCTRL3_SELECT__PWM2        0x3
 254 #define BV_TIMROT_TIMCTRL3_SELECT__PWM3        0x4
 255 #define BV_TIMROT_TIMCTRL3_SELECT__PWM4        0x5
 256 #define BV_TIMROT_TIMCTRL3_SELECT__PWM5        0x6
 257 #define BV_TIMROT_TIMCTRL3_SELECT__PWM6        0x7
 258 #define BV_TIMROT_TIMCTRL3_SELECT__PWM7        0x8
 259 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA     0x9
 260 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB     0xA
 261 #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL  0xB
 262 #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL   0xC
 263 #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL   0xD
 264 #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL   0xE
 265 #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF
 266
 267 #define HW_TIMROT_RUNNING_COUNT3        (0x000000f0)
 268
 269 #define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT      0
 270 #define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT      0xFFFFFFFF
 271 #define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v)   (v)
 272
 273 #define HW_TIMROT_FIXED_COUNT3  (0x00000100)
 274
 275 #define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0
 276 #define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF
 277 #define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v)      (v)
 278
 279 #define HW_TIMROT_VERSION       (0x00000120)
 280
 281 #define BP_TIMROT_VERSION_MAJOR 24
 282 #define BM_TIMROT_VERSION_MAJOR 0xFF000000
 283 #define BF_TIMROT_VERSION_MAJOR(v) \
 284                 (((v) << 24) & BM_TIMROT_VERSION_MAJOR)
 285 #define BP_TIMROT_VERSION_MINOR 16
 286 #define BM_TIMROT_VERSION_MINOR 0x00FF0000
 287 #define BF_TIMROT_VERSION_MINOR(v)  \
 288                 (((v) << 16) & BM_TIMROT_VERSION_MINOR)
 289 #define BP_TIMROT_VERSION_STEP  0
 290 #define BM_TIMROT_VERSION_STEP  0x0000FFFF
 291 #define BF_TIMROT_VERSION_STEP(v)  \
 292                 (((v) << 0) & BM_TIMROT_VERSION_STEP)
 293 #endif /* __ARCH_ARM___TIMROT_H */