include/asm-arm/arch-mx51/iomux.h

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13 #ifndef __MACH_MX51_IOMUX_H__
  14 #define __MACH_MX51_IOMUX_H__
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/mx51.h>
  19 #include <asm/arch/mx51_pins.h>
  20
  21 /*!
  22  * @file iomux.h
  23  *
  24  * @brief I/O Muxing control definitions and functions
  25  *
  26  * @ingroup GPIO_MX51
  27  */
  28
  29 typedef unsigned int iomux_pin_name_t;
  30
  31 /*!
  32  * various IOMUX output functions
  33  */
  34 typedef enum iomux_config {
  35         IOMUX_CONFIG_ALT0,      /*!< used as alternate function 0 */
  36         IOMUX_CONFIG_ALT1,      /*!< used as alternate function 1 */
  37         IOMUX_CONFIG_ALT2,      /*!< used as alternate function 2 */
  38         IOMUX_CONFIG_ALT3,      /*!< used as alternate function 3 */
  39         IOMUX_CONFIG_ALT4,      /*!< used as alternate function 4 */
  40         IOMUX_CONFIG_ALT5,      /*!< used as alternate function 5 */
  41         IOMUX_CONFIG_ALT6,      /*!< used as alternate function 6 */
  42         IOMUX_CONFIG_ALT7,      /*!< used as alternate function 7 */
  43         IOMUX_CONFIG_GPIO,      /*!< added to help user use GPIO mode */
  44         IOMUX_CONFIG_SION = 0x1 << 4,   /*!< used as LOOPBACK:MUX SION bit */
  45 } iomux_pin_cfg_t;
  46
  47 /*!
  48  * various IOMUX pad functions
  49  */
  50 typedef enum iomux_pad_config {
  51         PAD_CTL_SRE_SLOW = 0x0 << 0,
  52         PAD_CTL_SRE_FAST = 0x1 << 0,
  53         PAD_CTL_DRV_LOW = 0x0 << 1,
  54         PAD_CTL_DRV_MEDIUM = 0x1 << 1,
  55         PAD_CTL_DRV_HIGH = 0x2 << 1,
  56         PAD_CTL_DRV_MAX = 0x3 << 1,
  57         PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
  58         PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
  59         PAD_CTL_100K_PD = 0x0 << 4,
  60         PAD_CTL_47K_PU = 0x1 << 4,
  61         PAD_CTL_100K_PU = 0x2 << 4,
  62         PAD_CTL_22K_PU = 0x3 << 4,
  63         PAD_CTL_PUE_KEEPER = 0x0 << 6,
  64         PAD_CTL_PUE_PULL = 0x1 << 6,
  65         PAD_CTL_PKE_NONE = 0x0 << 7,
  66         PAD_CTL_PKE_ENABLE = 0x1 << 7,
  67         PAD_CTL_HYS_NONE = 0x0 << 8,
  68         PAD_CTL_HYS_ENABLE = 0x1 << 8,
  69         PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
  70         PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
  71         PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
  72         PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
  73 } iomux_pad_config_t;
  74
  75 /*!
  76  * various IOMUX input select register index
  77  */
  78 typedef enum iomux_input_select {
  79         MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
  80         MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
  81         MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
  82         MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
  83         MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
  84         MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
  85         MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
  86         MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
  87         MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
  88         MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
  89         MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
  90         MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
  91         MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
  92         MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
  93         MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
  94         MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
  95         MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
  96         /* TO2 */
  97         MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
  98         MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
  99         MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
 100         MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
 101         MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
 102         MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
 103         MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
 104         MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
 105         MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
 106         MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
 107         /* TO2 */
 108         MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
 109         MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
 110         MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
 111         MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
 112         MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
 113         MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
 114         MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
 115         MUX_IN_FEC_FEC_COL_SELECT_INPUT,
 116         MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
 117         MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
 118         MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
 119         MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
 120         MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
 121         MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
 122         MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
 123         MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
 124         MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
 125         MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
 126         MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
 127         MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
 128         MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
 129         MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
 130         MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
 131         MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
 132         MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
 133         MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
 134         /* TO2 */
 135         MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
 136         MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
 137         MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
 138         /* TO2 */
 139         MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
 140         /* TO2 */
 141         MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
 142         MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
 143         MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
 144         MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
 145         MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
 146         MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
 147
 148         MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
 149
 150         MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
 151
 152         MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
 153         MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
 154         MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
 155         MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
 156         MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
 157         MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
 158         MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
 159         MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
 160         MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
 161         MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
 162         MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
 163         MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
 164         MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
 165         MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
 166         MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
 167         MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
 168         MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
 169         MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
 170         MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
 171         MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
 172         MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
 173         MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
 174         MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
 175         MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
 176         MUX_INPUT_NUM_MUX,
 177 } iomux_input_select_t;
 178
 179 /*!
 180  * various IOMUX input functions
 181  */
 182 typedef enum iomux_input_config {
 183         INPUT_CTL_PATH0 = 0x0,
 184         INPUT_CTL_PATH1,
 185         INPUT_CTL_PATH2,
 186         INPUT_CTL_PATH3,
 187         INPUT_CTL_PATH4,
 188         INPUT_CTL_PATH5,
 189         INPUT_CTL_PATH6,
 190         INPUT_CTL_PATH7,
 191 } iomux_input_config_t;
 192
 193 /*!
 194  * Request ownership for an IO pin. This function has to be the first one
 195  * being called before that pin is used. The caller has to check the
 196  * return value to make sure it returns 0.
 197  *
 198  * @param  pin          a name defined by \b iomux_pin_name_t
 199  * @param  config       config as defined in \b #iomux_pin_ocfg_t
 200  *
 201  * @return              0 if successful; Non-zero otherwise
 202  */
 203 int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
 204
 205 /*!
 206  * Release ownership for an IO pin
 207  *
 208  * @param  pin          a name defined by \b iomux_pin_name_t
 209  * @param  config       config as defined in \b #iomux_pin_ocfg_t
 210  */
 211 void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
 212
 213 /*!
 214  * This function configures the pad value for a IOMUX pin.
 215  *
 216  * @param  pin          a pin number as defined in \b #iomux_pin_name_t
 217  * @param  config      the ORed value of elements defined in
 218  *                             \b #iomux_pad_config_t
 219  */
 220 void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
 221
 222 /*!
 223  * This function gets the current pad value for a IOMUX pin.
 224  *
 225  * @param  pin          a pin number as defined in \b #iomux_pin_name_t
 226  * @return              current pad value
 227  */
 228 unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
 229
 230 /*!
 231  * This function configures input path.
 232  *
 233  * @param  input        index of input select register as defined in
 234  *                              \b #iomux_input_select_t
 235  * @param  config       the binary value of elements defined in
 236  *                              \b #iomux_input_config_t
 237  */
 238 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
 239
 240 #endif                          /*  __MACH_MX51_IOMUX_H__ */