include/asm-arm/arch-mx51/mmu.h

   1 /*
   2  * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #ifndef __ARM_ARCH_MMU_H
  15 #define __ARM_ARCH_MMU_H
  16
  17 #include <linux/types.h>
  18
  19 /*
  20  * Translation Table Base Bit Masks
  21  */
  22 #define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
  23
  24 /*
  25  * Domain Access Control Bit Masks
  26  */
  27 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
  28 #define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
  29 #define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
  30
  31 struct ARM_MMU_FIRST_LEVEL_FAULT {
  32         unsigned int id:2;
  33         unsigned int sbz:30;
  34 };
  35
  36 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
  37
  38 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
  39         unsigned int id:2;
  40         unsigned int imp:2;
  41         unsigned int domain:4;
  42         unsigned int sbz:1;
  43         unsigned int base_address:23;
  44 };
  45
  46 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
  47
  48 struct ARM_MMU_FIRST_LEVEL_SECTION {
  49         unsigned int id:2;
  50         unsigned int b:1;
  51         unsigned int c:1;
  52         unsigned int imp:1;
  53         unsigned int domain:4;
  54         unsigned int sbz0:1;
  55         unsigned int ap:2;
  56         unsigned int sbz1:8;
  57         unsigned int base_address:12;
  58 };
  59
  60 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
  61
  62 struct ARM_MMU_FIRST_LEVEL_RESERVED {
  63         unsigned int id:2;
  64         unsigned int sbz:30;
  65 };
  66
  67 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
  68
  69 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
  70         (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
  71
  72 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
  73
  74 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,            \
  75                         cacheable, bufferable, perm)                    \
  76         {                                                               \
  77         register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;             \
  78         desc.word = 0;                                                  \
  79         desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;               \
  80         desc.section.domain = 0;                                        \
  81         desc.section.c = (cacheable);                                   \
  82         desc.section.b = (bufferable);                                  \
  83         desc.section.ap = (perm);                                       \
  84         desc.section.base_address = (actual_base);                      \
  85         *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
  86                                 = desc.word;                            \
  87         }
  88
  89 #define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access)      \
  90         {                                                               \
  91                 int i; int j = abase; int k = vbase;                    \
  92                 for (i = size; i > 0 ; i--, j++, k++)                   \
  93                         ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
  94         }
  95
  96 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
  97         unsigned long word;
  98         struct ARM_MMU_FIRST_LEVEL_FAULT fault;
  99         struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
 100         struct ARM_MMU_FIRST_LEVEL_SECTION section;
 101         struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 102 };
 103
 104 #define ARM_UNCACHEABLE         0
 105 #define ARM_CACHEABLE           1
 106 #define ARM_UNBUFFERABLE        0
 107 #define ARM_BUFFERABLE          1
 108
 109 #define ARM_ACCESS_PERM_NONE_NONE       0
 110 #define ARM_ACCESS_PERM_RO_NONE         0
 111 #define ARM_ACCESS_PERM_RO_RO           0
 112 #define ARM_ACCESS_PERM_RW_NONE         1
 113 #define ARM_ACCESS_PERM_RW_RO           2
 114 #define ARM_ACCESS_PERM_RW_RW           3
 115
 116 /*
 117  * Initialization for the Domain Access Control Register
 118  */
 119 #define ARM_ACCESS_DACR_DEFAULT      (  \
 120         ARM_ACCESS_TYPE_MANAGER(0)    | \
 121         ARM_ACCESS_TYPE_NO_ACCESS(1)  | \
 122         ARM_ACCESS_TYPE_NO_ACCESS(2)  | \
 123         ARM_ACCESS_TYPE_NO_ACCESS(3)  | \
 124         ARM_ACCESS_TYPE_NO_ACCESS(4)  | \
 125         ARM_ACCESS_TYPE_NO_ACCESS(5)  | \
 126         ARM_ACCESS_TYPE_NO_ACCESS(6)  | \
 127         ARM_ACCESS_TYPE_NO_ACCESS(7)  | \
 128         ARM_ACCESS_TYPE_NO_ACCESS(8)  | \
 129         ARM_ACCESS_TYPE_NO_ACCESS(9)  | \
 130         ARM_ACCESS_TYPE_NO_ACCESS(10) | \
 131         ARM_ACCESS_TYPE_NO_ACCESS(11) | \
 132         ARM_ACCESS_TYPE_NO_ACCESS(12) | \
 133         ARM_ACCESS_TYPE_NO_ACCESS(13) | \
 134         ARM_ACCESS_TYPE_NO_ACCESS(14) | \
 135         ARM_ACCESS_TYPE_NO_ACCESS(15))
 136
 137 #if defined(CONFIG_MX51_3DS)
 138
 139 /*
 140  * Translate the virtual address of ram space to physical address
 141  * It is dependent on the implementation of mmu_init
 142  */
 143 inline unsigned long iomem_to_phys(unsigned long virt)
 144 {
 145         if (virt < 0x08000000)
 146                 return (unsigned long)(virt | PHYS_SDRAM_1);
 147
 148         if ((virt & 0xF0000000) == PHYS_SDRAM_1)
 149                 return (unsigned long)(virt & (~0x08000000));
 150
 151         return (unsigned long)virt;
 152 }
 153
 154 /*
 155  * remap the physical address of ram space to uncacheable virtual address space
 156  * It is dependent on the implementation of hal_mmu_init
 157  */
 158 void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 159 {
 160         if (1 == flags) {
 161                 /* 0x98000000~0x9FFFFFFF is uncacheable meory
 162                         space which is mapped to SDRAM */
 163                 if ((offset & 0xF0000000) == PHYS_SDRAM_1)
 164                         return (void *)(offset |= 0x08000000);
 165                 else
 166                         return NULL;
 167         } else
 168                 return (void *)offset;
 169 }
 170
 171 #elif defined(CONFIG_MX51_BBG)
 172
 173 /*
 174  * Translate the virtual address of ram space to physical address
 175  * It is dependent on the implementation of mmu_init
 176  */
 177 inline unsigned long iomem_to_phys(unsigned long virt)
 178 {
 179         if (virt < (PHYS_SDRAM_1_SIZE - 0x100000))
 180                 return (unsigned long)(virt + PHYS_SDRAM_1);
 181
 182         if (virt >= 0xE0000000)
 183                 return (unsigned long)((virt - 0xE0000000) + PHYS_SDRAM_1);
 184
 185         return (unsigned long)virt;
 186 }
 187
 188 /*
 189  * Remap the physical address of ram space to uncacheable virtual address space
 190  * It is dependent on the implementation of hal_mmu_init
 191  */
 192 void __iounmap(void *addr)
 193 {
 194         return;
 195 }
 196
 197 void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 198 {
 199         if (1 == flags) {
 200                 /* 0xE0000000~0xFFFFFFFF is uncacheable
 201                 meory space which is mapped to SDRAM */
 202                 if (offset >= PHYS_SDRAM_1 &&
 203                         offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
 204                         return (void *)((offset - PHYS_SDRAM_1) + 0xE0000000);
 205                 else
 206                         return NULL;
 207         } else
 208                 return (void *)offset;
 209 }
 210
 211 #else
 212         #error "No such platforms for MMU!"
 213 #endif
 214
 215 #endif