2 * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
17 #include <asm/system.h>
19 #define MMU_L1_TYPE 0x03 /* Descriptor type */
20 #define MMU_L1_TYPE_Fault 0x00 /* Invalid */
21 #define MMU_L1_TYPE_Page 0x11 /* Individual page mapping */
22 #define MMU_L1_TYPE_Section 0x12 /* Mapping for 1M segment */
24 #define MMU_L2_TYPE 0x03 /* Descriptor type */
25 #define MMU_L2_TYPE_Fault 0x00 /* Invalid data */
26 #define MMU_L2_TYPE_Large 0x01 /* Large page (64K) */
27 #define MMU_L2_TYPE_Small 0x02 /* Small page (4K) */
29 #define MMU_Bufferable 0x04 /* Data can use write-buffer */
30 #define MMU_Cacheable 0x08 /* Data can use cache */
32 #define MMU_AP_Limited 0x000 /* Limited access */
33 #define MMU_AP_Supervisor 0x400 /* Supervisor RW, User none */
34 #define MMU_AP_UserRead 0x800 /* Supervisor RW, User read only */
35 #define MMU_AP_Any 0xC00 /* Supervisor RW, User RW */
37 #define MMU_AP_ap0_Any 0x030
38 #define MMU_AP_ap1_Any 0x0C0
39 #define MMU_AP_ap2_Any 0x300
40 #define MMU_AP_ap3_Any 0xC00
41 #define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any)
43 #define MMU_DOMAIN(x) ((x)<<5)
45 #define MMU_PAGE_SIZE 0x1000
46 #define MMU_SECTION_SIZE 0x100000
48 #define MMU_CP p15 /* Co-processor ID */
49 #define MMU_Control c1 /* Control register */
50 #define MMU_Base c2 /* Page tables base */
51 #define MMU_DomainAccess c3 /* Domain access control */
52 #define MMU_FaultStatus c5 /* Fault status register */
53 #define MMU_FaultAddress c6 /* Fault Address */
54 #define MMU_InvalidateCache c7 /* Invalidate cache data */
55 #define MMU_TLB c8 /* Translation Lookaside Buffer */
57 /* These seem to be 710 specific */
58 #define MMU_FlushTLB c5
59 #define MMU_FlushIDC c7
61 #define MMU_Control_M 0x001 /* Enable MMU */
62 #define MMU_Control_A 0x002 /* Enable address alignment faults */
63 #define MMU_Control_C 0x004 /* Enable cache */
64 #define MMU_Control_W 0x008 /* Enable write-buffer */
65 #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
66 #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
67 #define MMU_Control_L 0x040 /* Compatability: */
68 #define MMU_Control_B 0x080 /* Enable Big-Endian */
69 #define MMU_Control_S 0x100 /* Enable system protection */
70 #define MMU_Control_R 0x200 /* Enable ROM protection */
71 #define MMU_Control_I 0x1000 /* Enable Instruction cache */
72 #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
73 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
75 /* Extras for some newer versions eg. ARM920 with architecture version 4. */
76 #define MMU_Control_F 0x400 /* IMPLEMENTATION DEFINED */
77 #define MMU_Control_Z 0x800 /* Enable branch predicion */
78 #define MMU_Control_RR 0x4000 /* Select non-random cache replacement */
80 #ifdef CONFIG_ARCH_MMU
84 unsigned long cr = 0; \
85 asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) : /*:*/); \
86 cr |= (CR_M | CR_A | CR_C | CR_Z); \
87 asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \
88 /* Clean instruction pipeline */ \
100 unsigned long cr = 0; \
101 asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) /*: :*/); \
102 cr &= (~(CR_M | CR_A | CR_C | CR_I)); \
103 asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \
105 "nop;" /* flush i+d-TLBs */ \
106 "nop;" /* flush i+d-TLBs */ \
107 "nop;" /* flush i+d-TLBs */ \