include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  11  */
  12 #ifndef _ASM_MIPSREGS_H
  13 #define _ASM_MIPSREGS_H
  14
  15 #if 0
  16 #include <linux/linkage.h>
  17 #endif
  18
  19 /*
  20  * The following macros are especially useful for __asm__
  21  * inline assembler.
  22  */
  23 #ifndef __STR
  24 #define __STR(x) #x
  25 #endif
  26 #ifndef STR
  27 #define STR(x) __STR(x)
  28 #endif
  29
  30 /*
  31  * Coprocessor 0 register names
  32  */
  33 #define CP0_INDEX $0
  34 #define CP0_RANDOM $1
  35 #define CP0_ENTRYLO0 $2
  36 #define CP0_ENTRYLO1 $3
  37 #define CP0_CONF $3
  38 #define CP0_CONTEXT $4
  39 #define CP0_PAGEMASK $5
  40 #define CP0_WIRED $6
  41 #define CP0_INFO $7
  42 #define CP0_BADVADDR $8
  43 #define CP0_COUNT $9
  44 #define CP0_ENTRYHI $10
  45 #define CP0_COMPARE $11
  46 #define CP0_STATUS $12
  47 #define CP0_CAUSE $13
  48 #define CP0_EPC $14
  49 #define CP0_PRID $15
  50 #define CP0_CONFIG $16
  51 #define CP0_LLADDR $17
  52 #define CP0_WATCHLO $18
  53 #define CP0_WATCHHI $19
  54 #define CP0_XCONTEXT $20
  55 #define CP0_FRAMEMASK $21
  56 #define CP0_DIAGNOSTIC $22
  57 #define CP0_PERFORMANCE $25
  58 #define CP0_ECC $26
  59 #define CP0_CACHEERR $27
  60 #define CP0_TAGLO $28
  61 #define CP0_TAGHI $29
  62 #define CP0_ERROREPC $30
  63
  64 /*
  65  * R4640/R4650 cp0 register names.  These registers are listed
  66  * here only for completeness; without MMU these CPUs are not useable
  67  * by Linux.  A future ELKS port might take make Linux run on them
  68  * though ...
  69  */
  70 #define CP0_IBASE $0
  71 #define CP0_IBOUND $1
  72 #define CP0_DBASE $2
  73 #define CP0_DBOUND $3
  74 #define CP0_CALG $17
  75 #define CP0_IWATCH $18
  76 #define CP0_DWATCH $19
  77
  78 /*
  79  * Coprocessor 0 Set 1 register names
  80  */
  81 #define CP0_S1_DERRADDR0  $26
  82 #define CP0_S1_DERRADDR1  $27
  83 #define CP0_S1_INTCONTROL $20
  84 /*
  85  * Coprocessor 1 (FPU) register names
  86  */
  87 #define CP1_REVISION   $0
  88 #define CP1_STATUS     $31
  89
  90 /*
  91  * FPU Status Register Values
  92  */
  93 /*
  94  * Status Register Values
  95  */
  96
  97 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
  98 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
  99 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 100 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 101 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 102 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 103 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 104 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 105 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 106 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 107
 108 /*
 109  * X the exception cause indicator
 110  * E the exception enable
 111  * S the sticky/flag bit
 112 */
 113 #define FPU_CSR_ALL_X 0x0003f000
 114 #define FPU_CSR_UNI_X   0x00020000
 115 #define FPU_CSR_INV_X   0x00010000
 116 #define FPU_CSR_DIV_X   0x00008000
 117 #define FPU_CSR_OVF_X   0x00004000
 118 #define FPU_CSR_UDF_X   0x00002000
 119 #define FPU_CSR_INE_X   0x00001000
 120
 121 #define FPU_CSR_ALL_E   0x00000f80
 122 #define FPU_CSR_INV_E   0x00000800
 123 #define FPU_CSR_DIV_E   0x00000400
 124 #define FPU_CSR_OVF_E   0x00000200
 125 #define FPU_CSR_UDF_E   0x00000100
 126 #define FPU_CSR_INE_E   0x00000080
 127
 128 #define FPU_CSR_ALL_S   0x0000007c
 129 #define FPU_CSR_INV_S   0x00000040
 130 #define FPU_CSR_DIV_S   0x00000020
 131 #define FPU_CSR_OVF_S   0x00000010
 132 #define FPU_CSR_UDF_S   0x00000008
 133 #define FPU_CSR_INE_S   0x00000004
 134
 135 /* rounding mode */
 136 #define FPU_CSR_RN      0x0     /* nearest */
 137 #define FPU_CSR_RZ      0x1     /* towards zero */
 138 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 139 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 140
 141
 142 /*
 143  * Values for PageMask register
 144  */
 145 #include <linux/config.h>
 146 #ifdef CONFIG_CPU_VR41XX
 147 #define PM_1K   0x00000000
 148 #define PM_4K   0x00001800
 149 #define PM_16K  0x00007800
 150 #define PM_64K  0x0001f800
 151 #define PM_256K 0x0007f800
 152 #else
 153 #define PM_4K   0x00000000
 154 #define PM_16K  0x00006000
 155 #define PM_64K  0x0001e000
 156 #define PM_256K 0x0007e000
 157 #define PM_1M   0x001fe000
 158 #define PM_4M   0x007fe000
 159 #define PM_16M  0x01ffe000
 160 #endif
 161
 162 /*
 163  * Values used for computation of new tlb entries
 164  */
 165 #define PL_4K   12
 166 #define PL_16K  14
 167 #define PL_64K  16
 168 #define PL_256K 18
 169 #define PL_1M   20
 170 #define PL_4M   22
 171 #define PL_16M  24
 172
 173 /*
 174  * Macros to access the system control coprocessor
 175  */
 176 #define read_32bit_cp0_register(source)                         \
 177 ({ int __res;                                                   \
 178         __asm__ __volatile__(                                   \
 179         ".set\tpush\n\t"                                        \
 180         ".set\treorder\n\t"                                     \
 181         "mfc0\t%0,"STR(source)"\n\t"                            \
 182         ".set\tpop"                                             \
 183         : "=r" (__res));                                        \
 184         __res;})
 185
 186 #define read_32bit_cp0_set1_register(source)                    \
 187 ({ int __res;                                                   \
 188         __asm__ __volatile__(                                   \
 189         ".set\tpush\n\t"                                        \
 190         ".set\treorder\n\t"                                     \
 191         "cfc0\t%0,"STR(source)"\n\t"                            \
 192         ".set\tpop"                                             \
 193         : "=r" (__res));                                        \
 194         __res;})
 195
 196 /*
 197  * For now use this only with interrupts disabled!
 198  */
 199 #define read_64bit_cp0_register(source)                         \
 200 ({ int __res;                                                   \
 201         __asm__ __volatile__(                                   \
 202         ".set\tmips3\n\t"                                       \
 203         "dmfc0\t%0,"STR(source)"\n\t"                           \
 204         ".set\tmips0"                                           \
 205         : "=r" (__res));                                        \
 206         __res;})
 207
 208 #define write_32bit_cp0_register(register,value)                \
 209         __asm__ __volatile__(                                   \
 210         "mtc0\t%0,"STR(register)"\n\t"                          \
 211         "nop"                                                   \
 212         : : "r" (value));
 213
 214 #define write_32bit_cp0_set1_register(register,value)           \
 215         __asm__ __volatile__(                                   \
 216         "ctc0\t%0,"STR(register)"\n\t"                          \
 217         "nop"                                                   \
 218         : : "r" (value));
 219
 220 #define write_64bit_cp0_register(register,value)                \
 221         __asm__ __volatile__(                                   \
 222         ".set\tmips3\n\t"                                       \
 223         "dmtc0\t%0,"STR(register)"\n\t"                         \
 224         ".set\tmips0"                                           \
 225         : : "r" (value))
 226
 227 /*
 228  * This should be changed when we get a compiler that support the MIPS32 ISA.
 229  */
 230 #define read_mips32_cp0_config1()                               \
 231 ({ int __res;                                                   \
 232         __asm__ __volatile__(                                   \
 233         ".set\tnoreorder\n\t"                                   \
 234         ".set\tnoat\n\t"                                        \
 235         ".word\t0x40018001\n\t"                                 \
 236         "move\t%0,$1\n\t"                                       \
 237         ".set\tat\n\t"                                          \
 238         ".set\treorder"                                         \
 239         :"=r" (__res));                                         \
 240         __res;})
 241
 242 /*
 243  * R4x00 interrupt enable / cause bits
 244  */
 245 #define IE_SW0          (1<< 8)
 246 #define IE_SW1          (1<< 9)
 247 #define IE_IRQ0         (1<<10)
 248 #define IE_IRQ1         (1<<11)
 249 #define IE_IRQ2         (1<<12)
 250 #define IE_IRQ3         (1<<13)
 251 #define IE_IRQ4         (1<<14)
 252 #define IE_IRQ5         (1<<15)
 253
 254 /*
 255  * R4x00 interrupt cause bits
 256  */
 257 #define C_SW0           (1<< 8)
 258 #define C_SW1           (1<< 9)
 259 #define C_IRQ0          (1<<10)
 260 #define C_IRQ1          (1<<11)
 261 #define C_IRQ2          (1<<12)
 262 #define C_IRQ3          (1<<13)
 263 #define C_IRQ4          (1<<14)
 264 #define C_IRQ5          (1<<15)
 265
 266 #ifndef _LANGUAGE_ASSEMBLY
 267 /*
 268  * Manipulate the status register.
 269  * Mostly used to access the interrupt bits.
 270  */
 271 #define __BUILD_SET_CP0(name,register)                          \
 272 extern __inline__ unsigned int                                  \
 273 set_cp0_##name(unsigned int set)                                \
 274 {                                                               \
 275         unsigned int res;                                       \
 276                                                                 \
 277         res = read_32bit_cp0_register(register);                \
 278         res |= set;                                             \
 279         write_32bit_cp0_register(register, res);                \
 280                                                                 \
 281         return res;                                             \
 282 }                                                               \
 283                                                                 \
 284 extern __inline__ unsigned int                                  \
 285 clear_cp0_##name(unsigned int clear)                            \
 286 {                                                               \
 287         unsigned int res;                                       \
 288                                                                 \
 289         res = read_32bit_cp0_register(register);                \
 290         res &= ~clear;                                          \
 291         write_32bit_cp0_register(register, res);                \
 292                                                                 \
 293         return res;                                             \
 294 }                                                               \
 295                                                                 \
 296 extern __inline__ unsigned int                                  \
 297 change_cp0_##name(unsigned int change, unsigned int new)        \
 298 {                                                               \
 299         unsigned int res;                                       \
 300                                                                 \
 301         res = read_32bit_cp0_register(register);                \
 302         res &= ~change;                                         \
 303         res |= (new & change);                                  \
 304         if(change)                                              \
 305                 write_32bit_cp0_register(register, res);        \
 306                                                                 \
 307         return res;                                             \
 308 }
 309
 310 __BUILD_SET_CP0(status,CP0_STATUS)
 311 __BUILD_SET_CP0(cause,CP0_CAUSE)
 312 __BUILD_SET_CP0(config,CP0_CONFIG)
 313
 314 #endif /* defined (_LANGUAGE_ASSEMBLY) */
 315
 316 /*
 317  * Bitfields in the R4xx0 cp0 status register
 318  */
 319 #define ST0_IE                  0x00000001
 320 #define ST0_EXL                 0x00000002
 321 #define ST0_ERL                 0x00000004
 322 #define ST0_KSU                 0x00000018
 323 #  define KSU_USER              0x00000010
 324 #  define KSU_SUPERVISOR        0x00000008
 325 #  define KSU_KERNEL            0x00000000
 326 #define ST0_UX                  0x00000020
 327 #define ST0_SX                  0x00000040
 328 #define ST0_KX                  0x00000080
 329 #define ST0_DE                  0x00010000
 330 #define ST0_CE                  0x00020000
 331
 332 /*
 333  * Bitfields in the R[23]000 cp0 status register.
 334  */
 335 #define ST0_IEC                 0x00000001
 336 #define ST0_KUC                 0x00000002
 337 #define ST0_IEP                 0x00000004
 338 #define ST0_KUP                 0x00000008
 339 #define ST0_IEO                 0x00000010
 340 #define ST0_KUO                 0x00000020
 341 /* bits 6 & 7 are reserved on R[23]000 */
 342 #define ST0_ISC                 0x00010000
 343 #define ST0_SWC                 0x00020000
 344 #define ST0_CM                  0x00080000
 345
 346 /*
 347  * Bits specific to the R4640/R4650
 348  */
 349 #define ST0_UM                 (1   <<  4)
 350 #define ST0_IL                 (1   << 23)
 351 #define ST0_DL                 (1   << 24)
 352
 353 /*
 354  * Bitfields in the TX39 family CP0 Configuration Register 3
 355  */
 356 #define TX39_CONF_ICS_SHIFT     19
 357 #define TX39_CONF_ICS_MASK      0x00380000
 358 #define TX39_CONF_ICS_1KB       0x00000000
 359 #define TX39_CONF_ICS_2KB       0x00080000
 360 #define TX39_CONF_ICS_4KB       0x00100000
 361 #define TX39_CONF_ICS_8KB       0x00180000
 362 #define TX39_CONF_ICS_16KB      0x00200000
 363
 364 #define TX39_CONF_DCS_SHIFT     16
 365 #define TX39_CONF_DCS_MASK      0x00070000
 366 #define TX39_CONF_DCS_1KB       0x00000000
 367 #define TX39_CONF_DCS_2KB       0x00010000
 368 #define TX39_CONF_DCS_4KB       0x00020000
 369 #define TX39_CONF_DCS_8KB       0x00030000
 370 #define TX39_CONF_DCS_16KB      0x00040000
 371
 372 #define TX39_CONF_CWFON         0x00004000
 373 #define TX39_CONF_WBON          0x00002000
 374 #define TX39_CONF_RF_SHIFT      10
 375 #define TX39_CONF_RF_MASK       0x00000c00
 376 #define TX39_CONF_DOZE          0x00000200
 377 #define TX39_CONF_HALT          0x00000100
 378 #define TX39_CONF_LOCK          0x00000080
 379 #define TX39_CONF_ICE           0x00000020
 380 #define TX39_CONF_DCE           0x00000010
 381 #define TX39_CONF_IRSIZE_SHIFT  2
 382 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 383 #define TX39_CONF_DRSIZE_SHIFT  0
 384 #define TX39_CONF_DRSIZE_MASK   0x00000003
 385
 386 /*
 387  * Status register bits available in all MIPS CPUs.
 388  */
 389 #define ST0_IM                  0x0000ff00
 390 #define  STATUSB_IP0            8
 391 #define  STATUSF_IP0            (1   <<  8)
 392 #define  STATUSB_IP1            9
 393 #define  STATUSF_IP1            (1   <<  9)
 394 #define  STATUSB_IP2            10
 395 #define  STATUSF_IP2            (1   << 10)
 396 #define  STATUSB_IP3            11
 397 #define  STATUSF_IP3            (1   << 11)
 398 #define  STATUSB_IP4            12
 399 #define  STATUSF_IP4            (1   << 12)
 400 #define  STATUSB_IP5            13
 401 #define  STATUSF_IP5            (1   << 13)
 402 #define  STATUSB_IP6            14
 403 #define  STATUSF_IP6            (1   << 14)
 404 #define  STATUSB_IP7            15
 405 #define  STATUSF_IP7            (1   << 15)
 406 #define  STATUSB_IP8            0
 407 #define  STATUSF_IP8            (1   << 0)
 408 #define  STATUSB_IP9            1
 409 #define  STATUSF_IP9            (1   << 1)
 410 #define  STATUSB_IP10           2
 411 #define  STATUSF_IP10           (1   << 2)
 412 #define  STATUSB_IP11           3
 413 #define  STATUSF_IP11           (1   << 3)
 414 #define  STATUSB_IP12           4
 415 #define  STATUSF_IP12           (1   << 4)
 416 #define  STATUSB_IP13           5
 417 #define  STATUSF_IP13           (1   << 5)
 418 #define  STATUSB_IP14           6
 419 #define  STATUSF_IP14           (1   << 6)
 420 #define  STATUSB_IP15           7
 421 #define  STATUSF_IP15           (1   << 7)
 422 #define ST0_CH                  0x00040000
 423 #define ST0_SR                  0x00100000
 424 #define ST0_BEV                 0x00400000
 425 #define ST0_RE                  0x02000000
 426 #define ST0_FR                  0x04000000
 427 #define ST0_CU                  0xf0000000
 428 #define ST0_CU0                 0x10000000
 429 #define ST0_CU1                 0x20000000
 430 #define ST0_CU2                 0x40000000
 431 #define ST0_CU3                 0x80000000
 432 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 433
 434 /*
 435  * Bitfields and bit numbers in the coprocessor 0 cause register.
 436  *
 437  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 438  */
 439 #define  CAUSEB_EXCCODE         2
 440 #define  CAUSEF_EXCCODE         (31  <<  2)
 441 #define  CAUSEB_IP              8
 442 #define  CAUSEF_IP              (255 <<  8)
 443 #define  CAUSEB_IP0             8
 444 #define  CAUSEF_IP0             (1   <<  8)
 445 #define  CAUSEB_IP1             9
 446 #define  CAUSEF_IP1             (1   <<  9)
 447 #define  CAUSEB_IP2             10
 448 #define  CAUSEF_IP2             (1   << 10)
 449 #define  CAUSEB_IP3             11
 450 #define  CAUSEF_IP3             (1   << 11)
 451 #define  CAUSEB_IP4             12
 452 #define  CAUSEF_IP4             (1   << 12)
 453 #define  CAUSEB_IP5             13
 454 #define  CAUSEF_IP5             (1   << 13)
 455 #define  CAUSEB_IP6             14
 456 #define  CAUSEF_IP6             (1   << 14)
 457 #define  CAUSEB_IP7             15
 458 #define  CAUSEF_IP7             (1   << 15)
 459 #define  CAUSEB_IV              23
 460 #define  CAUSEF_IV              (1   << 23)
 461 #define  CAUSEB_CE              28
 462 #define  CAUSEF_CE              (3   << 28)
 463 #define  CAUSEB_BD              31
 464 #define  CAUSEF_BD              (1   << 31)
 465
 466 /*
 467  * Bits in the coprozessor 0 config register.
 468  */
 469 #define CONF_CM_CACHABLE_NO_WA          0
 470 #define CONF_CM_CACHABLE_WA             1
 471 #define CONF_CM_UNCACHED                2
 472 #define CONF_CM_CACHABLE_NONCOHERENT    3
 473 #define CONF_CM_CACHABLE_CE             4
 474 #define CONF_CM_CACHABLE_COW            5
 475 #define CONF_CM_CACHABLE_CUW            6
 476 #define CONF_CM_CACHABLE_ACCELERATED    7
 477 #define CONF_CM_CMASK                   7
 478 #define CONF_DB                         (1 <<  4)
 479 #define CONF_IB                         (1 <<  5)
 480 #define CONF_SC                         (1 << 17)
 481 #define CONF_AC                         (1 << 23)
 482 #define CONF_HALT                       (1 << 25)
 483
 484 /*
 485  * R10000 performance counter definitions.
 486  *
 487  * FIXME: The R10000 performance counter opens a nice way to implement CPU
 488  *        time accounting with a precission of one cycle.  I don't have
 489  *        R10000 silicon but just a manual, so ...
 490  */
 491
 492 /*
 493  * Events counted by counter #0
 494  */
 495 #define CE0_CYCLES                      0
 496 #define CE0_INSN_ISSUED                 1
 497 #define CE0_LPSC_ISSUED                 2
 498 #define CE0_S_ISSUED                    3
 499 #define CE0_SC_ISSUED                   4
 500 #define CE0_SC_FAILED                   5
 501 #define CE0_BRANCH_DECODED              6
 502 #define CE0_QW_WB_SECONDARY             7
 503 #define CE0_CORRECTED_ECC_ERRORS        8
 504 #define CE0_ICACHE_MISSES               9
 505 #define CE0_SCACHE_I_MISSES             10
 506 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
 507 #define CE0_EXT_INTERVENTIONS_REQ       12
 508 #define CE0_EXT_INVALIDATE_REQ          13
 509 #define CE0_VIRTUAL_COHERENCY_COND      14
 510 #define CE0_INSN_GRADUATED              15
 511
 512 /*
 513  * Events counted by counter #1
 514  */
 515 #define CE1_CYCLES                      0
 516 #define CE1_INSN_GRADUATED              1
 517 #define CE1_LPSC_GRADUATED              2
 518 #define CE1_S_GRADUATED                 3
 519 #define CE1_SC_GRADUATED                4
 520 #define CE1_FP_INSN_GRADUATED           5
 521 #define CE1_QW_WB_PRIMARY               6
 522 #define CE1_TLB_REFILL                  7
 523 #define CE1_BRANCH_MISSPREDICTED        8
 524 #define CE1_DCACHE_MISS                 9
 525 #define CE1_SCACHE_D_MISSES             10
 526 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
 527 #define CE1_EXT_INTERVENTION_HITS       12
 528 #define CE1_EXT_INVALIDATE_REQ          13
 529 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
 530 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 531
 532 /*
 533  * These flags define in which priviledge mode the counters count events
 534  */
 535 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
 536 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
 537 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
 538 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
 539
 540 #endif /* _ASM_MIPSREGS_H */