include/configs/CPU87.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
  21 #define CONFIG_PCI
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #ifdef CONFIG_BOOT_ROM
  25 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  26 #else
  27 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  28 #endif
  29
  30 /*
  31  * select serial console configuration
  32  *
  33  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  34  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  35  * for SCC).
  36  *
  37  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  38  * defined elsewhere (for example, on the cogent platform, there are serial
  39  * ports on the motherboard which are used for the serial console - see
  40  * cogent/cma101/serial.[ch]).
  41  */
  42 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  43 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  44 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  45 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  46
  47 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  48 #define CONFIG_BAUDRATE         230400
  49 #else
  50 #define CONFIG_BAUDRATE         9600
  51 #endif
  52
  53 /*
  54  * select ethernet configuration
  55  *
  56  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58  * for FCC)
  59  *
  60  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  61  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  64 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  65 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  66 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  67
  68 #define CONFIG_HAS_ETH1         1
  69 #define CONFIG_HAS_ETH2         1
  70
  71 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  72
  73 /*
  74  * - Rx-CLK is CLK11
  75  * - Tx-CLK is CLK12
  76  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  77  * - Enable Full Duplex in FSMR
  78  */
  79 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  80 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  81 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  82 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  83
  84 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  85
  86 /*
  87  * - Rx-CLK is CLK13
  88  * - Tx-CLK is CLK14
  89  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  90  * - Enable Full Duplex in FSMR
  91  */
  92 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  93 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  94 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  95 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  96
  97 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  98
  99 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 100 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 101
 102 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 103
 104 #define CONFIG_PREBOOT                                                          \
 105         "echo; "                                                                \
 106         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 107         "echo"
 108
 109 #undef  CONFIG_BOOTARGS
 110 #define CONFIG_BOOTCOMMAND                                                      \
 111         "bootp; "                                                               \
 112         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 113         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 114         "bootm"
 115
 116 /*-----------------------------------------------------------------------
 117  * I2C/EEPROM/RTC configuration
 118  */
 119 #define CONFIG_SYS_I2C
 120 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 121 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 122 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 123
 124 /*
 125  * Software (bit-bang) I2C driver configuration
 126  */
 127 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 128 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 129 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 130 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 131 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 132                         else    iop->pdat &= ~0x00010000
 133 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 134                         else    iop->pdat &= ~0x00020000
 135 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 136
 137 #define CONFIG_RTC_PCF8563
 138 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 139
 140 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 141
 142 /*-----------------------------------------------------------------------
 143  * Disk-On-Chip configuration
 144  */
 145
 146 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
 147
 148 #define CONFIG_SYS_DOC_SUPPORT_2000
 149 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 150
 151 /*-----------------------------------------------------------------------
 152  * Miscellaneous configuration options
 153  */
 154
 155 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 156 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 157
 158 /*
 159  * BOOTP options
 160  */
 161 #define CONFIG_BOOTP_SUBNETMASK
 162 #define CONFIG_BOOTP_GATEWAY
 163 #define CONFIG_BOOTP_HOSTNAME
 164 #define CONFIG_BOOTP_BOOTPATH
 165 #define CONFIG_BOOTP_BOOTFILESIZE
 166
 167
 168 /*
 169  * Command line configuration.
 170  */
 171 #include <config_cmd_default.h>
 172
 173 #define CONFIG_CMD_BEDBUG
 174 #define CONFIG_CMD_DATE
 175 #define CONFIG_CMD_EEPROM
 176 #define CONFIG_CMD_I2C
 177
 178 #ifdef CONFIG_PCI
 179 #define CONFIG_PCI_INDIRECT_BRIDGE
 180     #define CONFIG_CMD_PCI
 181 #endif
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 187 #if defined(CONFIG_CMD_KGDB)
 188 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 189 #else
 190 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 191 #endif
 192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 193 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 194 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 195
 196 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 197 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 198
 199 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 200
 201 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 202
 203 #define CONFIG_LOOPW
 204
 205 /*
 206  * For booting Linux, the board info and command line data
 207  * have to be in the first 8 MB of memory, since this is
 208  * the maximum mapped by the Linux kernel during initialization.
 209  */
 210 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 211
 212 /*-----------------------------------------------------------------------
 213  * Flash configuration
 214  */
 215
 216 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 217 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 218 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 219 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 220
 221 /*-----------------------------------------------------------------------
 222  * FLASH organization
 223  */
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 226
 227 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 228 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 229
 230 /*-----------------------------------------------------------------------
 231  * Other areas to be mapped
 232  */
 233
 234 /* CS3: Dual ported SRAM */
 235 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 236 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
 237
 238 /* CS4: DiskOnChip */
 239 #define CONFIG_SYS_DOC_BASE             0xF4000000
 240 #define CONFIG_SYS_DOC_SIZE             0x00100000
 241
 242 /* CS5: FDC37C78 controller */
 243 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 244 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 245
 246 /* CS6: Board configuration registers */
 247 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 248 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 249
 250 /* CS7: VME Extended Access Range */
 251 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
 252 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 253
 254 /* CS8: VME Standard Access Range */
 255 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 256 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 257
 258 /* CS9: VME Short I/O Access Range */
 259 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 260 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 261
 262 /*-----------------------------------------------------------------------
 263  * Hard Reset Configuration Words
 264  *
 265  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 266  * defines for the various registers affected by the HRCW e.g. changing
 267  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 268  */
 269 #if defined(CONFIG_BOOT_ROM)
 270 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 271                                  HRCW_BPS01 | HRCW_CS10PC01)
 272 #else
 273 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 274 #endif
 275
 276 /* no slaves so just fill with zeros */
 277 #define CONFIG_SYS_HRCW_SLAVE1          0
 278 #define CONFIG_SYS_HRCW_SLAVE2          0
 279 #define CONFIG_SYS_HRCW_SLAVE3          0
 280 #define CONFIG_SYS_HRCW_SLAVE4          0
 281 #define CONFIG_SYS_HRCW_SLAVE5          0
 282 #define CONFIG_SYS_HRCW_SLAVE6          0
 283 #define CONFIG_SYS_HRCW_SLAVE7          0
 284
 285 /*-----------------------------------------------------------------------
 286  * Internal Memory Mapped Register
 287  */
 288 #define CONFIG_SYS_IMMR         0xF0000000
 289
 290 /*-----------------------------------------------------------------------
 291  * Definitions for initial stack pointer and data area (in DPRAM)
 292  */
 293 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 294 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 295 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 296 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 297
 298 /*-----------------------------------------------------------------------
 299  * Start addresses for the final memory configuration
 300  * (Set up by the startup code)
 301  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 302  *
 303  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 304  */
 305 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 306 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 307 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 308 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 309 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 310
 311 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 312 # define CONFIG_SYS_RAMBOOT
 313 #endif
 314
 315 #ifdef  CONFIG_PCI
 316 #define CONFIG_PCI_PNP
 317 #define CONFIG_EEPRO100
 318 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 319 #endif
 320
 321 #if 0
 322 /* environment is in Flash */
 323 #define CONFIG_ENV_IS_IN_FLASH  1
 324 #ifdef CONFIG_BOOT_ROM
 325 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 326 # define CONFIG_ENV_SIZE                0x10000
 327 # define CONFIG_ENV_SECT_SIZE   0x10000
 328 #endif
 329 #else
 330 /* environment is in EEPROM */
 331 #define CONFIG_ENV_IS_IN_EEPROM 1
 332 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 334 /* mask of address bits that overflow into the "EEPROM chip address"    */
 335 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 337 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 338 #define CONFIG_ENV_OFFSET               512
 339 #define CONFIG_ENV_SIZE         (2048 - 512)
 340 #endif
 341
 342 /*-----------------------------------------------------------------------
 343  * Cache Configuration
 344  */
 345 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 346 #if defined(CONFIG_CMD_KGDB)
 347 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 348 #endif
 349
 350 /*-----------------------------------------------------------------------
 351  * HIDx - Hardware Implementation-dependent Registers                    2-11
 352  *-----------------------------------------------------------------------
 353  * HID0 also contains cache control - initially enable both caches and
 354  * invalidate contents, then the final state leaves only the instruction
 355  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 356  * but Soft reset does not.
 357  *
 358  * HID1 has only read-only information - nothing to set.
 359  */
 360 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
 361                          HID0_DCI|HID0_IFEM|HID0_ABE)
 362 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 363 #define CONFIG_SYS_HID2 0
 364
 365 /*-----------------------------------------------------------------------
 366  * RMR - Reset Mode Register                                     5-5
 367  *-----------------------------------------------------------------------
 368  * turn on Checkstop Reset Enable
 369  */
 370 #define CONFIG_SYS_RMR          RMR_CSRE
 371
 372 /*-----------------------------------------------------------------------
 373  * BCR - Bus Configuration                                       4-25
 374  *-----------------------------------------------------------------------
 375  */
 376 #define BCR_APD01       0x10000000
 377 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 378
 379 /*-----------------------------------------------------------------------
 380  * SIUMCR - SIU Module Configuration                             4-31
 381  *-----------------------------------------------------------------------
 382  */
 383 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 384                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 385
 386 /*-----------------------------------------------------------------------
 387  * SYPCR - System Protection Control                             4-35
 388  * SYPCR can only be written once after reset!
 389  *-----------------------------------------------------------------------
 390  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 391  */
 392 #if defined(CONFIG_WATCHDOG)
 393 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 394                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 395 #else
 396 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 397                          SYPCR_SWRI|SYPCR_SWP)
 398 #endif /* CONFIG_WATCHDOG */
 399
 400 /*-----------------------------------------------------------------------
 401  * TMCNTSC - Time Counter Status and Control                     4-40
 402  *-----------------------------------------------------------------------
 403  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 404  * and enable Time Counter
 405  */
 406 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 407
 408 /*-----------------------------------------------------------------------
 409  * PISCR - Periodic Interrupt Status and Control                 4-42
 410  *-----------------------------------------------------------------------
 411  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 412  * Periodic timer
 413  */
 414 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 415
 416 /*-----------------------------------------------------------------------
 417  * SCCR - System Clock Control                                   9-8
 418  *-----------------------------------------------------------------------
 419  * Ensure DFBRG is Divide by 16
 420  */
 421 #define CONFIG_SYS_SCCR SCCR_DFBRG01
 422
 423 /*-----------------------------------------------------------------------
 424  * RCCR - RISC Controller Configuration                         13-7
 425  *-----------------------------------------------------------------------
 426  */
 427 #define CONFIG_SYS_RCCR 0
 428
 429 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 430
 431 /*
 432  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
 433  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 434  */
 435
 436 /*-----------------------------------------------------------------------
 437  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 438  *-----------------------------------------------------------------------
 439  */
 440 #define CONFIG_SYS_MPTPR        0x2000
 441
 442 /*-----------------------------------------------------------------------
 443  * PSRT - Refresh Timer Register                                10-16
 444  *-----------------------------------------------------------------------
 445  */
 446 #define CONFIG_SYS_PSRT 0x16
 447
 448 /*-----------------------------------------------------------------------
 449  * PSRT - SDRAM Mode Register                                   10-10
 450  *-----------------------------------------------------------------------
 451  */
 452
 453         /* SDRAM initialization values for 8-column chips
 454          */
 455 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 456                          ORxS_BPD_4                     |\
 457                          ORxS_ROWST_PBI0_A9             |\
 458                          ORxS_NUMR_12)
 459
 460 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 461                          PSDMR_BSMA_A14_A16             |\
 462                          PSDMR_SDA10_PBI0_A10           |\
 463                          PSDMR_RFRC_7_CLK               |\
 464                          PSDMR_PRETOACT_2W              |\
 465                          PSDMR_ACTTORW_2W               |\
 466                          PSDMR_LDOTOPRE_1C              |\
 467                          PSDMR_WRC_1C                   |\
 468                          PSDMR_CL_2)
 469
 470         /* SDRAM initialization values for 9-column chips
 471          */
 472 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 473                          ORxS_BPD_4                     |\
 474                          ORxS_ROWST_PBI0_A7             |\
 475                          ORxS_NUMR_13)
 476
 477 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 478                          PSDMR_BSMA_A13_A15             |\
 479                          PSDMR_SDA10_PBI0_A9            |\
 480                          PSDMR_RFRC_7_CLK               |\
 481                          PSDMR_PRETOACT_2W              |\
 482                          PSDMR_ACTTORW_2W               |\
 483                          PSDMR_LDOTOPRE_1C              |\
 484                          PSDMR_WRC_1C                   |\
 485                          PSDMR_CL_2)
 486
 487         /* SDRAM initialization values for 10-column chips
 488          */
 489 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
 490                          ORxS_BPD_4                     |\
 491                          ORxS_ROWST_PBI1_A4             |\
 492                          ORxS_NUMR_13)
 493
 494 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 495                          PSDMR_SDAM_A17_IS_A5           |\
 496                          PSDMR_BSMA_A13_A15             |\
 497                          PSDMR_SDA10_PBI1_A6            |\
 498                          PSDMR_RFRC_7_CLK               |\
 499                          PSDMR_PRETOACT_2W              |\
 500                          PSDMR_ACTTORW_2W               |\
 501                          PSDMR_LDOTOPRE_1C              |\
 502                          PSDMR_WRC_1C                   |\
 503                          PSDMR_CL_2)
 504
 505 /*
 506  * Init Memory Controller:
 507  *
 508  * Bank Bus     Machine PortSz  Device
 509  * ---- ---     ------- ------  ------
 510  *  0   60x     GPCM    8  bit  Boot ROM
 511  *  1   60x     GPCM    64 bit  FLASH
 512  *  2   60x     SDRAM   64 bit  SDRAM
 513  *
 514  */
 515
 516 #define CONFIG_SYS_MRS_OFFS     0x00000000
 517
 518 #ifdef CONFIG_BOOT_ROM
 519 /* Bank 0 - Boot ROM
 520  */
 521 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 522                          BRx_PS_8                       |\
 523                          BRx_MS_GPCM_P                  |\
 524                          BRx_V)
 525
 526 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 527                          ORxG_CSNT                      |\
 528                          ORxG_ACS_DIV1                  |\
 529                          ORxG_SCY_5_CLK                 |\
 530                          ORxU_EHTR_8IDLE)
 531
 532 /* Bank 1 - FLASH
 533  */
 534 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 535                          BRx_PS_64                      |\
 536                          BRx_MS_GPCM_P                  |\
 537                          BRx_V)
 538
 539 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 540                          ORxG_CSNT                      |\
 541                          ORxG_ACS_DIV1                  |\
 542                          ORxG_SCY_5_CLK                 |\
 543                          ORxU_EHTR_8IDLE)
 544
 545 #else /* CONFIG_BOOT_ROM */
 546 /* Bank 0 - FLASH
 547  */
 548 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 549                          BRx_PS_64                      |\
 550                          BRx_MS_GPCM_P                  |\
 551                          BRx_V)
 552
 553 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 554                          ORxG_CSNT                      |\
 555                          ORxG_ACS_DIV1                  |\
 556                          ORxG_SCY_5_CLK                 |\
 557                          ORxU_EHTR_8IDLE)
 558
 559 /* Bank 1 - Boot ROM
 560  */
 561 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 562                          BRx_PS_8                       |\
 563                          BRx_MS_GPCM_P                  |\
 564                          BRx_V)
 565
 566 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 567                          ORxG_CSNT                      |\
 568                          ORxG_ACS_DIV1                  |\
 569                          ORxG_SCY_5_CLK                 |\
 570                          ORxU_EHTR_8IDLE)
 571
 572 #endif /* CONFIG_BOOT_ROM */
 573
 574
 575 /* Bank 2 - 60x bus SDRAM
 576  */
 577 #ifndef CONFIG_SYS_RAMBOOT
 578 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 579                          BRx_PS_64                      |\
 580                          BRx_MS_SDRAM_P                 |\
 581                          BRx_V)
 582
 583 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 584
 585 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 586 #endif /* CONFIG_SYS_RAMBOOT */
 587
 588 /* Bank 3 - Dual Ported SRAM
 589  */
 590 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 591                          BRx_PS_16                      |\
 592                          BRx_MS_GPCM_P                  |\
 593                          BRx_V)
 594
 595 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
 596                          ORxG_CSNT                      |\
 597                          ORxG_ACS_DIV1                  |\
 598                          ORxG_SCY_7_CLK                 |\
 599                          ORxG_SETA)
 600
 601 /* Bank 4 - DiskOnChip
 602  */
 603 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 604                          BRx_PS_8                       |\
 605                          BRx_MS_GPCM_P                  |\
 606                          BRx_V)
 607
 608 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 609                          ORxG_CSNT                      |\
 610                          ORxG_ACS_DIV2                  |\
 611                          ORxG_SCY_9_CLK                 |\
 612                          ORxU_EHTR_8IDLE)
 613
 614 /* Bank 5 - FDC37C78 controller
 615  */
 616 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 617                          BRx_PS_8                         |\
 618                          BRx_MS_GPCM_P                    |\
 619                          BRx_V)
 620
 621 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
 622                          ORxG_ACS_DIV2                    |\
 623                          ORxG_SCY_10_CLK                  |\
 624                          ORxU_EHTR_8IDLE)
 625
 626 /* Bank 6 - Board control registers
 627  */
 628 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
 629                          BRx_PS_8                       |\
 630                          BRx_MS_GPCM_P                  |\
 631                          BRx_V)
 632
 633 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
 634                          ORxG_CSNT                      |\
 635                          ORxG_SCY_7_CLK)
 636
 637 /* Bank 7 - VME Extended Access Range
 638  */
 639 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 640                          BRx_PS_32                      |\
 641                          BRx_MS_GPCM_P                  |\
 642                          BRx_V)
 643
 644 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
 645                          ORxG_CSNT                      |\
 646                          ORxG_ACS_DIV1                  |\
 647                          ORxG_SCY_7_CLK                 |\
 648                          ORxG_SETA)
 649
 650 /* Bank 8 - VME Standard Access Range
 651  */
 652 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 653                          BRx_PS_16                      |\
 654                          BRx_MS_GPCM_P                  |\
 655                          BRx_V)
 656
 657 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
 658                          ORxG_CSNT                      |\
 659                          ORxG_ACS_DIV1                  |\
 660                          ORxG_SCY_7_CLK                 |\
 661                          ORxG_SETA)
 662
 663 /* Bank 9 - VME Short I/O Access Range
 664  */
 665 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 666                          BRx_PS_16                        |\
 667                          BRx_MS_GPCM_P                    |\
 668                          BRx_V)
 669
 670 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
 671                          ORxG_CSNT                        |\
 672                          ORxG_ACS_DIV1                    |\
 673                          ORxG_SCY_7_CLK                   |\
 674                          ORxG_SETA)
 675
 676 #endif  /* __CONFIG_H */