include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config_GEN860T.h - board specific configuration options
  11  */
  12
  13 #ifndef __CONFIG_GEN860T_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_MPC860
  20 #define CONFIG_GEN860T
  21
  22 #define CONFIG_SYS_TEXT_BASE            0x40000000
  23
  24 /*
  25  * Identify the board
  26  */
  27 #if !defined(CONFIG_SC)
  28 #define CONFIG_IDENT_STRING             " B2"
  29 #else
  30 #define CONFIG_IDENT_STRING             " SC"
  31 #endif
  32
  33 /*
  34  * Don't depend on the RTC clock to determine clock frequency -
  35  * the 860's internal rtc uses a 32.768 KHz clock which is
  36  * generated by the DS1337 - and the DS1337 clock can be turned off.
  37  */
  38 #if !defined(CONFIG_SC)
  39 #define CONFIG_8xx_GCLK_FREQ            66600000
  40 #else
  41 #define CONFIG_8xx_GCLK_FREQ            48000000
  42 #endif
  43
  44 /*
  45  * The RS-232 console port is on SMC1
  46  */
  47 #define CONFIG_8xx_CONS_SMC1
  48 #define CONFIG_BAUDRATE                 38400
  49
  50 /*
  51  * Print console information
  52  */
  53 #undef   CONFIG_SYS_CONSOLE_INFO_QUIET
  54
  55 /*
  56  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  57  */
  58 #define CONFIG_BOOTDELAY                                5
  59
  60 /*
  61  * Pass the clock frequency to the Linux kernel in units of MHz
  62  */
  63 #define CONFIG_CLOCKS_IN_MHZ
  64
  65 #define CONFIG_PREBOOT          \
  66         "echo;echo"
  67
  68 #undef  CONFIG_BOOTARGS
  69 #define CONFIG_BOOTCOMMAND      \
  70         "bootp;" \
  71         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  72         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  73         "bootm"
  74
  75 /*
  76  * Turn off echo for serial download by default.  Allow baud rate to be changed
  77  * for downloads
  78  */
  79 #undef  CONFIG_LOADS_ECHO
  80 #define CONFIG_SYS_LOADS_BAUD_CHANGE
  81
  82 /*
  83  * Turn off the watchdog timer
  84  */
  85 #undef  CONFIG_WATCHDOG
  86
  87 /*
  88  * Do not reboot if a panic occurs
  89  */
  90 #define CONFIG_PANIC_HANG
  91
  92 /*
  93  * Enable the status LED
  94  */
  95 #define CONFIG_STATUS_LED
  96
  97 /*
  98  * Reset address. We pick an address such that when an instruction
  99  * is executed at that address, a machine check exception occurs
 100  */
 101 #define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_SUBNETMASK
 107 #define CONFIG_BOOTP_GATEWAY
 108 #define CONFIG_BOOTP_HOSTNAME
 109 #define CONFIG_BOOTP_BOOTPATH
 110 #define CONFIG_BOOTP_BOOTFILESIZE
 111
 112
 113 /*
 114  * The GEN860T network interface uses the on-chip 10/100 FEC with
 115  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 116  * MII address is hardwired on the board to zero.
 117  */
 118 #define CONFIG_FEC_ENET
 119 #define CONFIG_SYS_DISCOVER_PHY
 120 #define CONFIG_MII
 121 #define CONFIG_MII_INIT                 1
 122 #define CONFIG_PHY_ADDR                 0
 123
 124 /*
 125  * Set default IP stuff just to get bootstrap entries into the
 126  * environment so that we can source the full default environment.
 127  */
 128 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 129 #define CONFIG_SERVERIP                                 10.0.4.201
 130 #define CONFIG_IPADDR                                   10.0.4.111
 131
 132 /*
 133  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 134  * the MPC860T I2C interface.
 135  */
 136 #define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
 137 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
 138 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
 139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
 140 #define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
 141
 142 /*
 143  * Enable I2C and select the hardware/software driver
 144  */
 145 #define CONFIG_HARD_I2C         1               /* CPM based I2C */
 146 #undef  CONFIG_SYS_I2C_SOFT                     /* Bit-banged I2C */
 147
 148 #ifdef CONFIG_HARD_I2C
 149 #define CONFIG_SYS_I2C_SPEED            100000  /* clock speed in Hz */
 150 #define CONFIG_SYS_I2C_SLAVE            0xFE    /* I2C slave address */
 151 #endif
 152
 153 #ifdef CONFIG_SYS_I2C_SOFT
 154 #define CONFIG_SYS_I2C
 155 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 156 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 157 #define PB_SCL          0x00000020              /* PB 26 */
 158 #define PB_SDA          0x00000010              /* PB 27 */
 159 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 160 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 161 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 162 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 163 #define I2C_SDA(bit)    if (bit) \
 164                                 immr->im_cpm.cp_pbdat |=  PB_SDA; \
 165                         else \
 166                                 immr->im_cpm.cp_pbdat &= ~PB_SDA
 167 #define I2C_SCL(bit)    if (bit) \
 168                                 immr->im_cpm.cp_pbdat |=  PB_SCL; \
 169                         else \
 170                                 immr->im_cpm.cp_pbdat &= ~PB_SCL
 171 #define I2C_DELAY       udelay(5) /* 1/4 I2C clock duration */
 172 #endif
 173
 174 /*
 175  * Allow environment overwrites by anyone
 176  */
 177 #define CONFIG_ENV_OVERWRITE
 178
 179 #if !defined(CONFIG_SC)
 180 /*
 181  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 182  * internal MPC860T circuit nodes were inadvertently left floating; this
 183  * causes KAPWR current in power down mode to be three orders of magnitude
 184  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 185  * reasonable battery can keep that kind RTC running during powerdown for any
 186  * length of time, so we use an external RTC on the I2C bus instead.
 187  */
 188 #define CONFIG_RTC_DS1337
 189 #define CONFIG_SYS_I2C_RTC_ADDR                         0x68
 190
 191 #else
 192 /*
 193  * No external RTC on SC variant, so we're stuck with the internal one.
 194  */
 195 #define CONFIG_RTC_MPC8xx
 196 #endif
 197
 198 /*
 199  * Power On Self Test support
 200  */
 201 #define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
 202                                                                 CONFIG_SYS_POST_MEMORY          | \
 203                                                                 CONFIG_SYS_POST_CPU             | \
 204                                                                 CONFIG_SYS_POST_UART            | \
 205                                                                 CONFIG_SYS_POST_SPR )
 206
 207
 208 /*
 209  * Command line configuration.
 210  */
 211 #include <config_cmd_default.h>
 212
 213 #define CONFIG_CMD_ASKENV
 214 #define CONFIG_CMD_DHCP
 215 #define CONFIG_CMD_I2C
 216 #define CONFIG_CMD_EEPROM
 217 #define CONFIG_CMD_REGINFO
 218 #define CONFIG_CMD_IMMAP
 219 #define CONFIG_CMD_ELF
 220 #define CONFIG_CMD_DATE
 221 #define CONFIG_CMD_FPGA
 222 #define CONFIG_CMD_MII
 223 #define CONFIG_CMD_BEDBUG
 224
 225 #ifdef CONFIG_POST
 226 #define CONFIG_CMD_DIAG
 227 #endif
 228
 229 /*
 230  * There is no IDE/PCMCIA hardware support on the board.
 231  */
 232 #undef  CONFIG_IDE_PCMCIA
 233 #undef  CONFIG_IDE_LED
 234 #undef  CONFIG_IDE_RESET
 235
 236 /*
 237  * Enable the call to misc_init_r() for miscellaneous platform
 238  * dependent initialization.
 239  */
 240 #define CONFIG_MISC_INIT_R
 241
 242 /*
 243  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 244  */
 245 #define CONFIG_LAST_STAGE_INIT
 246
 247 /*
 248  * Virtex2 FPGA configuration support
 249  */
 250 #define CONFIG_FPGA_COUNT               1
 251 #define CONFIG_FPGA
 252 #define CONFIG_FPGA_XILINX
 253 #define CONFIG_FPGA_VIRTEX2
 254 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 255
 256 /*
 257  * Verbose help from command monitor.
 258  */
 259 #define CONFIG_SYS_LONGHELP
 260 #if !defined(CONFIG_SC)
 261 #define CONFIG_SYS_PROMPT                       "B2> "
 262 #else
 263 #define CONFIG_SYS_PROMPT                       "SC> "
 264 #endif
 265
 266
 267 /*
 268  * Use the "hush" command parser
 269  */
 270 #define CONFIG_SYS_HUSH_PARSER
 271
 272 /*
 273  * Set buffer size for console I/O
 274  */
 275 #if defined(CONFIG_CMD_KGDB)
 276 #define CONFIG_SYS_CBSIZE                       1024
 277 #else
 278 #define CONFIG_SYS_CBSIZE                       256
 279 #endif
 280
 281 /*
 282  * Print buffer size
 283  */
 284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 285
 286 /*
 287  * Maximum number of arguments that a command can accept
 288  */
 289 #define CONFIG_SYS_MAXARGS                      16
 290
 291 /*
 292  * Boot argument buffer size
 293  */
 294 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 295
 296 /*
 297  * Default memory test range
 298  */
 299 #define CONFIG_SYS_MEMTEST_START        0x0100000
 300 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 301
 302 /*
 303  * Select the more full-featured memory test
 304  */
 305 #define CONFIG_SYS_ALT_MEMTEST
 306
 307 /*
 308  * Default load address
 309  */
 310 #define CONFIG_SYS_LOAD_ADDR            0x01000000
 311
 312 /*
 313  * Set decrementer frequency (1 ms ticks)
 314  */
 315 #define CONFIG_SYS_HZ                           1000
 316
 317 /*
 318  * Device memory map (after SDRAM remap to 0x0):
 319  *
 320  * CS           Device                          Base Addr       Size
 321  * ----------------------------------------------------
 322  * CS0*         Flash                           0x40000000      64 M
 323  * CS1*         SDRAM                           0x00000000      16 M
 324  * CS2*         Disk-On-Chip            0x50000000      32 K
 325  * CS3*         FPGA                            0x60000000      64 M
 326  * CS4*         SelectMap                       0x70000000      32 K
 327  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 328  * CS6*         Unused
 329  * CS7*         Unused
 330  * IMMR         860T Registers          0xfff00000
 331  */
 332
 333 /*
 334  * Base addresses and block sizes
 335  */
 336 #define CONFIG_SYS_IMMR                 0xFF000000
 337
 338 #define SDRAM_BASE                      0x00000000
 339 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 340
 341 #define FLASH_BASE                      0x40000000
 342 #define FLASH_SIZE                      (16 * 1024 * 1024)
 343
 344 #define DOC_BASE                        0x50000000
 345 #define DOC_SIZE                        (32 * 1024)
 346
 347 #define FPGA_BASE                       0x60000000
 348 #define FPGA_SIZE                       (64 * 1024 * 1024)
 349
 350 #define SELECTMAP_BASE          0x70000000
 351 #define SELECTMAP_SIZE          (32 * 1024)
 352
 353 #define M1553_BASE                      0x80000000
 354 #define M1553_SIZE                      (64 * 1024)
 355
 356 /*
 357  * Definitions for initial stack pointer and data area (in DPRAM)
 358  */
 359 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 360 #define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
 361 #define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
 362 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 363 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 364
 365 /*
 366  * Start addresses for the final memory configuration
 367  * (Set up by the startup code)
 368  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 369  */
 370 #define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
 371
 372 /*
 373  * FLASH organization
 374  */
 375 #define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
 376 #define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
 377 #define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
 378 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 379 #define CONFIG_SYS_MAX_FLASH_SECT               128
 380
 381 /*
 382  * The timeout values are for an entire chip and are in milliseconds.
 383  * Yes I know that the write timeout is huge.  Accroding to the
 384  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 385  * case VCC and temp after 100K programming cycles.  It works out
 386  * to 280 minutes (might as well be forever).
 387  */
 388 #define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
 389 #define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 390
 391 /*
 392  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 393  */
 394 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 395
 396 /*
 397  * Reserve memory for U-Boot.
 398  */
 399 #define CONFIG_SYS_MAX_UBOOT_SECTS              4
 400 #define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
 401 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 402
 403 /*
 404  * Select environment placement.  NOTE that u-boot.lds must
 405  * be edited if this is changed!
 406  */
 407 #undef  CONFIG_ENV_IS_IN_FLASH
 408 #define CONFIG_ENV_IS_IN_EEPROM
 409
 410 #if defined(CONFIG_ENV_IS_IN_EEPROM)
 411 #define CONFIG_ENV_SIZE                 (2 * 1024)
 412 #define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 413 #else
 414 #define CONFIG_ENV_SIZE                 0x1000
 415 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
 416
 417 /*
 418  * This ultimately gets passed right into the linker script, so we have to
 419  * use a number :(
 420  */
 421 #define CONFIG_ENV_OFFSET                       0x060000
 422 #endif
 423
 424 /*
 425  * Reserve memory for malloc()
 426  */
 427 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
 428
 429 /*
 430  * For booting Linux, the board info and command line data
 431  * have to be in the first 8 MB of memory, since this is
 432  * the maximum mapped by the Linux kernel during initialization.
 433  */
 434 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 435
 436 /*
 437  * Cache Configuration
 438  */
 439 #define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
 440 #if defined(CONFIG_CMD_KGDB)
 441 #define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
 442 #endif
 443
 444 /*------------------------------------------------------------------------
 445  * SYPCR - System Protection Control                                                    UM 11-9
 446  * -----------------------------------------------------------------------
 447  * SYPCR can only be written once after reset!
 448  *
 449  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 450  */
 451 #if defined(CONFIG_WATCHDOG)
 452 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 453                                           SYPCR_BMT     | \
 454                                           SYPCR_BME     | \
 455                                           SYPCR_SWF     | \
 456                                           SYPCR_SWE     | \
 457                                           SYPCR_SWRI    | \
 458                                           SYPCR_SWP               \
 459                                         )
 460 #else
 461 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 462                                           SYPCR_BMT     | \
 463                                           SYPCR_BME     | \
 464                                           SYPCR_SWF     | \
 465                                           SYPCR_SWP               \
 466                                         )
 467 #endif
 468
 469 /*-----------------------------------------------------------------------
 470  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 471  *-----------------------------------------------------------------------
 472  * Set debug pin mux, enable SPKROUT and GPLB5*.
 473  */
 474 #define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
 475                                           SIUMCR_DBPC11 | \
 476                                           SIUMCR_MLRC11 | \
 477                                           SIUMCR_GB5E     \
 478                                         )
 479
 480 /*-----------------------------------------------------------------------
 481  * TBSCR - Time Base Status and Control                                                 UM 11-26
 482  *-----------------------------------------------------------------------
 483  * Clear Reference Interrupt Status, Timebase freeze enabled
 484  */
 485 #define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
 486                                           TBSCR_REFB | \
 487                                           TBSCR_TBF        \
 488                                         )
 489
 490 /*-----------------------------------------------------------------------
 491  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 492  *-----------------------------------------------------------------------
 493  */
 494 #define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
 495                                           RTCSC_ALR | \
 496                                           RTCSC_RTF | \
 497                                           RTCSC_RTE       \
 498                                         )
 499
 500 /*-----------------------------------------------------------------------
 501  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 502  *-----------------------------------------------------------------------
 503  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 504  */
 505 #define CONFIG_SYS_PISCR        ( PISCR_PS              | \
 506                                           PISCR_PITF      \
 507                                         )
 508
 509 /*-----------------------------------------------------------------------
 510  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 511  *-----------------------------------------------------------------------
 512  * Reset PLL lock status sticky bit, timer expired status bit and timer
 513  * interrupt status bit. Set MF for 1:2:1 mode.
 514  */
 515 #define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 516                                           PLPRCR_SPLSS  | \
 517                                           PLPRCR_TEXPS  | \
 518                                           PLPRCR_TMIST    \
 519                                         )
 520
 521 /*-----------------------------------------------------------------------
 522  * SCCR - System Clock and reset Control Register                               UM 15-27
 523  *-----------------------------------------------------------------------
 524  * Set clock output, timebase and RTC source and divider,
 525  * power management and some other internal clocks
 526  */
 527 #define SCCR_MASK   SCCR_EBDF11
 528
 529 #if !defined(CONFIG_SC)
 530 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 531                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 532                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 533                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 534                                           SCCR_DFNL000          | \
 535                                           SCCR_DFNH000            \
 536                                         )
 537 #else
 538 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 539                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 540                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 541                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 542                                           SCCR_DFNL000          | \
 543                                           SCCR_DFNH000          | \
 544                                           SCCR_RTDIV            | \
 545                                           SCCR_RTSEL              \
 546                                         )
 547 #endif
 548
 549 /*-----------------------------------------------------------------------
 550  * DER - Debug Enable Register                                                                  UM 37-46
 551  *-----------------------------------------------------------------------
 552  * Mask all events that can cause entry into debug mode
 553  */
 554 #define CONFIG_SYS_DER                          0
 555
 556 /*
 557  * Initialize Memory Controller:
 558  *
 559  * BR0 and OR0 (FLASH memory)
 560  */
 561 #define FLASH_BASE0_PRELIM      FLASH_BASE
 562
 563 /*
 564  * Flash address mask
 565  */
 566 #define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
 567
 568 /*
 569  * FLASH timing:
 570  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 571  */
 572 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
 573                                                           OR_ACS_DIV2   | \
 574                                                           OR_BI                 | \
 575                                                           OR_SCY_2_CLK  | \
 576                                                           OR_TRLX               | \
 577                                                           OR_EHTR                 \
 578                                                         )
 579
 580 #define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
 581                                                   CONFIG_SYS_OR_TIMING_FLASH      \
 582                                                 )
 583
 584 #define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 585                                                   BR_MS_GPCM                                            | \
 586                                                   BR_PS_8                                                       | \
 587                                                   BR_V                                                            \
 588                                                 )
 589
 590 /*
 591  * SDRAM configuration
 592  */
 593 #define CONFIG_SYS_OR1_AM       0xfc000000
 594 #define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
 595                                           OR_CSNT_SAM                             \
 596                                         )
 597
 598 #define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
 599                                           BR_MS_UPMA                            | \
 600                                           BR_PS_32                                      | \
 601                                           BR_V                                            \
 602                                         )
 603
 604 /*
 605  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 606  * of 256 MBit SDRAM
 607  */
 608 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
 609
 610 /*
 611  * Periodic timer for refresh @ 33 MHz system clock
 612  */
 613 #define CONFIG_SYS_MAMR_PTA     64
 614
 615 /*
 616  * MAMR settings for SDRAM
 617  */
 618 #define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
 619                                                   MAMR_PTAE                             | \
 620                                                   MAMR_AMA_TYPE_1                       | \
 621                                                   MAMR_DSA_1_CYCL                       | \
 622                                                   MAMR_G0CLA_A10                        | \
 623                                                   MAMR_RLFA_1X                          | \
 624                                                   MAMR_WLFA_1X                          | \
 625                                                   MAMR_TLFA_4X                            \
 626                                                 )
 627
 628 /*
 629  * CS2* configuration for Disk On Chip:
 630  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 631  * no burst.
 632  */
 633 #define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 634                                                   OR_CSNT_SAM                           | \
 635                                                   OR_ACS_DIV2                           | \
 636                                                   OR_BI                                         | \
 637                                                   OR_SCY_2_CLK                          | \
 638                                                   OR_TRLX                                       | \
 639                                                   OR_EHTR                                         \
 640                                                 )
 641
 642 #define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
 643                                                   BR_PS_8                                       | \
 644                                                   BR_MS_GPCM                            | \
 645                                                   BR_V                                            \
 646                                                 )
 647
 648 /*
 649  * CS3* configuration for FPGA:
 650  * 33 MHz bus with SCY=15, no burst.
 651  * The FPGA uses TA and TEA to terminate bus cycles, but we
 652  * clear SETA and set the cycle length to a large number so that
 653  * the cycle will still complete even if there is a configuration
 654  * error that prevents TA from asserting on FPGA accesss.
 655  */
 656 #define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
 657                                                   OR_SCY_15_CLK                         | \
 658                                                   OR_BI                                   \
 659                                                 )
 660
 661 #define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
 662                                                   BR_PS_32                                      | \
 663                                                   BR_MS_GPCM                            | \
 664                                                   BR_V                                            \
 665                                                 )
 666 /*
 667  * CS4* configuration for FPGA SelectMap configuration interface.
 668  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 669  * of GCLK1_50
 670  */
 671 #define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 672                                                   OR_G5LS                                               | \
 673                                                   OR_BI                                                   \
 674                                                 )
 675
 676 #define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 677                                                   BR_PS_8                                               | \
 678                                                   BR_MS_UPMB                                    | \
 679                                                   BR_V                                                    \
 680                                                 )
 681
 682 /*
 683  * CS5* configuration for Mil-Std 1553 databus interface.
 684  * 33 MHz bus, GPCM, no burst.
 685  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 686  * but we clear SETA and set the cycle length to a large number so that
 687  * the cycle will still complete even if there is a configuration
 688  * error that prevents TA from asserting on FPGA accesss.
 689  */
 690 #define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
 691                                                   OR_SCY_15_CLK                         | \
 692                                                   OR_EHTR                                       | \
 693                                                   OR_TRLX                                       | \
 694                                                   OR_CSNT_SAM                           | \
 695                                                   OR_BI                                           \
 696                                                 )
 697
 698 #define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
 699                                                   BR_PS_16                                      | \
 700                                                   BR_MS_GPCM                            | \
 701                                                   BR_V                                            \
 702                                                 )
 703
 704 /*
 705  * FEC interrupt assignment
 706  */
 707 #define FEC_INTERRUPT   SIU_LEVEL1
 708
 709 /*
 710  * Sanity checks
 711  */
 712 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 713 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 714 #endif
 715
 716 #endif  /* __CONFIG_GEN860T_H */