include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config_GEN860T.h - board specific configuration options
  27  */
  28
  29 #ifndef __CONFIG_GEN860T_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_MPC860
  36 #define CONFIG_GEN860T
  37
  38 /*
  39  * Identify the board
  40  */
  41 #define CONFIG_IDENT_STRING                             " GEN860T"
  42
  43 /*
  44  * Don't depend on the RTC clock to determine clock frequency -
  45  * the 860's internal rtc uses a 32.768 KHz clock which is
  46  * generated by the DS1337 - and the DS1337 clock can be turned off.
  47  */
  48 #define CONFIG_8xx_GCLK_FREQ                    66600000
  49
  50 /*
  51  * The RS-232 console port is on SMC1
  52  */
  53 #define CONFIG_8xx_CONS_SMC1
  54 #define CONFIG_BAUDRATE                                 38400
  55
  56 /*
  57  * Set allowable console baud rates
  58  */
  59 #define CFG_BAUDRATE_TABLE                              { 9600,         \
  60                                                                                   19200,        \
  61                                                                                   38400,        \
  62                                                                                   57600,        \
  63                                                                                   115200,       \
  64                                                                                 }
  65
  66 /*
  67  * Print console information
  68  */
  69 #undef   CFG_CONSOLE_INFO_QUIET
  70
  71 /*
  72  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  73  */
  74 #define CONFIG_BOOTDELAY                                5
  75
  76 /*
  77  * Pass the clock frequency to the Linux kernel in units of MHz
  78  */
  79 #define CONFIG_CLOCKS_IN_MHZ
  80
  81 #define CONFIG_PREBOOT          \
  82         "echo;echo"
  83
  84 #undef  CONFIG_BOOTARGS
  85 #define CONFIG_BOOTCOMMAND      \
  86         "bootp;" \
  87         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  88         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  89         "bootm"
  90
  91 /*
  92  * Turn off echo for serial download by default.  Allow baud rate to be changed
  93  * for downloads
  94  */
  95 #undef  CONFIG_LOADS_ECHO
  96 #define CFG_LOADS_BAUD_CHANGE
  97
  98 /*
  99  * Set default load address for tftp network downloads
 100  */
 101 #define CFG_TFTP_LOADADDR                               0x01000000
 102
 103 /*
 104  * Turn off the watchdog timer
 105  */
 106 #undef  CONFIG_WATCHDOG
 107
 108 /*
 109  * Do not reboot if a panic occurs
 110  */
 111 #define CONFIG_PANIC_HANG
 112
 113 /*
 114  * Enable the status LED
 115  */
 116 #define CONFIG_STATUS_LED
 117
 118 /*
 119  * Reset address. We pick an address such that when an instruction
 120  * is executed at that address, a machine check exception occurs
 121  */
 122 #define CFG_RESET_ADDRESS                               ((ulong) -1)
 123
 124 /*
 125  * BOOTP options
 126  */
 127 #define CONFIG_BOOTP_MASK                               ( CONFIG_BOOTP_DEFAULT          | \
 128                                                                                   CONFIG_BOOTP_BOOTFILESIZE   \
 129                                                                                 )
 130
 131 /*
 132  * The GEN860T network interface uses the on-chip 10/100 FEC with
 133  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 134  * MII address is hardwired on the board to zero.
 135  */
 136 #define CONFIG_FEC_ENET
 137 #define CFG_DISCOVER_PHY
 138 #define CONFIG_MII
 139 #define CONFIG_PHY_ADDR                         0
 140
 141 /*
 142  * Set default IP stuff just to get bootstrap entries into the
 143  * environment so that we can autoscript the full default environment.
 144  */
 145 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 146 #define CONFIG_SERVERIP                                 10.0.4.200
 147 #define CONFIG_IPADDR                                   10.0.4.111
 148
 149 /*
 150  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 151  * the MPC860T I2C interface.
 152  */
 153 #define CFG_I2C_EEPROM_ADDR                             0x50
 154 #define CFG_EEPROM_PAGE_WRITE_BITS              6               /* 64 byte pages                */
 155 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  12              /* 10 mS w/ 20% margin  */
 156 #define CFG_I2C_EEPROM_ADDR_LEN                 2               /* need 16 bit address  */
 157 #define CFG_ENV_EEPROM_SIZE                             (32 * 1024)
 158
 159 #undef  CONFIG_HARD_I2C
 160 #define CONFIG_SOFT_I2C
 161
 162 /*
 163  * Configure software I2C support (taken from IP860 BSP).
 164  * The I2C bus is connected to the GEN860T's 'dedicated' I2C
 165  * pins, i.e. PB26 and PB27
 166  */
 167 #define PB_SCL                          0x00000020              /* PB 26                                        */
 168 #define PB_SDA                          0x00000010              /* PB 27                                        */
 169
 170 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 171 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 172 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 173 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 174 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 175                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 176 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 177                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 178 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
 179
 180 #define CFG_I2C_SPEED           100000                  /* clock speed in Hz            */
 181 #define CFG_I2C_SLAVE           0xFE                    /* I2C slave address            */
 182
 183 /*
 184  * Allow environment overwrites by anyone
 185  */
 186 #define CONFIG_ENV_OVERWRITE
 187
 188 /*
 189  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 190  * internal MPC860T circuit nodes were inadvertently left floating; this
 191  * causes KAPWR current in power down mode to be three orders of magnitude
 192  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 193  * reasonable battery can keep that kind RTC running during powerdown for any
 194  * length of time, so we use an external RTC on the I2C bus instead.
 195  */
 196 #undef  CONFIG_RTC_MPC8xx
 197 #define CONFIG_RTC_DS1337
 198 #define CFG_I2C_RTC_ADDR                                0x68
 199
 200 /*
 201  * Allow partial commands to be matched to uniqueness.
 202  */
 203 #define CFG_MATCH_PARTIAL_CMD
 204
 205 /*
 206  * List of available monitor commands.  Use the system default list
 207  * plus add some of the "non-standard" commands back in.
 208  * See ./cmd_confdefs.h
 209  */
 210 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 211                                                                 CFG_CMD_ASKENV  | \
 212                                                                 CFG_CMD_DHCP    | \
 213                                                                 CFG_CMD_I2C             | \
 214                                                                 CFG_CMD_DOC             | \
 215                                                                 CFG_CMD_EEPROM  | \
 216                                                                 CFG_CMD_REGINFO | \
 217                                                                 CFG_CMD_IMMAP   | \
 218                                                                 CFG_CMD_ELF             | \
 219                                                                 CFG_CMD_DATE    | \
 220                                                                 CFG_CMD_DATE    | \
 221                                                                 CFG_CMD_FPGA    | \
 222                                                                 CFG_CMD_MII     | \
 223                                                                 CFG_CMD_BEDBUG  \
 224                                                       )
 225
 226 /*
 227  * There is no IDE/PCMCIA hardware support on the board.
 228  */
 229 #undef  CONFIG_IDE_PCMCIA
 230 #undef  CONFIG_IDE_LED
 231 #undef  CONFIG_IDE_RESET
 232
 233 /*
 234  * Enable the call to misc_init_r() for miscellaneous platform
 235  * dependent initialization.
 236  */
 237 #define CONFIG_MISC_INIT_R
 238
 239 /*
 240  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 241  */
 242 #define CONFIG_LAST_STAGE_INIT
 243
 244 /*
 245  * Virtex2 FPGA configuration support
 246  */
 247 #define CONFIG_FPGA_COUNT               1
 248 #define CONFIG_FPGA                             CFG_XILINX_VIRTEX2
 249 #define CFG_FPGA_PROG_FEEDBACK
 250
 251
 252 /************************************************************************
 253  * This must be included AFTER the definition of any CONFIG_COMMANDS
 254  */
 255 #include <cmd_confdefs.h>
 256
 257 /*
 258  * Verbose help from command monitor.
 259  */
 260 #define CFG_LONGHELP
 261 #define CFG_PROMPT                      "gen860t> "
 262
 263 /*
 264  * Use the "hush" command parser
 265  */
 266 #define CFG_HUSH_PARSER
 267 #define CFG_PROMPT_HUSH_PS2     "> "
 268
 269 /*
 270  * Set buffer size for console I/O
 271  */
 272 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 273 #define CFG_CBSIZE                      1024
 274 #else
 275 #define CFG_CBSIZE                      256
 276 #endif
 277
 278 /*
 279  * Print buffer size
 280  */
 281 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 282
 283 /*
 284  * Maximum number of arguments that a command can accept
 285  */
 286 #define CFG_MAXARGS                     16
 287
 288 /*
 289  * Boot argument buffer size
 290  */
 291 #define CFG_BARGSIZE            CFG_CBSIZE
 292
 293 /*
 294  * Default memory test range
 295  */
 296 #define CFG_MEMTEST_START       0x0100000
 297 #define CFG_MEMTEST_END         (CFG_MEMTEST_START  + (128 * 1024))
 298
 299 /*
 300  * Select the more full-featured memory test
 301  */
 302 #define CFG_ALT_MEMTEST
 303
 304 /*
 305  * Default load address
 306  */
 307 #define CFG_LOAD_ADDR           0x01000000
 308
 309 /*
 310  * Set decrementer frequency (1 ms ticks)
 311  */
 312 #define CFG_HZ                          1000
 313
 314 /*
 315  * Device memory map (after SDRAM remap to 0x0):
 316  *
 317  * CS           Device                          Base Addr       Size
 318  * ----------------------------------------------------
 319  * CS0*         Flash                           0x40000000      64 M
 320  * CS1*         SDRAM                           0x00000000      16 M
 321  * CS2*         Disk-On-Chip            0x50000000      32 K
 322  * CS3*         FPGA                            0x60000000      64 M
 323  * CS4*         SelectMap                       0x70000000      32 K
 324  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 325  * CS6*         Unused
 326  * CS7*         Unused
 327  * IMMR         860T Registers          0xfff00000
 328  */
 329
 330 /*
 331  * Base addresses and block sizes
 332  */
 333 #define CFG_IMMR                        0xFF000000
 334
 335 #define SDRAM_BASE                      0x00000000
 336 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 337
 338 #define FLASH_BASE                      0x40000000
 339 #define FLASH_SIZE                      (16 * 1024 * 1024)
 340
 341 #define DOC_BASE                        0x50000000
 342 #define DOC_SIZE                        (32 * 1024)
 343
 344 #define FPGA_BASE                       0x60000000
 345 #define FPGA_SIZE                       (64 * 1024 * 1024)
 346
 347 #define SELECTMAP_BASE          0x70000000
 348 #define SELECTMAP_SIZE          (32 * 1024)
 349
 350 #define M1553_BASE                      0x80000000
 351 #define M1553_SIZE                      (64 * 1024)
 352
 353 /*
 354  * Definitions for initial stack pointer and data area (in DPRAM)
 355  */
 356 #define CFG_INIT_RAM_ADDR               CFG_IMMR
 357 #define CFG_INIT_RAM_END                0x2F00  /* End of used area in DPRAM            */
 358 #define CFG_INIT_DATA_SIZE              64      /* # bytes reserved for initial data*/
 359 #define CFG_GBL_DATA_OFFSET             (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 360 #define CFG_INIT_SP_OFFSET              CFG_GBL_DATA_OFFSET
 361
 362 /*
 363  * Start addresses for the final memory configuration
 364  * (Set up by the startup code)
 365  * Please note that CFG_SDRAM_BASE _must_ start at 0
 366  */
 367 #define CFG_SDRAM_BASE                  SDRAM_BASE
 368
 369 /*
 370  * FLASH organization
 371  */
 372 #define CFG_FLASH_BASE                  FLASH_BASE
 373 #define CFG_FLASH_SIZE                  FLASH_SIZE
 374 #define CFG_FLASH_SECT_SIZE             (128 * 1024)
 375 #define CFG_MAX_FLASH_BANKS             1
 376 #define CFG_MAX_FLASH_SECT              128
 377
 378 /*
 379  * The timeout values are for an entire chip and are in milliseconds.
 380  * Yes I know that the write timeout is huge.  Accroding to the
 381  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 382  * case VCC and temp after 100K programming cycles.  It works out
 383  * to 280 minutes (might as well be forever).
 384  */
 385 #define CFG_FLASH_ERASE_TOUT    (CFG_MAX_FLASH_SECT * 5000)
 386 #define CFG_FLASH_WRITE_TOUT    (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
 387
 388 /*
 389  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 390  */
 391 #define CFG_DIRECT_FLASH_TFTP
 392
 393 /*
 394  * Reserve memory for U-Boot.
 395  */
 396 #define CFG_MAX_U_BOOT_SECT     3
 397
 398 #if defined(DEBUG)
 399 #define CFG_MONITOR_LEN         (512 * 1024)
 400 #else
 401 #define CFG_MONITOR_LEN         (256 * 1024)
 402 #endif
 403
 404 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 405
 406 /*
 407  * Select environment placement.  NOTE that u-boot.lds must
 408  * be edited if this is changed!
 409  */
 410 #undef  CFG_ENV_IS_IN_FLASH
 411 #define CFG_ENV_IS_IN_EEPROM
 412
 413 #if defined(CFG_ENV_IS_IN_EEPROM)
 414 #define CFG_ENV_SIZE                    (2 * 1024)
 415 #define CFG_ENV_OFFSET                  (CFG_ENV_EEPROM_SIZE - (8 * 1024))
 416 #else
 417 #define CFG_ENV_SIZE                    (4 * 1024)
 418 #define CFG_ENV_OFFSET                  (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE)
 419 #endif
 420
 421 /*
 422  * Reserve memory for malloc()
 423  */
 424 #define CFG_MALLOC_LEN          (128 * 1024)
 425
 426 /*
 427  * For booting Linux, the board info and command line data
 428  * have to be in the first 8 MB of memory, since this is
 429  * the maximum mapped by the Linux kernel during initialization.
 430  */
 431 #define CFG_BOOTMAPSZ           (8 * 1024 * 1024)
 432
 433 /*
 434  * Cache Configuration
 435  */
 436 #define CFG_CACHELINE_SIZE              16      /* For all MPC8xx CPUs                          */
 437 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 438 #define CFG_CACHELINE_SHIFT             4       /* log base 2 of above value            */
 439 #endif
 440
 441 /*------------------------------------------------------------------------
 442  * SYPCR - System Protection Control                            UM 11-9
 443  * -----------------------------------------------------------------------
 444  * SYPCR can only be written once after reset!
 445  *
 446  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 447  */
 448 #if defined(CONFIG_WATCHDOG)
 449 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 450                                           SYPCR_BMT     | \
 451                                           SYPCR_BME     | \
 452                                           SYPCR_SWF     | \
 453                                           SYPCR_SWE     | \
 454                                           SYPCR_SWRI    | \
 455                                           SYPCR_SWP               \
 456                                         )
 457 #else
 458 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 459                                           SYPCR_BMT     | \
 460                                           SYPCR_BME     | \
 461                                           SYPCR_SWF     | \
 462                                           SYPCR_SWP               \
 463                                         )
 464 #endif
 465
 466 /*-----------------------------------------------------------------------
 467  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 468  *-----------------------------------------------------------------------
 469  * Set debug pin mux, enable SPKROUT and GPLB5*.
 470  */
 471 #define CFG_SIUMCR      ( SIUMCR_DBGC11 | \
 472                                           SIUMCR_DBPC11 | \
 473                                           SIUMCR_MLRC11 | \
 474                                           SIUMCR_GB5E     \
 475                                         )
 476
 477 /*-----------------------------------------------------------------------
 478  * TBSCR - Time Base Status and Control                                                 UM 11-26
 479  *-----------------------------------------------------------------------
 480  * Clear Reference Interrupt Status, Timebase freeze enabled
 481  */
 482 #define CFG_TBSCR       ( TBSCR_REFA | \
 483                                           TBSCR_REFB | \
 484                                           TBSCR_TBF        \
 485                                         )
 486
 487 /*-----------------------------------------------------------------------
 488  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 489  *-----------------------------------------------------------------------
 490  */
 491 #define CFG_RTCSC       ( RTCSC_SEC     | \
 492                                           RTCSC_ALR | \
 493                                           RTCSC_RTF | \
 494                                           RTCSC_RTE       \
 495                                         )
 496
 497 /*-----------------------------------------------------------------------
 498  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 499  *-----------------------------------------------------------------------
 500  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 501  */
 502 #define CFG_PISCR       ( PISCR_PS              | \
 503                                           PISCR_PITF      \
 504                                         )
 505
 506 /*-----------------------------------------------------------------------
 507  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 508  *-----------------------------------------------------------------------
 509  * Reset PLL lock status sticky bit, timer expired status bit and timer
 510  * interrupt status bit. Set MF for 1:2:1 mode.
 511  */
 512 #define CFG_PLPRCR      ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 513                                           PLPRCR_SPLSS  | \
 514                                           PLPRCR_TEXPS  | \
 515                                           PLPRCR_TMIST    \
 516                                         )
 517
 518 /*-----------------------------------------------------------------------
 519  * SCCR - System Clock and reset Control Register                               UM 15-27
 520  *-----------------------------------------------------------------------
 521  * Set clock output, timebase and RTC source and divider,
 522  * power management and some other internal clocks
 523  */
 524 #define SCCR_MASK   SCCR_EBDF11
 525
 526 #define CFG_SCCR        ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 527                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 528                                           SCCR_DFSYNC00         |       /* SYNCLK / 1 (normal)  */ \
 529                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 530                                           SCCR_DFNL000          | \
 531                                           SCCR_DFNH000            \
 532                                         )
 533
 534 /*-----------------------------------------------------------------------
 535  * DER - Debug Enable Register                                                                  UM 37-46
 536  *-----------------------------------------------------------------------
 537  * Mask all events that can cause entry into debug mode
 538  */
 539 #define CFG_DER                         0
 540
 541 /*
 542  * Initialize Memory Controller:
 543  *
 544  * BR0 and OR0 (FLASH memory)
 545  */
 546 #define FLASH_BASE0_PRELIM      FLASH_BASE
 547
 548 /*
 549  * Flash address mask
 550  */
 551 #define CFG_PRELIM_OR_AM        0xfe000000
 552
 553 /*
 554  * FLASH timing:
 555  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 556  */
 557 #define CFG_OR_TIMING_FLASH     ( OR_CSNT_SAM   | \
 558                                                           OR_ACS_DIV2   | \
 559                                                           OR_BI                 | \
 560                                                           OR_SCY_2_CLK  | \
 561                                                           OR_TRLX               | \
 562                                                           OR_EHTR                 \
 563                                                         )
 564
 565 #define CFG_OR0_PRELIM  ( CFG_PRELIM_OR_AM              | \
 566                                                   CFG_OR_TIMING_FLASH     \
 567                                                 )
 568
 569 #define CFG_BR0_PRELIM  ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 570                                                   BR_MS_GPCM                                            | \
 571                                                   BR_PS_8                                                       | \
 572                                                   BR_V                                                            \
 573                                                 )
 574
 575 /*
 576  * SDRAM configuration
 577  */
 578 #define CFG_OR1_AM      0xfc000000
 579 #define CFG_OR1         ( (CFG_OR1_AM & OR_AM_MSK)      | \
 580                                           OR_CSNT_SAM                             \
 581                                         )
 582
 583 #define CFG_BR1         ( (SDRAM_BASE & BR_BA_MSK)      | \
 584                                           BR_MS_UPMA                            | \
 585                                           BR_PS_32                                      | \
 586                                           BR_V                                            \
 587                                         )
 588
 589 /*
 590  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 591  * of 256 MBit SDRAM
 592  */
 593 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16
 594
 595 /*
 596  * Periodic timer for refresh @ 33 MHz system clock
 597  */
 598 #define CFG_MAMR_PTA    64
 599
 600 /*
 601  * MAMR settings for SDRAM
 602  */
 603 #define CFG_MAMR_8COL   ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)      | \
 604                                                   MAMR_PTAE                             | \
 605                                                   MAMR_AMA_TYPE_1                       | \
 606                                                   MAMR_DSA_1_CYCL                       | \
 607                                                   MAMR_G0CLA_A10                        | \
 608                                                   MAMR_RLFA_1X                          | \
 609                                                   MAMR_WLFA_1X                          | \
 610                                                   MAMR_TLFA_4X                            \
 611                                                 )
 612
 613 /*
 614  * CS2* configuration for Disk On Chip:
 615  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 616  * no burst.
 617  */
 618 #define CFG_OR2_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 619                                                   OR_CSNT_SAM                           | \
 620                                                   OR_ACS_DIV2                           | \
 621                                                   OR_BI                                         | \
 622                                                   OR_SCY_2_CLK                          | \
 623                                                   OR_TRLX                                       | \
 624                                                   OR_EHTR                                         \
 625                                                 )
 626
 627 #define CFG_BR2_PRELIM  ( (DOC_BASE & BR_BA_MSK)        | \
 628                                                   BR_PS_8                                       | \
 629                                                   BR_MS_GPCM                            | \
 630                                                   BR_V                                            \
 631                                                 )
 632
 633 /*
 634  * CS3* configuration for FPGA:
 635  * 33 MHz bus with SCY=15, no burst.
 636  * The FPGA uses TA and TEA to terminate bus cycles, but we
 637  * clear SETA and set the cycle length to a large number so that
 638  * the cycle will still complete even if there is a configuration
 639  * error that prevents TA from asserting on FPGA accesss.
 640  */
 641 #define CFG_OR3_PRELIM  ( (0xfc000000 & OR_AM_MSK)  | \
 642                                                   OR_SCY_15_CLK                         | \
 643                                                   OR_BI                                           \
 644                                                 )
 645
 646 #define CFG_BR3_PRELIM  ( (FPGA_BASE & BR_BA_MSK)       | \
 647                                                   BR_PS_32                                      | \
 648                                                   BR_MS_GPCM                            | \
 649                                                   BR_V                                            \
 650                                                 )
 651 /*
 652  * CS4* configuration for FPGA SelectMap configuration interface.
 653  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 654  * of GCLK1_50
 655  */
 656 #define CFG_OR4_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 657                                                   OR_G5LS                                               | \
 658                                                   OR_BI                                                   \
 659                                                 )
 660
 661 #define CFG_BR4_PRELIM  ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 662                                                   BR_PS_8                                               | \
 663                                                   BR_MS_UPMB                                    | \
 664                                                   BR_V                                                    \
 665                                                 )
 666
 667 /*
 668  * CS5* configuration for Mil-Std 1553 databus interface.
 669  * 33 MHz bus, GPCM, no burst.
 670  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 671  * but we clear SETA and set the cycle length to a large number so that
 672  * the cycle will still complete even if there is a configuration
 673  * error that prevents TA from asserting on FPGA accesss.
 674  */
 675 #define CFG_OR5_PRELIM  ( (0xffff0000 & OR_AM_MSK)  | \
 676                                                   OR_SCY_15_CLK                         | \
 677                                                   OR_EHTR                                       | \
 678                                                   OR_TRLX                                       | \
 679                                                   OR_CSNT_SAM                           | \
 680                                                   OR_BI                                           \
 681                                                 )
 682
 683 #define CFG_BR5_PRELIM  ( (M1553_BASE & BR_BA_MSK)      | \
 684                                                   BR_PS_16                                      | \
 685                                                   BR_MS_GPCM                            | \
 686                                                   BR_V                                            \
 687                                                 )
 688
 689 /*
 690  * Boot Flags
 691  */
 692 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 693 #define BOOTFLAG_WARM   0x02    /* Software reboot                                      */
 694
 695 /*
 696  * Disk On Chip (millenium) configuration
 697  */
 698 #define CFG_MAX_DOC_DEVICE      1
 699 #undef  CFG_DOC_SUPPORT_2000
 700 #define CFG_DOC_SUPPORT_MILLENNIUM
 701 #undef  CFG_DOC_PASSIVE_PROBE
 702
 703 /*
 704  * FEC interrupt assignment
 705  */
 706 #define FEC_INTERRUPT   SIU_LEVEL1
 707
 708 /*
 709  * Sanity checks
 710  */
 711 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 712 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 713 #endif
 714
 715 #endif  /* __CONFIG_GEN860T_H */
 716
 717 /* vim: set ts=4 tw=78 ai shiftwidth=4: */