3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
39 #define CONFIG_PM826 1 /* ...on a PM8260 module */
41 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
43 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
47 #undef CONFIG_BOOTARGS
48 #define CONFIG_BOOTCOMMAND \
50 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
51 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
54 /* enable I2C and select the hardware/software driver */
55 #undef CONFIG_HARD_I2C
56 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
57 # define CFG_I2C_SPEED 50000
58 # define CFG_I2C_SLAVE 0xFE
60 * Software (bit-bang) I2C driver configuration
62 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
63 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
64 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
65 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
66 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
67 else iop->pdat &= ~0x00010000
68 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
69 else iop->pdat &= ~0x00020000
70 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
73 #define CONFIG_RTC_PCF8563
74 #define CFG_I2C_RTC_ADDR 0x51
77 * select serial console configuration
79 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
80 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
83 * if CONFIG_CONS_NONE is defined, then the serial console routines must
84 * defined elsewhere (for example, on the cogent platform, there are serial
85 * ports on the motherboard which are used for the serial console - see
86 * cogent/cma101/serial.[ch]).
88 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
89 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
90 #undef CONFIG_CONS_NONE /* define if console on something else*/
91 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
94 * select ethernet configuration
96 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
97 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
100 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
101 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
102 * from CONFIG_COMMANDS to remove support for networking.
104 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
105 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
106 #undef CONFIG_ETHER_NONE /* define if ether on something else */
107 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
109 #if (CONFIG_ETHER_INDEX == 1)
113 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
114 * - Enable Full Duplex in FSMR
116 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
117 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
118 # define CFG_CPMFCR_RAMTYPE 0
119 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
121 #endif /* CONFIG_ETHER_INDEX */
123 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
124 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
126 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
127 #define CONFIG_BAUDRATE 230400
129 #define CONFIG_BAUDRATE 9600
132 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
133 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
135 #undef CONFIG_WATCHDOG /* watchdog disabled */
137 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
139 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
146 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
147 #include <cmd_confdefs.h>
150 * Disk-On-Chip configuration
153 #define CFG_DOC_SHORT_TIMEOUT
154 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
156 #define CFG_DOC_SUPPORT_2000
157 #define CFG_DOC_SUPPORT_MILLENNIUM
160 * Miscellaneous configurable options
162 #define CFG_LONGHELP /* undef to save memory */
163 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
164 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
165 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
167 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
169 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
170 #define CFG_MAXARGS 16 /* max number of command args */
171 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
173 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
174 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
176 #define CFG_LOAD_ADDR 0x100000 /* default load address */
178 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
180 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
182 #define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization.
189 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
191 /*-----------------------------------------------------------------------
192 * Flash and Boot ROM mapping
195 #define CFG_BOOTROM_BASE 0x60000000
196 #define CFG_BOOTROM_SIZE 0x00080000
197 #define CFG_FLASH0_BASE 0x40000000
198 #define CFG_FLASH0_SIZE 0x02000000
199 #define CFG_DOC_BASE 0x60000000
200 #define CFG_DOC_SIZE 0x00100000
203 /* Flash bank size (for preliminary settings)
205 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
207 /*-----------------------------------------------------------------------
210 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
211 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
213 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
214 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
217 /* Start port with environment in flash; switch to EEPROM later */
218 #define CFG_ENV_IS_IN_FLASH 1
219 #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
220 #define CFG_ENV_SIZE 0x40000
221 #define CFG_ENV_SECT_SIZE 0x40000
223 /* Final version: environment in EEPROM */
224 #define CFG_ENV_IS_IN_EEPROM 1
225 #define CFG_I2C_EEPROM_ADDR 0x58
226 #define CFG_I2C_EEPROM_ADDR_LEN 1
227 #define CFG_EEPROM_PAGE_WRITE_BITS 4
228 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
229 #define CFG_ENV_OFFSET 0
230 #define CFG_ENV_SIZE 2048
233 /*-----------------------------------------------------------------------
234 * Hard Reset Configuration Words
236 * if you change bits in the HRCW, you must also change the CFG_*
237 * defines for the various registers affected by the HRCW e.g. changing
238 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
240 #if defined(CONFIG_BOOT_ROM)
241 #define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
243 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
246 /* no slaves so just fill with zeros */
247 #define CFG_HRCW_SLAVE1 0
248 #define CFG_HRCW_SLAVE2 0
249 #define CFG_HRCW_SLAVE3 0
250 #define CFG_HRCW_SLAVE4 0
251 #define CFG_HRCW_SLAVE5 0
252 #define CFG_HRCW_SLAVE6 0
253 #define CFG_HRCW_SLAVE7 0
255 /*-----------------------------------------------------------------------
256 * Internal Memory Mapped Register
258 #define CFG_IMMR 0xF0000000
260 /*-----------------------------------------------------------------------
261 * Definitions for initial stack pointer and data area (in DPRAM)
263 #define CFG_INIT_RAM_ADDR CFG_IMMR
264 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
265 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
266 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
267 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
269 /*-----------------------------------------------------------------------
270 * Start addresses for the final memory configuration
271 * (Set up by the startup code)
272 * Please note that CFG_SDRAM_BASE _must_ start at 0
274 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
275 * is mapped at SDRAM_BASE2_PRELIM.
277 #define CFG_SDRAM_BASE 0x00000000
278 #define CFG_FLASH_BASE CFG_FLASH0_BASE
279 #define CFG_MONITOR_BASE TEXT_BASE
280 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
281 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
283 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
288 * Internal Definitions
292 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
293 #define BOOTFLAG_WARM 0x02 /* Software reboot */
296 /*-----------------------------------------------------------------------
297 * Cache Configuration
299 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
300 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
304 /*-----------------------------------------------------------------------
305 * HIDx - Hardware Implementation-dependent Registers 2-11
306 *-----------------------------------------------------------------------
307 * HID0 also contains cache control - initially enable both caches and
308 * invalidate contents, then the final state leaves only the instruction
309 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
310 * but Soft reset does not.
312 * HID1 has only read-only information - nothing to set.
314 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
316 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
319 /*-----------------------------------------------------------------------
320 * RMR - Reset Mode Register 5-5
321 *-----------------------------------------------------------------------
322 * turn on Checkstop Reset Enable
324 #define CFG_RMR RMR_CSRE
326 /*-----------------------------------------------------------------------
327 * BCR - Bus Configuration 4-25
328 *-----------------------------------------------------------------------
331 #define BCR_APD01 0x10000000
332 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
334 /*-----------------------------------------------------------------------
335 * SIUMCR - SIU Module Configuration 4-31
336 *-----------------------------------------------------------------------
339 #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
341 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
345 /*-----------------------------------------------------------------------
346 * SYPCR - System Protection Control 4-35
347 * SYPCR can only be written once after reset!
348 *-----------------------------------------------------------------------
349 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
351 #if defined(CONFIG_WATCHDOG)
352 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
353 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
355 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
356 SYPCR_SWRI|SYPCR_SWP)
357 #endif /* CONFIG_WATCHDOG */
359 /*-----------------------------------------------------------------------
360 * TMCNTSC - Time Counter Status and Control 4-40
361 *-----------------------------------------------------------------------
362 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
363 * and enable Time Counter
365 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
367 /*-----------------------------------------------------------------------
368 * PISCR - Periodic Interrupt Status and Control 4-42
369 *-----------------------------------------------------------------------
370 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
373 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
375 /*-----------------------------------------------------------------------
376 * SCCR - System Clock Control 9-8
377 *-----------------------------------------------------------------------
379 #define CFG_SCCR (SCCR_DFBRG01)
381 /*-----------------------------------------------------------------------
382 * RCCR - RISC Controller Configuration 13-7
383 *-----------------------------------------------------------------------
388 * Init Memory Controller:
390 * Bank Bus Machine PortSz Device
391 * ---- --- ------- ------ ------
392 * 0 60x GPCM 64 bit FLASH
393 * 1 60x SDRAM 64 bit SDRAM
394 * 2 Local SDRAM 32 bit SDRAM
398 /* Initialize SDRAM on local bus
400 #define CFG_INIT_LOCAL_SDRAM
403 /* Minimum mask to separate preliminary
404 * address ranges for CS[0:2]
406 #define CFG_MIN_AM_MASK 0xC0000000
408 #define CFG_MPTPR 0x1F00
410 #define CFG_MRS_OFFS 0x00000000
413 #if defined(CONFIG_BOOT_ROM)
415 * Bank 0 - Boot ROM (8 bit wide)
417 #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
422 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
430 * Bank 1 - Flash (64 bit wide)
432 #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
437 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
444 #else /* ! CONFIG_BOOT_ROM */
447 * Bank 0 - Flash (64 bit wide)
449 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
454 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
462 * Bank 1 - Disk-On-Chip
464 #define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
469 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
476 #endif /* CONFIG_BOOT_ROM */
480 #define CFG_PSRT 0x0F
482 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
487 /* SDRAM initialization values for 8-column chips
489 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
491 ORxS_ROWST_PBI0_A9 |\
494 #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
495 PSDMR_BSMA_A14_A16 |\
496 PSDMR_SDA10_PBI0_A10 |\
504 /* SDRAM initialization values for 9-column chips
506 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
508 ORxS_ROWST_PBI0_A7 |\
511 #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
512 PSDMR_BSMA_A13_A15 |\
513 PSDMR_SDA10_PBI0_A9 |\
521 #define CFG_OR2_PRELIM CFG_OR2_9COL
522 #define CFG_PSDMR CFG_PSDMR_9COL
524 #endif /* CFG_RAMBOOT */
526 #endif /* __CONFIG_H */