include/configs/SIMPC8313.h

   1 /*
   2  * Copyright (C) Sheldon Instruments, Inc. 2008
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 /*
   7  * simpc8313 board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_NAND_U_BOOT
  17
  18 #define CONFIG_E300                     1
  19 #define CONFIG_MPC83xx                  1
  20 #define CONFIG_MPC831x                  1
  21 #define CONFIG_MPC8313                  1
  22
  23 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
  24 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
  25 #define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
  26 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
  27 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  28
  29 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  31
  32 #ifdef CONFIG_NAND_SPL
  33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  34 #else
  35 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  36 #endif
  37
  38 #define CONFIG_PCI
  39 #define CONFIG_PCI_INDIRECT_BRIDGE
  40 #define CONFIG_FSL_ELBC                 1
  41
  42 #define CONFIG_MISC_INIT_R
  43
  44 /*
  45  * On-board devices
  46  *
  47  * TSEC1 is Marvell PHY 88E1118
  48  */
  49
  50 #define CONFIG_SYS_33MHZ
  51
  52 #define CONFIG_83XX_CLKIN               33333333        /* in Hz */
  53
  54 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  55
  56 #define CONFIG_SYS_IMMR                 0xE0000000
  57
  58 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  59 #define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
  60 #endif
  61
  62 #define CONFIG_SYS_MEMTEST_START        0x00001000
  63 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  64
  65 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  66 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  67
  68 /*
  69  * Device configurations
  70  */
  71 #define CONFIG_TSEC1
  72
  73 /*
  74  * DDR Setup
  75  */
  76                                         /* DDR is system memory*/
  77 #define CONFIG_SYS_DDR_BASE             0x00000000
  78 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  79 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  80
  81 #define CONFIG_VERY_BIG_RAM
  82 #define CONFIG_MAX_MEM_MAPPED           (512 << 20)
  83
  84 #define CONFIG_SYS_DDRCDR               (DDRCDR_EN \
  85                                         | DDRCDR_PZ_NOMZ \
  86                                         | DDRCDR_NZ_NOMZ \
  87                                         | DDRCDR_M_ODR)
  88                                         /* 0x73000002 TODO ODR & DRN ? */
  89
  90 /*
  91  * FLASH on the Local Bus
  92  */
  93 #define CONFIG_SYS_NO_FLASH
  94
  95 #if !defined(CONFIG_NAND_SPL)
  96 #define CONFIG_SYS_RAMBOOT
  97 #endif
  98
  99 #define CONFIG_SYS_INIT_RAM_LOCK        1
 100 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 101 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 102
 103 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 104                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 105 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 106
 107 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 108 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 109 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 110
 111 /*
 112  * Local Bus LCRR and LBCR regs
 113  */
 114 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 115 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 116 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 117 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 118                                 | (0xFF << LBCR_BMT_SHIFT) \
 119                                 | 0xF)  /* 0x0004ff0f */
 120
 121                                 /* LB refresh timer prescal, 266MHz/32 */
 122 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 123
 124 /* drivers/mtd/nand/nand.c */
 125 #ifdef CONFIG_NAND_SPL
 126 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 127 #else
 128 #define CONFIG_SYS_NAND_BASE            0xE2800000
 129 #endif
 130 #define CONFIG_SYS_FPGA_BASE            0xFF000000
 131
 132 #define CONFIG_CMD_NAND
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 134 #define CONFIG_MTD_NAND_VERIFY_WRITE
 135 #define CONFIG_NAND_FSL_ELBC            1
 136
 137 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 138                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 139                                 | BR_PS_8               /* 8 bit Port */ \
 140                                 | BR_MS_FCM             /* MSEL = FCM */ \
 141                                 | BR_V)                 /* valid */
 142
 143 #ifdef CONFIG_NAND_SP
 144 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 145                                         | OR_FCM_CSCT \
 146                                         | OR_FCM_CST \
 147                                         | OR_FCM_CHT \
 148                                         | OR_FCM_SCY_1 \
 149                                         | OR_FCM_TRLX \
 150                                         | OR_FCM_EHTR)
 151 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 152 #define CONFIG_SYS_NAND_PAGE_SIZE       512     /* NAND chip page size */
 153                                         /* NAND chip block size */
 154 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)
 155 #define NAND_CACHE_PAGES                32
 156 #elif defined(CONFIG_NAND_LP)
 157 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_256KB \
 158                                         | OR_FCM_PGS \
 159                                         | OR_FCM_CSCT \
 160                                         | OR_FCM_CST \
 161                                         | OR_FCM_CHT \
 162                                         | OR_FCM_SCY_1 \
 163                                         | OR_FCM_TRLX \
 164                                         | OR_FCM_EHTR)
 165 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 166 #define CONFIG_SYS_NAND_PAGE_SIZE       2048    /* NAND chip page size */
 167                                         /* NAND chip block size */
 168 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 169 #define NAND_CACHE_PAGES                64
 170 #else
 171 #error Page size of NAND not defined.
 172 #endif /* CONFIG_NAND_SP */
 173
 174 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 175
 176 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 177 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 178
 179 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 180
 181 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 182 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 183
 184 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_FPGA_BASE \
 185                                         | BR_PS_16 \
 186                                         | BR_MS_UPMA \
 187                                         | BR_V)
 188 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_2MB \
 189                                         | OR_UPM_BCTLD)
 190
 191 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA_BASE
 192 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_2MB)
 193
 194 /*
 195  * JFFS2 configuration
 196  */
 197 #define CONFIG_JFFS2_NAND
 198 #define CONFIG_JFFS2_DEV        "nand0"
 199
 200 /* mtdparts command line support */
 201 #define CONFIG_CMD_MTDPARTS
 202 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 203 #define MTDIDS_DEFAULT          "nand0=nand0"
 204 #define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 205
 206 /* pass open firmware flat tree */
 207 #define CONFIG_OF_LIBFDT                1
 208 #define CONFIG_OF_BOARD_SETUP           1
 209 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 210
 211 /*
 212  * Serial Port
 213  */
 214 #define CONFIG_CONS_INDEX               1
 215 #define CONFIG_SYS_NS16550
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #ifdef CONFIG_NAND_SPL
 219 #define CONFIG_NS16550_MIN_FUNCTIONS
 220 #endif
 221
 222 #define CONFIG_SYS_BAUDRATE_TABLE       \
 223                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 224
 225 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 226 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 227
 228 /* Use the HUSH parser */
 229 #define CONFIG_SYS_HUSH_PARSER
 230
 231 /* I2C */
 232 #define CONFIG_SYS_I2C
 233 #define CONFIG_SYS_I2C_FSL
 234 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 235 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 236 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 237 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 238 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 239 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 240 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 241
 242 /*
 243  * General PCI
 244  * Addresses are mapped 1-1.
 245  */
 246 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 247 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 248 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 249 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 250 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 251 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 252 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 253 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 254 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 255
 256 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 257 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 258
 259 /*
 260  * TSEC
 261  */
 262 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 263
 264 #define CONFIG_GMII                     /* MII PHY management */
 265
 266 #ifdef CONFIG_TSEC1
 267 #define CONFIG_HAS_ETH0
 268 #define CONFIG_TSEC1_NAME               "TSEC0"
 269 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 270 #define TSEC1_PHY_ADDR                  0x0
 271 #define TSEC1_FLAGS                     TSEC_GIGABIT
 272 #define TSEC1_PHYIDX                    0
 273 #endif
 274
 275 #ifdef CONFIG_TSEC2
 276 #define CONFIG_HAS_ETH1
 277 #define CONFIG_TSEC2_NAME               "TSEC1"
 278 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 279 #define TSEC2_PHY_ADDR                  4
 280 #define TSEC2_FLAGS                     TSEC_GIGABIT
 281 #define TSEC2_PHYIDX                    0
 282 #endif
 283
 284
 285 /* Options are: TSEC[0-1] */
 286 #define CONFIG_ETHPRIME                 "TSEC1"
 287
 288 /*
 289  * Configure on-board RTC
 290  */
 291 #define CONFIG_RTC_DS1337
 292 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 293
 294 /*
 295  * Environment
 296  */
 297 #if defined(CONFIG_NAND_U_BOOT)
 298         #define CONFIG_ENV_IS_IN_NAND   1
 299         #define CONFIG_ENV_OFFSET       (768 * 1024)
 300         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 301         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 302         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 303         #define CONFIG_ENV_RANGE        (CONFIG_ENV_SECT_SIZE * 4)
 304         #define CONFIG_ENV_OFFSET_REDUND        \
 305                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 306 #elif !defined(CONFIG_SYS_RAMBOOT)
 307         #define CONFIG_ENV_IS_IN_FLASH  1
 308         #define CONFIG_ENV_ADDR         \
 309                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 310         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 311         #define CONFIG_ENV_SIZE         0x2000
 312
 313 /* Address and size of Redundant Environment Sector */
 314 #else
 315         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 316         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 317         #define CONFIG_ENV_SIZE         0x2000
 318 #endif
 319
 320 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 321 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 322
 323 /*
 324  * BOOTP options
 325  */
 326 #define CONFIG_BOOTP_BOOTFILESIZE
 327 #define CONFIG_BOOTP_BOOTPATH
 328 #define CONFIG_BOOTP_GATEWAY
 329 #define CONFIG_BOOTP_HOSTNAME
 330
 331
 332 /*
 333  * Command line configuration.
 334  */
 335 #include <config_cmd_default.h>
 336 #undef CONFIG_CMD_IMLS
 337 #undef CONFIG_CMD_FLASH
 338
 339 #define CONFIG_CMD_PING
 340 #define CONFIG_CMD_DHCP
 341 #define CONFIG_CMD_I2C
 342 #define CONFIG_CMD_MII
 343 #define CONFIG_CMD_DATE
 344 #define CONFIG_CMD_PCI
 345 #define CONFIG_CMD_JFFS2
 346
 347 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 348         #undef CONFIG_CMD_SAVEENV
 349         #undef CONFIG_CMD_LOADS
 350 #endif
 351
 352 #define CONFIG_CMDLINE_EDITING  1
 353 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 359 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 360 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 361 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 362
 363 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE              \
 364                                 + sizeof(CONFIG_SYS_PROMPT)     \
 365                                 + 16)   /* Print Buffer Size */
 366 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 367                                 /* Boot Argument Buffer Size */
 368 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 369 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 370
 371 /*
 372  * For booting Linux, the board info and command line data
 373  * have to be in the first 256 MB of memory, since this is
 374  * the maximum mapped by the Linux kernel during initialization.
 375  */
 376                                 /* Initial Memory map for Linux*/
 377 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 378
 379 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST */
 380
 381 #define CONFIG_SYS_HRCW_LOW     (HRCWL_LCL_BUS_TO_SCB_CLK_1X1   \
 382                                 | 0x20000000 /* reserved */     \
 383                                 | HRCWL_DDR_TO_SCB_CLK_2X1      \
 384                                 | HRCWL_CSB_TO_CLKIN_4X1        \
 385                                 | HRCWL_CORE_TO_CSB_2_5X1)
 386
 387 #define CONFIG_SYS_NS16550_CLK  (CONFIG_83XX_CLKIN * 4)
 388
 389 #define CONFIG_SYS_HRCW_HIGH_BASE       (HRCWH_PCI_HOST \
 390                                 | HRCWH_PCI1_ARBITER_ENABLE     \
 391                                 | HRCWH_CORE_ENABLE             \
 392                                 | HRCWH_BOOTSEQ_DISABLE         \
 393                                 | HRCWH_SW_WATCHDOG_DISABLE     \
 394                                 | HRCWH_TSEC1M_IN_RGMII         \
 395                                 | HRCWH_TSEC2M_IN_RGMII         \
 396                                 | HRCWH_BIG_ENDIAN              \
 397                                 | HRCWH_LALE_NORMAL)
 398
 399 #ifdef CONFIG_NAND_LP
 400 #define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 401                                 | HRCWH_FROM_0XFFF00100         \
 402                                 | HRCWH_ROM_LOC_NAND_LP_8BIT    \
 403                                 | HRCWH_RL_EXT_NAND)
 404 #else
 405 #define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 406                                 | HRCWH_FROM_0XFFF00100         \
 407                                 | HRCWH_ROM_LOC_NAND_SP_8BIT    \
 408                                 | HRCWH_RL_EXT_NAND)
 409 #endif
 410
 411 /* System IO Config */
 412 #define CONFIG_SYS_SICRH        (SICRH_ETSEC2_B \
 413                                 | SICRH_ETSEC2_C        \
 414                                 | SICRH_ETSEC2_D        \
 415                                 | SICRH_ETSEC2_E        \
 416                                 | SICRH_ETSEC2_F        \
 417                                 | SICRH_ETSEC2_G        \
 418                                 | SICRH_TSOBI1          \
 419                                 | SICRH_TSOBI2)
 420 #define CONFIG_SYS_SICRL        (SICRL_LBC              \
 421                                 | SICRL_USBDR_10        \
 422                                 | SICRL_ETSEC2_A)
 423
 424 #define CONFIG_SYS_HID0_INIT    0x000000000
 425 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 426                                 | HID0_ENABLE_INSTRUCTION_CACHE \
 427                                 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 428
 429 #define CONFIG_SYS_HID2         HID2_HBE
 430
 431 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 432
 433 /* DDR @ 0x00000000 */
 434 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 435 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 436                                 | BATU_BL_256M \
 437                                 | BATU_VS \
 438                                 | BATU_VP)
 439 #define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 440                                 | BATL_PP_RW)
 441 #define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 442                                 | BATU_BL_256M \
 443                                 | BATU_VS \
 444                                 | BATU_VP)
 445
 446 /* PCI @ 0x80000000 */
 447 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 448 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE \
 449                                 | BATU_BL_256M \
 450                                 | BATU_VS \
 451                                 | BATU_VP)
 452 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE \
 453                                 | BATL_PP_RW \
 454                                 | BATL_CACHEINHIBIT \
 455                                 | BATL_GUARDEDSTORAGE)
 456 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE \
 457                                 | BATU_BL_256M \
 458                                 | BATU_VS \
 459                                 | BATU_VP)
 460
 461 /* PCI2 not supported on 8313 */
 462 #define CONFIG_SYS_IBAT4L       (0)
 463 #define CONFIG_SYS_IBAT4U       (0)
 464
 465 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 466 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 467                                 | BATL_PP_RW \
 468                                 | BATL_CACHEINHIBIT \
 469                                 | BATL_GUARDEDSTORAGE)
 470 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 471                                 | BATU_BL_256M \
 472                                 | BATU_VS \
 473                                 | BATU_VP)
 474
 475 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 476 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 477                                 | BATL_PP_RW \
 478                                 | BATL_GUARDEDSTORAGE)
 479 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 480                                 | BATU_BL_256M \
 481                                 | BATU_VS \
 482                                 | BATU_VP)
 483
 484 #define CONFIG_SYS_IBAT7L       (0)
 485 #define CONFIG_SYS_IBAT7U       (0)
 486
 487 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 488 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 489 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 490 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 491 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 492 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 493 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 494 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 495 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 496 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 497 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 498 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 499 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 500 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 501 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 502 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 503
 504 /*
 505  * Environment Configuration
 506  */
 507 #define CONFIG_ENV_OVERWRITE
 508
 509 #define CONFIG_NETDEV           "eth1"
 510
 511 #define CONFIG_HOSTNAME         simpc8313
 512 #define CONFIG_ROOTPATH         "/tftpboot/"
 513 #define CONFIG_BOOTFILE         "/tftpboot/uImage"
 514                                 /* U-Boot image on TFTP server */
 515 #define CONFIG_UBOOTPATH        "u-boot-nand.bin"
 516 #define CONFIG_FDTFILE          "simpc8313.dtb"
 517
 518                                 /* default location for tftp and bootm */
 519 #define CONFIG_LOADADDR         500000
 520 #define CONFIG_BOOTDELAY        5       /* 5 second delay */
 521 #define CONFIG_BAUDRATE         115200
 522
 523 #define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;" \
 524                                         "bootm $loadaddr - $fdtaddr"
 525
 526 #define CONFIG_EXTRA_ENV_SETTINGS \
 527         "netdev=" CONFIG_NETDEV "\0"                                    \
 528         "ethprime=TSEC1\0"                                              \
 529         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 530         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 531                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 532                         " +$filesize; " \
 533                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 534                         " +$filesize; " \
 535                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 536                         " $filesize; "  \
 537                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 538                         " +$filesize; " \
 539                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 540                         " $filesize\0"  \
 541         "fdtaddr=ae0000\0"                                              \
 542         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 543         "console=ttyS0\0"                                               \
 544         "setbootargs=setenv bootargs "                                  \
 545                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 546         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 547                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 548                                                         "$netdev:off "  \
 549                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 550         "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 551         "burn_uboot=nand erase u-boot 80000; "                          \
 552                 "nand write 100000 u-boot $filesize\0"                  \
 553         "update_uboot=run load_uboot;run burn_uboot\0"                  \
 554         "mtdids=nand0=nand0\0"                                          \
 555         "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 556         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 557                 "nfsroot=${serverip}:${rootpath}\0"                     \
 558         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 559         "addip=setenv bootargs ${bootargs} "                            \
 560                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 561                 ":${hostname}:${netdev}:off panic=1\0"                  \
 562         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 563         "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 564                 "console=ttyS0,115200\0"                                \
 565         ""
 566
 567 #define CONFIG_NFSBOOTCOMMAND                                           \
 568         "setenv rootdev /dev/nfs;"                                      \
 569         "run setbootargs;"                                              \
 570         "run setipargs;"                                                \
 571         "tftp $loadaddr $bootfile;"                                     \
 572         "tftp $fdtaddr $fdtfile;"                                       \
 573         "bootm $loadaddr - $fdtaddr"
 574
 575 #define CONFIG_RAMBOOTCOMMAND                                           \
 576         "setenv rootdev /dev/ram;"                                      \
 577         "run setbootargs;"                                              \
 578         "tftp $ramdiskaddr $ramdiskfile;"                               \
 579         "tftp $loadaddr $bootfile;"                                     \
 580         "tftp $fdtaddr $fdtfile;"                                       \
 581         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 582
 583 #endif  /* __CONFIG_H */