include/configs/T2080QDS.h

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 QDS board configuration file
   9  */
  10
  11 #ifndef __T2080QDS_H
  12 #define __T2080QDS_H
  13
  14 #define CONFIG_T2080QDS
  15 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  16 #define CONFIG_MMC
  17 #define CONFIG_SPI_FLASH
  18 #define CONFIG_USB_EHCI
  19 #define CONFIG_FSL_SATA_V2
  20 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  21 #define CONFIG_SRIO1            /* SRIO port 1 */
  22 #define CONFIG_SRIO2            /* SRIO port 2 */
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_PHYS_64BIT
  26 #define CONFIG_BOOKE
  27 #define CONFIG_E500             /* BOOKE e500 family */
  28 #define CONFIG_E500MC           /* BOOKE e500mc family */
  29 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  30 #define CONFIG_MPC85xx          /* MPC85xx/PQ3 platform */
  31 #define CONFIG_MP               /* support multiple processors */
  32 #define CONFIG_ENABLE_36BIT_PHYS
  33
  34 #ifdef CONFIG_PHYS_64BIT
  35 #define CONFIG_ADDR_MAP 1
  36 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  37 #endif
  38
  39 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  40 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
  41 #define CONFIG_FSL_IFC          /* Enable IFC Support */
  42 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  43 #define CONFIG_ENV_OVERWRITE
  44
  45 #ifdef CONFIG_RAMBOOT_PBL
  46 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  47 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  48 #endif
  49
  50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  52 /* Set 1M boot space */
  53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  55                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  57 #define CONFIG_SYS_NO_FLASH
  58 #endif
  59
  60 #ifndef CONFIG_SYS_TEXT_BASE
  61 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #define CONFIG_SYS_CACHE_STASHING
  72 #define CONFIG_BTB              /* toggle branch predition */
  73 #define CONFIG_DDR_ECC
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  76 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  77 #endif
  78
  79 #ifdef CONFIG_SYS_NO_FLASH
  80 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  81 #define CONFIG_ENV_IS_NOWHERE
  82 #endif
  83 #else
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_CFI
  86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  87 #endif
  88
  89 #if defined(CONFIG_SPIFLASH)
  90 #define CONFIG_SYS_EXTRA_ENV_RELOC
  91 #define CONFIG_ENV_IS_IN_SPI_FLASH
  92 #define CONFIG_ENV_SPI_BUS      0
  93 #define CONFIG_ENV_SPI_CS       0
  94 #define CONFIG_ENV_SPI_MAX_HZ   10000000
  95 #define CONFIG_ENV_SPI_MODE     0
  96 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
  97 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
  98 #define CONFIG_ENV_SECT_SIZE    0x10000
  99 #elif defined(CONFIG_SDCARD)
 100 #define CONFIG_SYS_EXTRA_ENV_RELOC
 101 #define CONFIG_ENV_IS_IN_MMC
 102 #define CONFIG_SYS_MMC_ENV_DEV  0
 103 #define CONFIG_ENV_SIZE         0x2000
 104 #define CONFIG_ENV_OFFSET       (512 * 1105)
 105 #elif defined(CONFIG_NAND)
 106 #define CONFIG_SYS_EXTRA_ENV_RELOC
 107 #define CONFIG_ENV_IS_IN_NAND
 108 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 109 #define CONFIG_ENV_OFFSET       (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 110 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 111 #define CONFIG_ENV_IS_IN_REMOTE
 112 #define CONFIG_ENV_ADDR         0xffe20000
 113 #define CONFIG_ENV_SIZE         0x2000
 114 #elif defined(CONFIG_ENV_IS_NOWHERE)
 115 #define CONFIG_ENV_SIZE         0x2000
 116 #else
 117 #define CONFIG_ENV_IS_IN_FLASH
 118 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 119 #define CONFIG_ENV_SIZE         0x2000
 120 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 121 #endif
 122
 123 #ifndef __ASSEMBLY__
 124 unsigned long get_board_sys_clk(void);
 125 unsigned long get_board_ddr_clk(void);
 126 #endif
 127
 128 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 129 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 130
 131 /*
 132  * Config the L3 Cache as L3 SRAM
 133  */
 134 #define CONFIG_SYS_INIT_L3_ADDR  CONFIG_RAMBOOT_TEXT_BASE
 135
 136 #define CONFIG_SYS_DCSRBAR      0xf0000000
 137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 138
 139 /* EEPROM */
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_NXID
 142 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 145
 146 /*
 147  * DDR Setup
 148  */
 149 #define CONFIG_VERY_BIG_RAM
 150 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 152 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 153 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 154 #define CONFIG_DDR_SPD
 155 #define CONFIG_SYS_FSL_DDR3
 156 #define CONFIG_FSL_DDR_INTERACTIVE
 157 #define CONFIG_SYS_SPD_BUS_NUM  0
 158 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 159 #define SPD_EEPROM_ADDRESS1     0x51
 160 #define SPD_EEPROM_ADDRESS2     0x52
 161 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 162 #define CTRL_INTLV_PREFERED     cacheline
 163
 164 /*
 165  * IFC Definitions
 166  */
 167 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 168 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 169 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 170 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 171                                 + 0x8000000) | \
 172                                 CSPR_PORT_SIZE_16 | \
 173                                 CSPR_MSEL_NOR | \
 174                                 CSPR_V)
 175 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 176 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 177                                 CSPR_PORT_SIZE_16 | \
 178                                 CSPR_MSEL_NOR | \
 179                                 CSPR_V)
 180 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 181 /* NOR Flash Timing Params */
 182 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 183
 184 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 185                                 FTIM0_NOR_TEADC(0x5) | \
 186                                 FTIM0_NOR_TEAHC(0x5))
 187 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 188                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 189                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 190 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 191                                 FTIM2_NOR_TCH(0x4) | \
 192                                 FTIM2_NOR_TWPH(0x0E) | \
 193                                 FTIM2_NOR_TWP(0x1c))
 194 #define CONFIG_SYS_NOR_FTIM3    0x0
 195
 196 #define CONFIG_SYS_FLASH_QUIET_TEST
 197 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 203
 204 #define CONFIG_SYS_FLASH_EMPTY_INFO
 205 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 206                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 207
 208 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 209 #define QIXIS_BASE                      0xffdf0000
 210 #define QIXIS_LBMAP_SWITCH              6
 211 #define QIXIS_LBMAP_MASK                0x0f
 212 #define QIXIS_LBMAP_SHIFT               0
 213 #define QIXIS_LBMAP_DFLTBANK            0x00
 214 #define QIXIS_LBMAP_ALTBANK             0x04
 215 #define QIXIS_RST_CTL_RESET             0x83
 216 #define QIXIS_RST_FORCE_MEM             0x1
 217 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 218 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 219 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 220 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 221
 222 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 223 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 224                                 | CSPR_PORT_SIZE_8 \
 225                                 | CSPR_MSEL_GPCM \
 226                                 | CSPR_V)
 227 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 228 #define CONFIG_SYS_CSOR3        0x0
 229 /* QIXIS Timing parameters for IFC CS3 */
 230 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 231                                         FTIM0_GPCM_TEADC(0x0e) | \
 232                                         FTIM0_GPCM_TEAHC(0x0e))
 233 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 234                                         FTIM1_GPCM_TRAD(0x3f))
 235 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 236                                         FTIM2_GPCM_TCH(0x0) | \
 237                                         FTIM2_GPCM_TWP(0x1f))
 238 #define CONFIG_SYS_CS3_FTIM3            0x0
 239
 240 /* NAND Flash on IFC */
 241 #define CONFIG_NAND_FSL_IFC
 242 #define CONFIG_SYS_NAND_BASE            0xff800000
 243 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 244
 245 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 246 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 247                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 248                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 249                                 | CSPR_V)
 250 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 251
 252 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 253                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 254                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 255                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 256                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 257                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 258                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 259
 260 #define CONFIG_SYS_NAND_ONFI_DETECTION
 261
 262 /* ONFI NAND Flash mode0 Timing Params */
 263 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 264                                         FTIM0_NAND_TWP(0x18)    | \
 265                                         FTIM0_NAND_TWCHT(0x07)  | \
 266                                         FTIM0_NAND_TWH(0x0a))
 267 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 268                                         FTIM1_NAND_TWBE(0x39)   | \
 269                                         FTIM1_NAND_TRR(0x0e)    | \
 270                                         FTIM1_NAND_TRP(0x18))
 271 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 272                                         FTIM2_NAND_TREH(0x0a)   | \
 273                                         FTIM2_NAND_TWHRE(0x1e))
 274 #define CONFIG_SYS_NAND_FTIM3           0x0
 275
 276 #define CONFIG_SYS_NAND_DDR_LAW         11
 277 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 278 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 279 #define CONFIG_MTD_NAND_VERIFY_WRITE
 280 #define CONFIG_CMD_NAND
 281 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 282
 283 #if defined(CONFIG_NAND)
 284 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 285 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 286 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 287 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 288 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 289 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 290 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 291 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 292 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 293 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 294 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 295 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 296 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 297 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 298 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 299 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 300 #else
 301 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 302 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 303 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 304 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 305 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 306 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 307 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 308 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 309 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 310 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 311 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 312 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 313 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 314 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 315 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 316 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 317 #endif
 318 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 319 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 320 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 321 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 322 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 323 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 324 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 325 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 326
 327 #if defined(CONFIG_RAMBOOT_PBL)
 328 #define CONFIG_SYS_RAMBOOT
 329 #endif
 330
 331 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE
 332 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 333 #define CONFIG_MISC_INIT_R
 334 #define CONFIG_HWCONFIG
 335
 336 /* define to use L1 as initial stack */
 337 #define CONFIG_L1_INIT_RAM
 338 #define CONFIG_SYS_INIT_RAM_LOCK
 339 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 340 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 342 /* The assembler doesn't like typecast */
 343 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 344                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 345                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 346 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 347 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 348                                                 GENERATED_GBL_DATA_SIZE)
 349 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 350 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 351 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 352
 353 /*
 354  * Serial Port
 355  */
 356 #define CONFIG_CONS_INDEX               1
 357 #define CONFIG_SYS_NS16550
 358 #define CONFIG_SYS_NS16550_SERIAL
 359 #define CONFIG_SYS_NS16550_REG_SIZE     1
 360 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 361 #define CONFIG_SYS_BAUDRATE_TABLE       \
 362         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 363 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 364 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 365 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 366 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 367
 368 /* Use the HUSH parser */
 369 #define CONFIG_SYS_HUSH_PARSER
 370 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 371
 372 /* pass open firmware flat tree */
 373 #define CONFIG_OF_LIBFDT
 374 #define CONFIG_OF_BOARD_SETUP
 375 #define CONFIG_OF_STDOUT_VIA_ALIAS
 376
 377 /* new uImage format support */
 378 #define CONFIG_FIT
 379 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 380
 381 /*
 382  * I2C
 383  */
 384 #define CONFIG_SYS_I2C
 385 #define CONFIG_SYS_I2C_FSL
 386 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 387 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 388 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 389 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 390 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 391 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 392 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 393 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 394 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 395 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 396 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 397 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 398 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 399 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 400 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 401 #define I2C_MUX_CH_DEFAULT      0x8
 402
 403
 404 /*
 405  * RapidIO
 406  */
 407 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 408 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 409 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 410 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 411 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 412 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 413 /*
 414  * for slave u-boot IMAGE instored in master memory space,
 415  * PHYS must be aligned based on the SIZE
 416  */
 417 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 418 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 419 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
 420 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 421 /*
 422  * for slave UCODE and ENV instored in master memory space,
 423  * PHYS must be aligned based on the SIZE
 424  */
 425 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 426 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 427 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 428
 429 /* slave core release by master*/
 430 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 431 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 432
 433 /*
 434  * SRIO_PCIE_BOOT - SLAVE
 435  */
 436 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 437 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 438 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 439                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 440 #endif
 441
 442 /*
 443  * eSPI - Enhanced SPI
 444  */
 445 #ifdef CONFIG_SPI_FLASH
 446 #define CONFIG_FSL_ESPI
 447 #define CONFIG_SPI_FLASH_SST
 448 #define CONFIG_SPI_FLASH_STMICRO
 449 #define CONFIG_SPI_FLASH_SPANSION
 450 #define CONFIG_CMD_SF
 451 #define CONFIG_SF_DEFAULT_SPEED  10000000
 452 #define CONFIG_SF_DEFAULT_MODE    0
 453 #endif
 454
 455 /*
 456  * General PCI
 457  * Memory space is mapped 1-1, but I/O space must start from 0.
 458  */
 459 #define CONFIG_PCI              /* Enable PCI/PCIE */
 460 #define CONFIG_PCIE1            /* PCIE controler 1 */
 461 #define CONFIG_PCIE2            /* PCIE controler 2 */
 462 #define CONFIG_PCIE3            /* PCIE controler 3 */
 463 #define CONFIG_PCIE4            /* PCIE controler 4 */
 464 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 465 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 466 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 467 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 468 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 469 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 470 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 471 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 472 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 473 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 474 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 475
 476 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 477 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 478 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 479 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 480 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 481 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 482 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 483 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 484 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 485
 486 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 487 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 488 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 489 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 490 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 491 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 492 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 493 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 494 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 495
 496 /* controller 4, Base address 203000 */
 497 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 498 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 499 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 500 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 501 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 502 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 503 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 504
 505 #ifdef CONFIG_PCI
 506 #define CONFIG_PCI_INDIRECT_BRIDGE
 507 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 508 #define CONFIG_NET_MULTI
 509 #define CONFIG_E1000
 510 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 511 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 512 #define CONFIG_DOS_PARTITION
 513 #endif
 514
 515 /* Qman/Bman */
 516 #ifndef CONFIG_NOBQFMAN
 517 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 518 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 519 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 520 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 521 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 522 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 523 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 524 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 525 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 526
 527 #define CONFIG_SYS_DPAA_FMAN
 528 #define CONFIG_SYS_DPAA_PME
 529 #define CONFIG_SYS_PMAN
 530 #define CONFIG_SYS_DPAA_DCE
 531 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 532 #define CONFIG_SYS_INTERLAKEN
 533
 534 /* Default address of microcode for the Linux Fman driver */
 535 #if defined(CONFIG_SPIFLASH)
 536 /*
 537  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 538  * env, so we got 0x110000.
 539  */
 540 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 541 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 542 #elif defined(CONFIG_SDCARD)
 543 /*
 544  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 545  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 546  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 547  */
 548 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 549 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 550 #elif defined(CONFIG_NAND)
 551 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 552 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 553 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 554 /*
 555  * Slave has no ucode locally, it can fetch this from remote. When implementing
 556  * in two corenet boards, slave's ucode could be stored in master's memory
 557  * space, the address can be mapped from slave TLB->slave LAW->
 558  * slave SRIO or PCIE outbound window->master inbound window->
 559  * master LAW->the ucode address in master's memory space.
 560  */
 561 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 562 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 563 #else
 564 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 565 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEFF40000
 566 #endif
 567 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 568 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 569 #endif /* CONFIG_NOBQFMAN */
 570
 571 #ifdef CONFIG_SYS_DPAA_FMAN
 572 #define CONFIG_FMAN_ENET
 573 #define CONFIG_PHYLIB_10G
 574 #define CONFIG_PHY_VITESSE
 575 #define CONFIG_PHY_REALTEK
 576 #define CONFIG_PHY_TERANETICS
 577 #define RGMII_PHY1_ADDR 0x1
 578 #define RGMII_PHY2_ADDR 0x2
 579 #define FM1_10GEC1_PHY_ADDR       0x3
 580 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 581 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 582 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 583 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 584 #endif
 585
 586 #ifdef CONFIG_FMAN_ENET
 587 #define CONFIG_MII              /* MII PHY management */
 588 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 589 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 590 #endif
 591
 592 /*
 593  * SATA
 594  */
 595 #ifdef CONFIG_FSL_SATA_V2
 596 #define CONFIG_LIBATA
 597 #define CONFIG_FSL_SATA
 598 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 599 #define CONFIG_SATA1
 600 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 601 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 602 #define CONFIG_SATA2
 603 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 604 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 605 #define CONFIG_LBA48
 606 #define CONFIG_CMD_SATA
 607 #define CONFIG_DOS_PARTITION
 608 #define CONFIG_CMD_EXT2
 609 #endif
 610
 611 /*
 612  * USB
 613  */
 614 #ifdef CONFIG_USB_EHCI
 615 #define CONFIG_CMD_USB
 616 #define CONFIG_USB_STORAGE
 617 #define CONFIG_USB_EHCI_FSL
 618 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 619 #define CONFIG_CMD_EXT2
 620 #define CONFIG_HAS_FSL_DR_USB
 621 #endif
 622
 623 /*
 624  * SDHC
 625  */
 626 #ifdef CONFIG_MMC
 627 #define CONFIG_CMD_MMC
 628 #define CONFIG_FSL_ESDHC
 629 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 630 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 631 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 632 #define CONFIG_GENERIC_MMC
 633 #define CONFIG_CMD_EXT2
 634 #define CONFIG_CMD_FAT
 635 #define CONFIG_DOS_PARTITION
 636 #endif
 637
 638 /*
 639  * Environment
 640  */
 641 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 642 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 643
 644 /*
 645  * Command line configuration.
 646  */
 647 #include <config_cmd_default.h>
 648
 649 #define CONFIG_CMD_DHCP
 650 #define CONFIG_CMD_ELF
 651 #define CONFIG_CMD_ERRATA
 652 #define CONFIG_CMD_GREPENV
 653 #define CONFIG_CMD_IRQ
 654 #define CONFIG_CMD_I2C
 655 #define CONFIG_CMD_MII
 656 #define CONFIG_CMD_PING
 657 #define CONFIG_CMD_SETEXPR
 658 #define CONFIG_CMD_REGINFO
 659 #define CONFIG_CMD_BDI
 660
 661 #ifdef CONFIG_PCI
 662 #define CONFIG_CMD_PCI
 663 #define CONFIG_CMD_NET
 664 #endif
 665
 666 /*
 667  * Miscellaneous configurable options
 668  */
 669 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 670 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 671 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 672 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 673 #define CONFIG_SYS_PROMPT       "=> "     /* Monitor Command Prompt */
 674 #ifdef CONFIG_CMD_KGDB
 675 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 676 #else
 677 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 678 #endif
 679 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 680 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 681 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 682 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks*/
 683
 684 /*
 685  * For booting Linux, the board info and command line data
 686  * have to be in the first 64 MB of memory, since this is
 687  * the maximum mapped by the Linux kernel during initialization.
 688  */
 689 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 690 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 691
 692 #ifdef CONFIG_CMD_KGDB
 693 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 694 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 695 #endif
 696
 697 /*
 698  * Environment Configuration
 699  */
 700 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 701 #define CONFIG_BOOTFILE  "uImage"
 702 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 703
 704 /* default location for tftp and bootm */
 705 #define CONFIG_LOADADDR         1000000
 706 #define CONFIG_BAUDRATE         115200
 707 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 708 #define __USB_PHY_TYPE          utmi
 709
 710 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 711         "hwconfig=fsl_ddr:"                                     \
 712         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 713         "bank_intlv=auto;"                                      \
 714         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 715         "netdev=eth0\0"                                         \
 716         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 717         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 718         "tftpflash=tftpboot $loadaddr $uboot && "               \
 719         "protect off $ubootaddr +$filesize && "                 \
 720         "erase $ubootaddr +$filesize && "                       \
 721         "cp.b $loadaddr $ubootaddr $filesize && "               \
 722         "protect on $ubootaddr +$filesize && "                  \
 723         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 724         "consoledev=ttyS0\0"                                    \
 725         "ramdiskaddr=2000000\0"                                 \
 726         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 727         "fdtaddr=c00000\0"                                      \
 728         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 729         "bdev=sda3\0"                                           \
 730         "c=ffe\0"
 731
 732 /*
 733  * For emulation this causes u-boot to jump to the start of the
 734  * proof point app code automatically
 735  */
 736 #define CONFIG_PROOF_POINTS                             \
 737         "setenv bootargs root=/dev/$bdev rw "           \
 738         "console=$consoledev,$baudrate $othbootargs;"   \
 739         "cpu 1 release 0x29000000 - - -;"               \
 740         "cpu 2 release 0x29000000 - - -;"               \
 741         "cpu 3 release 0x29000000 - - -;"               \
 742         "cpu 4 release 0x29000000 - - -;"               \
 743         "cpu 5 release 0x29000000 - - -;"               \
 744         "cpu 6 release 0x29000000 - - -;"               \
 745         "cpu 7 release 0x29000000 - - -;"               \
 746         "go 0x29000000"
 747
 748 #define CONFIG_HVBOOT                           \
 749         "setenv bootargs config-addr=0x60000000; "      \
 750         "bootm 0x01000000 - 0x00f00000"
 751
 752 #define CONFIG_ALU                              \
 753         "setenv bootargs root=/dev/$bdev rw "           \
 754         "console=$consoledev,$baudrate $othbootargs;"   \
 755         "cpu 1 release 0x01000000 - - -;"               \
 756         "cpu 2 release 0x01000000 - - -;"               \
 757         "cpu 3 release 0x01000000 - - -;"               \
 758         "cpu 4 release 0x01000000 - - -;"               \
 759         "cpu 5 release 0x01000000 - - -;"               \
 760         "cpu 6 release 0x01000000 - - -;"               \
 761         "cpu 7 release 0x01000000 - - -;"               \
 762         "go 0x01000000"
 763
 764 #define CONFIG_LINUX                            \
 765         "setenv bootargs root=/dev/ram rw "             \
 766         "console=$consoledev,$baudrate $othbootargs;"   \
 767         "setenv ramdiskaddr 0x02000000;"                \
 768         "setenv fdtaddr 0x00c00000;"                    \
 769         "setenv loadaddr 0x1000000;"                    \
 770         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 771
 772 #define CONFIG_HDBOOT                                   \
 773         "setenv bootargs root=/dev/$bdev rw "           \
 774         "console=$consoledev,$baudrate $othbootargs;"   \
 775         "tftp $loadaddr $bootfile;"                     \
 776         "tftp $fdtaddr $fdtfile;"                       \
 777         "bootm $loadaddr - $fdtaddr"
 778
 779 #define CONFIG_NFSBOOTCOMMAND                   \
 780         "setenv bootargs root=/dev/nfs rw "     \
 781         "nfsroot=$serverip:$rootpath "          \
 782         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 783         "console=$consoledev,$baudrate $othbootargs;"   \
 784         "tftp $loadaddr $bootfile;"             \
 785         "tftp $fdtaddr $fdtfile;"               \
 786         "bootm $loadaddr - $fdtaddr"
 787
 788 #define CONFIG_RAMBOOTCOMMAND                           \
 789         "setenv bootargs root=/dev/ram rw "             \
 790         "console=$consoledev,$baudrate $othbootargs;"   \
 791         "tftp $ramdiskaddr $ramdiskfile;"               \
 792         "tftp $loadaddr $bootfile;"                     \
 793         "tftp $fdtaddr $fdtfile;"                       \
 794         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 795
 796 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 797
 798 #ifdef CONFIG_SECURE_BOOT
 799 #include <asm/fsl_secure_boot.h>
 800 #undef CONFIG_CMD_USB
 801 #endif
 802
 803 #endif  /* __T2080QDS_H */