include/configs/T208xQDS.h

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_MMC
  16 #define CONFIG_SPI_FLASH
  17 #define CONFIG_USB_EHCI
  18 #if defined(CONFIG_PPC_T2080)
  19 #define CONFIG_T2080QDS
  20 #define CONFIG_FSL_SATA_V2
  21 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  22 #define CONFIG_SRIO1            /* SRIO port 1 */
  23 #define CONFIG_SRIO2            /* SRIO port 2 */
  24 #elif defined(CONFIG_PPC_T2081)
  25 #define CONFIG_T2081QDS
  26 #endif
  27
  28 /* High Level Configuration Options */
  29 #define CONFIG_PHYS_64BIT
  30 #define CONFIG_BOOKE
  31 #define CONFIG_E500             /* BOOKE e500 family */
  32 #define CONFIG_E500MC           /* BOOKE e500mc family */
  33 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  34 #define CONFIG_MP               /* support multiple processors */
  35 #define CONFIG_ENABLE_36BIT_PHYS
  36
  37 #ifdef CONFIG_PHYS_64BIT
  38 #define CONFIG_ADDR_MAP 1
  39 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  40 #endif
  41
  42 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  43 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
  44 #define CONFIG_FSL_IFC          /* Enable IFC Support */
  45 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #ifdef CONFIG_RAMBOOT_PBL
  49 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  51 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
  52 #if defined(CONFIG_PPC_T2080)
  53 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
  54 #elif defined(CONFIG_PPC_T2081)
  55 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
  56 #endif
  57 #endif
  58
  59 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  60 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  61 /* Set 1M boot space */
  62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  63 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  64                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  65 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  66 #define CONFIG_SYS_NO_FLASH
  67 #endif
  68
  69 #ifndef CONFIG_SYS_TEXT_BASE
  70 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  71 #endif
  72
  73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  75 #endif
  76
  77 /*
  78  * These can be toggled for performance analysis, otherwise use default.
  79  */
  80 #define CONFIG_SYS_CACHE_STASHING
  81 #define CONFIG_BTB              /* toggle branch predition */
  82 #define CONFIG_DDR_ECC
  83 #ifdef CONFIG_DDR_ECC
  84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  85 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  86 #endif
  87
  88 #ifdef CONFIG_SYS_NO_FLASH
  89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  90 #define CONFIG_ENV_IS_NOWHERE
  91 #endif
  92 #else
  93 #define CONFIG_FLASH_CFI_DRIVER
  94 #define CONFIG_SYS_FLASH_CFI
  95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  96 #endif
  97
  98 #if defined(CONFIG_SPIFLASH)
  99 #define CONFIG_SYS_EXTRA_ENV_RELOC
 100 #define CONFIG_ENV_IS_IN_SPI_FLASH
 101 #define CONFIG_ENV_SPI_BUS      0
 102 #define CONFIG_ENV_SPI_CS       0
 103 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 104 #define CONFIG_ENV_SPI_MODE     0
 105 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 106 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 107 #define CONFIG_ENV_SECT_SIZE    0x10000
 108 #elif defined(CONFIG_SDCARD)
 109 #define CONFIG_SYS_EXTRA_ENV_RELOC
 110 #define CONFIG_ENV_IS_IN_MMC
 111 #define CONFIG_SYS_MMC_ENV_DEV  0
 112 #define CONFIG_ENV_SIZE         0x2000
 113 #define CONFIG_ENV_OFFSET       (512 * 1658)
 114 #elif defined(CONFIG_NAND)
 115 #define CONFIG_SYS_EXTRA_ENV_RELOC
 116 #define CONFIG_ENV_IS_IN_NAND
 117 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 118 #define CONFIG_ENV_OFFSET       (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 120 #define CONFIG_ENV_IS_IN_REMOTE
 121 #define CONFIG_ENV_ADDR         0xffe20000
 122 #define CONFIG_ENV_SIZE         0x2000
 123 #elif defined(CONFIG_ENV_IS_NOWHERE)
 124 #define CONFIG_ENV_SIZE         0x2000
 125 #else
 126 #define CONFIG_ENV_IS_IN_FLASH
 127 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 128 #define CONFIG_ENV_SIZE         0x2000
 129 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 130 #endif
 131
 132 #ifndef __ASSEMBLY__
 133 unsigned long get_board_sys_clk(void);
 134 unsigned long get_board_ddr_clk(void);
 135 #endif
 136
 137 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 138 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 139
 140 /*
 141  * Config the L3 Cache as L3 SRAM
 142  */
 143 #define CONFIG_SYS_INIT_L3_ADDR  CONFIG_RAMBOOT_TEXT_BASE
 144
 145 #define CONFIG_SYS_DCSRBAR      0xf0000000
 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 147
 148 /* EEPROM */
 149 #define CONFIG_ID_EEPROM
 150 #define CONFIG_SYS_I2C_EEPROM_NXID
 151 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 154
 155 /*
 156  * DDR Setup
 157  */
 158 #define CONFIG_VERY_BIG_RAM
 159 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 160 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 161 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 162 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 163 #define CONFIG_DDR_SPD
 164 #define CONFIG_SYS_FSL_DDR3
 165 #undef CONFIG_FSL_DDR_INTERACTIVE
 166 #define CONFIG_SYS_SPD_BUS_NUM  0
 167 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 168 #define SPD_EEPROM_ADDRESS1     0x51
 169 #define SPD_EEPROM_ADDRESS2     0x52
 170 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 171 #define CTRL_INTLV_PREFERED     cacheline
 172
 173 /*
 174  * IFC Definitions
 175  */
 176 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 177 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 178 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 179 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 180                                 + 0x8000000) | \
 181                                 CSPR_PORT_SIZE_16 | \
 182                                 CSPR_MSEL_NOR | \
 183                                 CSPR_V)
 184 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 185 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 186                                 CSPR_PORT_SIZE_16 | \
 187                                 CSPR_MSEL_NOR | \
 188                                 CSPR_V)
 189 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 190 /* NOR Flash Timing Params */
 191 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 192
 193 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 194                                 FTIM0_NOR_TEADC(0x5) | \
 195                                 FTIM0_NOR_TEAHC(0x5))
 196 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 197                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 198                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 199 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 200                                 FTIM2_NOR_TCH(0x4) | \
 201                                 FTIM2_NOR_TWPH(0x0E) | \
 202                                 FTIM2_NOR_TWP(0x1c))
 203 #define CONFIG_SYS_NOR_FTIM3    0x0
 204
 205 #define CONFIG_SYS_FLASH_QUIET_TEST
 206 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212
 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
 214 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 215                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 216
 217 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 218 #define QIXIS_BASE                      0xffdf0000
 219 #define QIXIS_LBMAP_SWITCH              6
 220 #define QIXIS_LBMAP_MASK                0x0f
 221 #define QIXIS_LBMAP_SHIFT               0
 222 #define QIXIS_LBMAP_DFLTBANK            0x00
 223 #define QIXIS_LBMAP_ALTBANK             0x04
 224 #define QIXIS_RST_CTL_RESET             0x83
 225 #define QIXIS_RST_FORCE_MEM             0x1
 226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 227 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 229 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 230
 231 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 232 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 233                                 | CSPR_PORT_SIZE_8 \
 234                                 | CSPR_MSEL_GPCM \
 235                                 | CSPR_V)
 236 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 237 #define CONFIG_SYS_CSOR3        0x0
 238 /* QIXIS Timing parameters for IFC CS3 */
 239 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 240                                         FTIM0_GPCM_TEADC(0x0e) | \
 241                                         FTIM0_GPCM_TEAHC(0x0e))
 242 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 243                                         FTIM1_GPCM_TRAD(0x3f))
 244 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 245                                         FTIM2_GPCM_TCH(0x0) | \
 246                                         FTIM2_GPCM_TWP(0x1f))
 247 #define CONFIG_SYS_CS3_FTIM3            0x0
 248
 249 /* NAND Flash on IFC */
 250 #define CONFIG_NAND_FSL_IFC
 251 #define CONFIG_SYS_NAND_BASE            0xff800000
 252 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 253
 254 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 255 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 256                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 257                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 258                                 | CSPR_V)
 259 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 260
 261 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 262                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 263                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 264                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 265                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 266                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 267                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 268
 269 #define CONFIG_SYS_NAND_ONFI_DETECTION
 270
 271 /* ONFI NAND Flash mode0 Timing Params */
 272 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 273                                         FTIM0_NAND_TWP(0x18)    | \
 274                                         FTIM0_NAND_TWCHT(0x07)  | \
 275                                         FTIM0_NAND_TWH(0x0a))
 276 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 277                                         FTIM1_NAND_TWBE(0x39)   | \
 278                                         FTIM1_NAND_TRR(0x0e)    | \
 279                                         FTIM1_NAND_TRP(0x18))
 280 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 281                                         FTIM2_NAND_TREH(0x0a)   | \
 282                                         FTIM2_NAND_TWHRE(0x1e))
 283 #define CONFIG_SYS_NAND_FTIM3           0x0
 284
 285 #define CONFIG_SYS_NAND_DDR_LAW         11
 286 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 287 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 288 #define CONFIG_MTD_NAND_VERIFY_WRITE
 289 #define CONFIG_CMD_NAND
 290 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 291
 292 #if defined(CONFIG_NAND)
 293 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 294 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 295 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 296 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 297 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 298 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 299 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 300 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 301 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 302 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 303 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 304 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 305 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 306 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 307 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 308 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 309 #else
 310 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 311 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 312 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 319 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 320 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 321 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 322 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 323 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 324 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 325 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 326 #endif
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 335
 336 #if defined(CONFIG_RAMBOOT_PBL)
 337 #define CONFIG_SYS_RAMBOOT
 338 #endif
 339
 340 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE
 341 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 342 #define CONFIG_MISC_INIT_R
 343 #define CONFIG_HWCONFIG
 344
 345 /* define to use L1 as initial stack */
 346 #define CONFIG_L1_INIT_RAM
 347 #define CONFIG_SYS_INIT_RAM_LOCK
 348 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 351 /* The assembler doesn't like typecast */
 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 353                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 354                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 355 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 356 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 357                                                 GENERATED_GBL_DATA_SIZE)
 358 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 359 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 360 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 361
 362 /*
 363  * Serial Port
 364  */
 365 #define CONFIG_CONS_INDEX               1
 366 #define CONFIG_SYS_NS16550
 367 #define CONFIG_SYS_NS16550_SERIAL
 368 #define CONFIG_SYS_NS16550_REG_SIZE     1
 369 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 370 #define CONFIG_SYS_BAUDRATE_TABLE       \
 371         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 374 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 375 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 376
 377 /* Use the HUSH parser */
 378 #define CONFIG_SYS_HUSH_PARSER
 379 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 380
 381 /* pass open firmware flat tree */
 382 #define CONFIG_OF_LIBFDT
 383 #define CONFIG_OF_BOARD_SETUP
 384 #define CONFIG_OF_STDOUT_VIA_ALIAS
 385
 386 /* new uImage format support */
 387 #define CONFIG_FIT
 388 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 389
 390 /*
 391  * I2C
 392  */
 393 #define CONFIG_SYS_I2C
 394 #define CONFIG_SYS_I2C_FSL
 395 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 396 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 397 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 398 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 399 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 401 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 402 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 403 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 404 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 405 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 406 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 407 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 408 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 409 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 410 #define I2C_MUX_CH_DEFAULT      0x8
 411
 412
 413 /*
 414  * RapidIO
 415  */
 416 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 417 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 418 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 419 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 420 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 421 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 422 /*
 423  * for slave u-boot IMAGE instored in master memory space,
 424  * PHYS must be aligned based on the SIZE
 425  */
 426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
 429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 430 /*
 431  * for slave UCODE and ENV instored in master memory space,
 432  * PHYS must be aligned based on the SIZE
 433  */
 434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 435 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 436 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 437
 438 /* slave core release by master*/
 439 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 440 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 441
 442 /*
 443  * SRIO_PCIE_BOOT - SLAVE
 444  */
 445 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 446 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 447 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 448                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 449 #endif
 450
 451 /*
 452  * eSPI - Enhanced SPI
 453  */
 454 #ifdef CONFIG_SPI_FLASH
 455 #define CONFIG_FSL_ESPI
 456 #define CONFIG_SPI_FLASH_SST
 457 #define CONFIG_SPI_FLASH_STMICRO
 458 #if defined(CONFIG_T2080QDS)
 459 #define CONFIG_SPI_FLASH_SPANSION
 460 #elif defined(CONFIG_T2081QDS)
 461 #define CONFIG_SPI_FLASH_EON
 462 #endif
 463
 464 #define CONFIG_CMD_SF
 465 #define CONFIG_SF_DEFAULT_SPEED  10000000
 466 #define CONFIG_SF_DEFAULT_MODE    0
 467 #endif
 468
 469 /*
 470  * General PCI
 471  * Memory space is mapped 1-1, but I/O space must start from 0.
 472  */
 473 #define CONFIG_PCI              /* Enable PCI/PCIE */
 474 #define CONFIG_PCIE1            /* PCIE controler 1 */
 475 #define CONFIG_PCIE2            /* PCIE controler 2 */
 476 #define CONFIG_PCIE3            /* PCIE controler 3 */
 477 #define CONFIG_PCIE4            /* PCIE controler 4 */
 478 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 479 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 480 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 481 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 482 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 483 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 484 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 485 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 486 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 487 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 488 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 489
 490 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 491 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 492 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 493 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 494 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 495 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 496 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 497 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 498 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 499
 500 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 501 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 502 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 503 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 504 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 505 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 506 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 507 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 508 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 509
 510 /* controller 4, Base address 203000 */
 511 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 512 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 513 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 514 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 515 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 516 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 517 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 518
 519 #ifdef CONFIG_PCI
 520 #define CONFIG_PCI_INDIRECT_BRIDGE
 521 #define CONFIG_FSL_PCIE_RESET      /* need PCIe reset errata */
 522 #define CONFIG_NET_MULTI
 523 #define CONFIG_E1000
 524 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 525 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 526 #define CONFIG_DOS_PARTITION
 527 #endif
 528
 529 /* Qman/Bman */
 530 #ifndef CONFIG_NOBQFMAN
 531 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 532 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 533 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 534 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 535 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 536 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 537 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 538 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 539 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 540
 541 #define CONFIG_SYS_DPAA_FMAN
 542 #define CONFIG_SYS_DPAA_PME
 543 #define CONFIG_SYS_PMAN
 544 #define CONFIG_SYS_DPAA_DCE
 545 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 546 #define CONFIG_SYS_INTERLAKEN
 547
 548 /* Default address of microcode for the Linux Fman driver */
 549 #if defined(CONFIG_SPIFLASH)
 550 /*
 551  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 552  * env, so we got 0x110000.
 553  */
 554 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 555 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 556 #elif defined(CONFIG_SDCARD)
 557 /*
 558  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 559  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 560  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 561  */
 562 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 563 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1680)
 564 #elif defined(CONFIG_NAND)
 565 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 566 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 567 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 568 /*
 569  * Slave has no ucode locally, it can fetch this from remote. When implementing
 570  * in two corenet boards, slave's ucode could be stored in master's memory
 571  * space, the address can be mapped from slave TLB->slave LAW->
 572  * slave SRIO or PCIE outbound window->master inbound window->
 573  * master LAW->the ucode address in master's memory space.
 574  */
 575 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 576 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 577 #else
 578 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 579 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEFF00000
 580 #endif
 581 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 582 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 583 #endif /* CONFIG_NOBQFMAN */
 584
 585 #ifdef CONFIG_SYS_DPAA_FMAN
 586 #define CONFIG_FMAN_ENET
 587 #define CONFIG_PHYLIB_10G
 588 #define CONFIG_PHY_VITESSE
 589 #define CONFIG_PHY_REALTEK
 590 #define CONFIG_PHY_TERANETICS
 591 #define RGMII_PHY1_ADDR 0x1
 592 #define RGMII_PHY2_ADDR 0x2
 593 #define FM1_10GEC1_PHY_ADDR       0x3
 594 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 595 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 596 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 597 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 598 #endif
 599
 600 #ifdef CONFIG_FMAN_ENET
 601 #define CONFIG_MII              /* MII PHY management */
 602 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 603 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 604 #endif
 605
 606 /*
 607  * SATA
 608  */
 609 #ifdef CONFIG_FSL_SATA_V2
 610 #define CONFIG_LIBATA
 611 #define CONFIG_FSL_SATA
 612 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 613 #define CONFIG_SATA1
 614 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 615 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 616 #define CONFIG_SATA2
 617 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 618 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 619 #define CONFIG_LBA48
 620 #define CONFIG_CMD_SATA
 621 #define CONFIG_DOS_PARTITION
 622 #define CONFIG_CMD_EXT2
 623 #endif
 624
 625 /*
 626  * USB
 627  */
 628 #ifdef CONFIG_USB_EHCI
 629 #define CONFIG_CMD_USB
 630 #define CONFIG_USB_STORAGE
 631 #define CONFIG_USB_EHCI_FSL
 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 633 #define CONFIG_CMD_EXT2
 634 #define CONFIG_HAS_FSL_DR_USB
 635 #endif
 636
 637 /*
 638  * SDHC
 639  */
 640 #ifdef CONFIG_MMC
 641 #define CONFIG_CMD_MMC
 642 #define CONFIG_FSL_ESDHC
 643 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 645 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 646 #define CONFIG_GENERIC_MMC
 647 #define CONFIG_CMD_EXT2
 648 #define CONFIG_CMD_FAT
 649 #define CONFIG_DOS_PARTITION
 650 #endif
 651
 652 /*
 653  * Environment
 654  */
 655 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 656 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 657
 658 /*
 659  * Command line configuration.
 660  */
 661 #include <config_cmd_default.h>
 662
 663 #define CONFIG_CMD_DHCP
 664 #define CONFIG_CMD_ELF
 665 #define CONFIG_CMD_ERRATA
 666 #define CONFIG_CMD_GREPENV
 667 #define CONFIG_CMD_IRQ
 668 #define CONFIG_CMD_I2C
 669 #define CONFIG_CMD_MII
 670 #define CONFIG_CMD_PING
 671 #define CONFIG_CMD_SETEXPR
 672 #define CONFIG_CMD_REGINFO
 673 #define CONFIG_CMD_BDI
 674
 675 #ifdef CONFIG_PCI
 676 #define CONFIG_CMD_PCI
 677 #define CONFIG_CMD_NET
 678 #endif
 679
 680 /*
 681  * Miscellaneous configurable options
 682  */
 683 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 684 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 685 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 686 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 687 #define CONFIG_SYS_PROMPT       "=> "     /* Monitor Command Prompt */
 688 #ifdef CONFIG_CMD_KGDB
 689 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 690 #else
 691 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 692 #endif
 693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 694 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 695 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 696
 697 /*
 698  * For booting Linux, the board info and command line data
 699  * have to be in the first 64 MB of memory, since this is
 700  * the maximum mapped by the Linux kernel during initialization.
 701  */
 702 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 703 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 704
 705 #ifdef CONFIG_CMD_KGDB
 706 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 707 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 708 #endif
 709
 710 /*
 711  * Environment Configuration
 712  */
 713 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 714 #define CONFIG_BOOTFILE  "uImage"
 715 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 716
 717 /* default location for tftp and bootm */
 718 #define CONFIG_LOADADDR         1000000
 719 #define CONFIG_BAUDRATE         115200
 720 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 721 #define __USB_PHY_TYPE          utmi
 722
 723 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 724         "hwconfig=fsl_ddr:"                                     \
 725         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 726         "bank_intlv=auto;"                                      \
 727         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 728         "netdev=eth0\0"                                         \
 729         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 730         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 731         "tftpflash=tftpboot $loadaddr $uboot && "               \
 732         "protect off $ubootaddr +$filesize && "                 \
 733         "erase $ubootaddr +$filesize && "                       \
 734         "cp.b $loadaddr $ubootaddr $filesize && "               \
 735         "protect on $ubootaddr +$filesize && "                  \
 736         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 737         "consoledev=ttyS0\0"                                    \
 738         "ramdiskaddr=2000000\0"                                 \
 739         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 740         "fdtaddr=c00000\0"                                      \
 741         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 742         "bdev=sda3\0"                                           \
 743         "c=ffe\0"
 744
 745 /*
 746  * For emulation this causes u-boot to jump to the start of the
 747  * proof point app code automatically
 748  */
 749 #define CONFIG_PROOF_POINTS                             \
 750         "setenv bootargs root=/dev/$bdev rw "           \
 751         "console=$consoledev,$baudrate $othbootargs;"   \
 752         "cpu 1 release 0x29000000 - - -;"               \
 753         "cpu 2 release 0x29000000 - - -;"               \
 754         "cpu 3 release 0x29000000 - - -;"               \
 755         "cpu 4 release 0x29000000 - - -;"               \
 756         "cpu 5 release 0x29000000 - - -;"               \
 757         "cpu 6 release 0x29000000 - - -;"               \
 758         "cpu 7 release 0x29000000 - - -;"               \
 759         "go 0x29000000"
 760
 761 #define CONFIG_HVBOOT                           \
 762         "setenv bootargs config-addr=0x60000000; "      \
 763         "bootm 0x01000000 - 0x00f00000"
 764
 765 #define CONFIG_ALU                              \
 766         "setenv bootargs root=/dev/$bdev rw "           \
 767         "console=$consoledev,$baudrate $othbootargs;"   \
 768         "cpu 1 release 0x01000000 - - -;"               \
 769         "cpu 2 release 0x01000000 - - -;"               \
 770         "cpu 3 release 0x01000000 - - -;"               \
 771         "cpu 4 release 0x01000000 - - -;"               \
 772         "cpu 5 release 0x01000000 - - -;"               \
 773         "cpu 6 release 0x01000000 - - -;"               \
 774         "cpu 7 release 0x01000000 - - -;"               \
 775         "go 0x01000000"
 776
 777 #define CONFIG_LINUX                            \
 778         "setenv bootargs root=/dev/ram rw "             \
 779         "console=$consoledev,$baudrate $othbootargs;"   \
 780         "setenv ramdiskaddr 0x02000000;"                \
 781         "setenv fdtaddr 0x00c00000;"                    \
 782         "setenv loadaddr 0x1000000;"                    \
 783         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 784
 785 #define CONFIG_HDBOOT                                   \
 786         "setenv bootargs root=/dev/$bdev rw "           \
 787         "console=$consoledev,$baudrate $othbootargs;"   \
 788         "tftp $loadaddr $bootfile;"                     \
 789         "tftp $fdtaddr $fdtfile;"                       \
 790         "bootm $loadaddr - $fdtaddr"
 791
 792 #define CONFIG_NFSBOOTCOMMAND                   \
 793         "setenv bootargs root=/dev/nfs rw "     \
 794         "nfsroot=$serverip:$rootpath "          \
 795         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 796         "console=$consoledev,$baudrate $othbootargs;"   \
 797         "tftp $loadaddr $bootfile;"             \
 798         "tftp $fdtaddr $fdtfile;"               \
 799         "bootm $loadaddr - $fdtaddr"
 800
 801 #define CONFIG_RAMBOOTCOMMAND                           \
 802         "setenv bootargs root=/dev/ram rw "             \
 803         "console=$consoledev,$baudrate $othbootargs;"   \
 804         "tftp $ramdiskaddr $ramdiskfile;"               \
 805         "tftp $loadaddr $bootfile;"                     \
 806         "tftp $fdtaddr $fdtfile;"                       \
 807         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 808
 809 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 810
 811 #ifdef CONFIG_SECURE_BOOT
 812 #include <asm/fsl_secure_boot.h>
 813 #undef CONFIG_CMD_USB
 814 #endif
 815
 816 #endif  /* __T208xQDS_H */