include/configs/calimain.h

   1 /*
   2  * Copyright (C) 2011-2014 OMICRON electronics GmbH
   3  *
   4  * Based on da850evm.h. Original Copyrights follow:
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * Board
  17  */
  18 #define CONFIG_DRIVER_TI_EMAC
  19 #define MACH_TYPE_CALIMAIN      3528
  20 #define CONFIG_MACH_TYPE        MACH_TYPE_CALIMAIN
  21 #define CONFIG_SYS_GENERIC_BOARD
  22
  23 /*
  24  * SoC Configuration
  25  */
  26 #define CONFIG_MACH_DAVINCI_CALIMAIN
  27 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  28 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  29 #define CONFIG_SYS_OSCIN_FREQ           calimain_get_osc_freq()
  30 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  31 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  32 #define CONFIG_SYS_TEXT_BASE            0x60000000
  33 #define CONFIG_DA850_LOWLEVEL
  34 #define CONFIG_SYS_DA850_PLL_INIT
  35 #define CONFIG_SYS_DA850_DDR_INIT
  36 #define CONFIG_ARCH_CPU_INIT
  37 #define CONFIG_DA8XX_GPIO
  38 #define CONFIG_HW_WATCHDOG
  39 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
  40 #define CONFIG_SYS_WDT_PERIOD_LOW \
  41         (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
  42 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
  43 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  44
  45 /*
  46  * PLL configuration
  47  */
  48 #define CONFIG_SYS_DV_CLKMODE          0
  49 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  50 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  51 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  52 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  53 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  54 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  55 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  56 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  57
  58 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  59 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  60 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  61 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  62
  63 #define CONFIG_SYS_DA850_PLL0_PLLM \
  64         ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
  65 #define CONFIG_SYS_DA850_PLL1_PLLM \
  66         ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
  67
  68 /*
  69  * DDR2 memory configuration
  70  */
  71 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  72                                         DV_DDR_PHY_EXT_STRBEN | \
  73                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  74
  75 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  76         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
  77         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
  78         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  79         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  80         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  81         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  82         (0x3 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  83         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  84
  85 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  86 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0
  87
  88 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  89         (16 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  90         (1 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  91         (1 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  92         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  93         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  94         (7 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  95         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  96         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  97
  98 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  99         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 100         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 101         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 102         (18 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 103         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 104         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 105         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 106
 107 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x000003FF
 108 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
 109
 110 /*
 111  * Flash memory timing
 112  */
 113
 114 #define CONFIG_SYS_DA850_CS2CFG (       \
 115         DAVINCI_ABCR_WSETUP(2) |        \
 116         DAVINCI_ABCR_WSTROBE(5) |       \
 117         DAVINCI_ABCR_WHOLD(3) |         \
 118         DAVINCI_ABCR_RSETUP(1) |        \
 119         DAVINCI_ABCR_RSTROBE(14) |      \
 120         DAVINCI_ABCR_RHOLD(0) |         \
 121         DAVINCI_ABCR_TA(3) |            \
 122         DAVINCI_ABCR_ASIZE_16BIT)
 123
 124 /* single 64 MB NOR flash device connected to CS2 and CS3 */
 125 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
 126
 127 /*
 128  * Memory Info
 129  */
 130 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
 131 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 132 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
 133 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 134
 135 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
 136         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
 137         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
 138         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
 139         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
 140         DAVINCI_SYSCFG_SUSPSRC_I2C)
 141
 142 /* memtest start addr */
 143 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
 144
 145 /* memtest will be run on 16MB */
 146 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (16 << 20))
 147
 148 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
 149
 150 /*
 151  * Serial Driver info
 152  */
 153 #define CONFIG_SYS_NS16550
 154 #define CONFIG_SYS_NS16550_SERIAL
 155 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 156 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 157 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 158 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 159 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 160
 161 #define CONFIG_ENV_IS_IN_FLASH
 162 #define CONFIG_FLASH_CFI_DRIVER
 163 #define CONFIG_SYS_FLASH_CFI
 164 #define CONFIG_SYS_FLASH_PROTECTION
 165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 166 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
 167 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
 168 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 169 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
 170 #define CONFIG_ENV_ADDR \
 171         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
 172 #define CONFIG_ENV_SIZE             (128 << 10)
 173 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 174 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
 175 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
 176 #define CONFIG_SYS_MAX_FLASH_SECT \
 177         ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
 178
 179 /*
 180  * Network & Ethernet Configuration
 181  */
 182 #ifdef CONFIG_DRIVER_TI_EMAC
 183 #define CONFIG_EMAC_MDIO_PHY_NUM        1
 184 #define CONFIG_MII
 185 #define CONFIG_BOOTP_DNS
 186 #define CONFIG_BOOTP_DNS2
 187 #define CONFIG_BOOTP_SEND_HOSTNAME
 188 #define CONFIG_NET_RETRY_COUNT  10
 189 #endif
 190
 191 /*
 192  * U-Boot general configuration
 193  */
 194 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
 195 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size  */
 196 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 197 #define CONFIG_SYS_MAXARGS     16 /* max number of command args */
 198 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 199 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
 200 #define CONFIG_LOADADDR        0xc0700000
 201 #define CONFIG_VERSION_VARIABLE
 202 #define CONFIG_AUTO_COMPLETE
 203 #define CONFIG_SYS_HUSH_PARSER
 204 #define CONFIG_CMDLINE_EDITING
 205 #define CONFIG_SYS_LONGHELP
 206 #define CONFIG_CRC32_VERIFY
 207 #define CONFIG_MX_CYCLIC
 208
 209 /*
 210  * Linux Information
 211  */
 212 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
 213 #define CONFIG_CMDLINE_TAG
 214 #define CONFIG_REVISION_TAG
 215 #define CONFIG_SETUP_MEMORY_TAGS
 216 #define CONFIG_BOOTARGS           ""
 217 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
 218 #define CONFIG_BOOTDELAY          0
 219 #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
 220 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 221 #define CONFIG_RESET_TO_RETRY
 222
 223 /*
 224  * Default environment settings
 225  * gpio0 = button, gpio1 = led green, gpio2 = led red
 226  * verify = n ... disable kernel checksum verification for faster booting
 227  */
 228 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 229         "tftpdir=calimero\0"                                            \
 230         "flashkernel=tftpboot $loadaddr $tftpdir/uImage; "              \
 231                 "erase 0x60800000 +0x400000; "                          \
 232                 "cp.b $loadaddr 0x60800000 $filesize\0"                 \
 233         "flashrootfs="                                                  \
 234                 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; "            \
 235                 "erase 0x60c00000 +0x2e00000; "                         \
 236                 "cp.b $loadaddr 0x60c00000 $filesize\0"                 \
 237         "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "           \
 238                 "protect off all; "                                     \
 239                 "erase 0x60000000 +0x80000; "                           \
 240                 "cp.b $loadaddr 0x60000000 $filesize\0"                 \
 241         "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "             \
 242                 "erase 0x60080000 +0x780000; "                          \
 243                 "cp.b $loadaddr 0x60080000 $filesize\0"                 \
 244         "erase_persistent=erase 0x63a00000 +0x600000;\0"                \
 245         "bootnor=setenv bootargs console=ttyS2,115200n8 "               \
 246                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 247                 "rootwait ethaddr=$ethaddr; "                           \
 248                 "gpio c 1; gpio s 2; bootm 0x60800000\0"                \
 249         "bootrlk=gpio s 1; gpio s 2;"                                   \
 250                 "setenv bootargs console=ttyS2,115200n8 "               \
 251                 "ethaddr=$ethaddr; bootm 0x60080000\0"                  \
 252         "boottftp=setenv bootargs console=ttyS2,115200n8 "              \
 253                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 254                 "rootwait ethaddr=$ethaddr; "                           \
 255                 "tftpboot $loadaddr $tftpdir/uImage;"                   \
 256                 "gpio c 1; gpio s 2; bootm $loadaddr\0"                 \
 257         "checkupdate=if test -n $update_flag; then "                    \
 258                 "echo Previous update failed - starting RLK; "          \
 259                 "run bootrlk; fi; "                                     \
 260                 "if test -n $initial_setup; then "                      \
 261                 "echo Running initial setup procedure; "                \
 262                 "sleep 1; run flashall; fi\0"                           \
 263         "product=accessory\0"                                           \
 264         "serial=XX12345\0"                                              \
 265         "checknor="                                                     \
 266                 "if gpio i 0; then run bootnor; fi;\0"                  \
 267         "checkrlk="                                                     \
 268                 "if gpio i 0; then run bootrlk; fi;\0"                  \
 269         "checkbutton="                                                  \
 270                 "run checknor; sleep 1;"                                \
 271                 "run checknor; sleep 1;"                                \
 272                 "run checknor; sleep 1;"                                \
 273                 "run checknor; sleep 1;"                                \
 274                 "run checknor;"                                         \
 275                 "gpio s 1; gpio s 2;"                                   \
 276                 "echo ---- Release button to boot RLK ----;"            \
 277                 "run checkrlk; sleep 1;"                                \
 278                 "run checkrlk; sleep 1;"                                \
 279                 "run checkrlk; sleep 1;"                                \
 280                 "run checkrlk; sleep 1;"                                \
 281                 "run checkrlk; sleep 1;"                                \
 282                 "run checkrlk;"                                         \
 283                 "echo ---- Factory reset requested ----;"               \
 284                 "gpio c 1;"                                             \
 285                 "setenv factory_reset true;"                            \
 286                 "saveenv;"                                              \
 287                 "run bootnor;\0"                                        \
 288         "flashall=run flashrlk;"                                        \
 289                 "run flashkernel;"                                      \
 290                 "run flashrootfs;"                                      \
 291                 "setenv erase_datafs true;"                             \
 292                 "setenv initial_setup;"                                 \
 293                 "saveenv;"                                              \
 294                 "run bootnor;\0"                                        \
 295         "verify=n\0"                                                    \
 296         "clearenv=protect off all;"                                     \
 297                 "erase 0x60040000 +0x40000;\0"                          \
 298         "bootlimit=3\0"                                                 \
 299         "altbootcmd=run bootrlk\0"
 300
 301 #define CONFIG_PREBOOT                  \
 302         "echo Version: $ver; "          \
 303         "echo Serial: $serial; "        \
 304         "echo MAC: $ethaddr; "          \
 305         "echo Product: $product; "      \
 306         "gpio c 1; gpio c 2;"
 307
 308 /*
 309  * U-Boot commands
 310  */
 311 #define CONFIG_CMD_ENV
 312 #define CONFIG_CMD_ASKENV
 313 #define CONFIG_CMD_DHCP
 314 #define CONFIG_CMD_DIAG
 315 #define CONFIG_CMD_MII
 316 #define CONFIG_CMD_PING
 317 #define CONFIG_CMD_SAVES
 318 #define CONFIG_CMD_GPIO
 319
 320 #ifndef CONFIG_DRIVER_TI_EMAC
 321 #undef CONFIG_CMD_DHCP
 322 #undef CONFIG_CMD_MII
 323 #undef CONFIG_CMD_PING
 324 #endif
 325
 326 /* additions for new relocation code, must added to all boards */
 327 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 328 /* initial stack pointer in internal SRAM */
 329 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 330
 331 #define CONFIG_BOOTCOUNT_LIMIT
 332 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
 333 #define CONFIG_SYS_BOOTCOUNT_ADDR       DAVINCI_RTC_BASE
 334
 335 #ifndef __ASSEMBLY__
 336 int calimain_get_osc_freq(void);
 337 #endif
 338
 339 #endif /* __CONFIG_H */