3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
17 #define CONFIG_DISPLAY_BOARDINFO
19 #ifdef CONFIG_DBAU1000
20 /* Also known as Merlot */
22 #ifdef CONFIG_DBAU1100
24 #ifdef CONFIG_DBAU1500
26 #ifdef CONFIG_DBAU1550
29 #error "No valid board set"
35 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
37 #define CONFIG_BAUDRATE 115200
41 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
42 #undef CONFIG_BOOTARGS
44 #define CONFIG_EXTRA_ENV_SETTINGS \
45 "addmisc=setenv bootargs ${bootargs} " \
46 "console=ttyS0,${baudrate} " \
48 "bootfile=/tftpboot/vmlinux.srec\0" \
49 "load=tftp 80500000 ${u-boot}\0" \
52 #ifdef CONFIG_DBAU1550
53 /* Boot from flash by default, revert to bootp */
54 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
55 #else /* CONFIG_DBAU1550 */
56 #define CONFIG_BOOTCOMMAND "bootp;bootm"
57 #endif /* CONFIG_DBAU1550 */
63 #define CONFIG_BOOTP_BOOTFILESIZE
64 #define CONFIG_BOOTP_BOOTPATH
65 #define CONFIG_BOOTP_GATEWAY
66 #define CONFIG_BOOTP_HOSTNAME
70 * Command line configuration.
72 #undef CONFIG_CMD_BEDBUG
77 #ifdef CONFIG_DBAU1550
81 #undef CONFIG_CMD_PCMCIA
85 #define CONFIG_CMD_IDE
86 #define CONFIG_CMD_DHCP
92 * Miscellaneous configurable options
94 #define CONFIG_SYS_LONGHELP /* undef to save memory */
96 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
98 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
99 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
100 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
102 #define CONFIG_SYS_MALLOC_LEN 128*1024
104 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
106 #define CONFIG_SYS_MHZ 396
108 #if (CONFIG_SYS_MHZ % 12) != 0
109 #error "Invalid CPU frequency - must be multiple of 12!"
112 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
114 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
116 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
118 #define CONFIG_SYS_MEMTEST_START 0x80100000
119 #define CONFIG_SYS_MEMTEST_END 0x80800000
121 /*-----------------------------------------------------------------------
122 * FLASH and environment organization
124 #ifdef CONFIG_DBAU1550
126 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
129 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
130 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
132 #else /* CONFIG_DBAU1550 */
134 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
135 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
137 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
138 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
140 #endif /* CONFIG_DBAU1550 */
142 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
144 #define CONFIG_SYS_FLASH_CFI 1
145 #define CONFIG_FLASH_CFI_DRIVER 1
147 /* The following #defines are needed to get flash environment right */
148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
149 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
151 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
153 /* We boot from this flash, selected with dip switch */
154 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
156 /* timeout values are in ticks */
157 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
158 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
160 #define CONFIG_ENV_IS_NOWHERE 1
162 /* Address and size of Primary Environment Sector */
163 #define CONFIG_ENV_ADDR 0xB0030000
164 #define CONFIG_ENV_SIZE 0x10000
166 #define CONFIG_FLASH_16BIT
168 #define CONFIG_NR_DRAM_BANKS 2
171 #ifdef CONFIG_DBAU1550
177 #define CONFIG_MEMSIZE_IN_BYTES
179 #ifndef CONFIG_DBAU1550
180 /*---ATA PCMCIA ------------------------------------*/
181 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
182 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
183 #define CONFIG_PCMCIA_SLOT_A
185 #define CONFIG_ATAPI 1
186 #define CONFIG_MAC_PARTITION 1
188 /* We run CF in "true ide" mode or a harddrive via pcmcia */
189 #define CONFIG_IDE_PCMCIA 1
191 /* We only support one slot for now */
192 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
193 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
195 #undef CONFIG_IDE_LED /* LED for ide not supported */
196 #undef CONFIG_IDE_RESET /* reset for ide not supported */
198 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
200 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
202 /* Offset for data I/O */
203 #define CONFIG_SYS_ATA_DATA_OFFSET 8
205 /* Offset for normal register accesses */
206 #define CONFIG_SYS_ATA_REG_OFFSET 0
208 /* Offset for alternate registers */
209 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
210 #endif /* CONFIG_DBAU1550 */
212 /*-----------------------------------------------------------------------
213 * Cache Configuration
215 #define CONFIG_SYS_DCACHE_SIZE 16384
216 #define CONFIG_SYS_ICACHE_SIZE 16384
217 #define CONFIG_SYS_CACHELINE_SIZE 32
219 #endif /* __CONFIG_H */