2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
12 #define CONFIG_EXYNOS5 /* Exynos5 Family */
14 #include "exynos-common.h"
16 #define CONFIG_SYS_CACHELINE_SIZE 64
17 #define CONFIG_ARCH_EARLY_INIT_R
18 #define CONFIG_EXYNOS_SPL
20 /* Allow tracing to be enabled */
22 #define CONFIG_CMD_TRACE
23 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
24 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
25 #define CONFIG_TRACE_EARLY
26 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
29 /* Enable ACE acceleration for SHA1 and SHA256 */
30 #define CONFIG_EXYNOS_ACE_SHA
31 #define CONFIG_SHA_HW_ACCEL
33 /* Power Down Modes */
34 #define S5P_CHECK_SLEEP 0x00000BAD
35 #define S5P_CHECK_DIDLE 0xBAD00000
36 #define S5P_CHECK_LPA 0xABAD0000
38 /* Offset for inform registers */
39 #define INFORM0_OFFSET 0x800
40 #define INFORM1_OFFSET 0x804
41 #define INFORM2_OFFSET 0x808
42 #define INFORM3_OFFSET 0x80c
44 /* select serial console configuration */
45 #define CONFIG_BAUDRATE 115200
46 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
47 #define CONFIG_SILENT_CONSOLE
48 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
49 #define CONFIG_CONSOLE_MUX
52 #define CONFIG_CROS_EC /* CROS_EC protocol */
53 #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
54 #define CONFIG_CMD_CROS_EC
55 #define CONFIG_KEYBOARD
57 /* Console configuration */
58 #define EXYNOS_DEVICE_SETTINGS \
59 "stdin=serial,cros-ec-keyb\0" \
60 "stdout=serial,lcd\0" \
63 #define CONFIG_EXTRA_ENV_SETTINGS \
64 EXYNOS_DEVICE_SETTINGS
66 #define CONFIG_CMD_PING
67 #define CONFIG_CMD_ELF
68 #define CONFIG_CMD_NET
69 #define CONFIG_CMD_HASH
71 /* Thermal Management Unit */
72 #define CONFIG_EXYNOS_TMU
73 #define CONFIG_CMD_DTT
74 #define CONFIG_TMU_CMD_DTT
78 #define CONFIG_CMD_TPM
79 #define CONFIG_TPM_TIS_I2C
80 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
81 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
84 #define COPY_BL2_FNPTR_ADDR 0x02020030
85 #define CONFIG_SUPPORT_EMMC_BOOT
87 #define CONFIG_SPL_LIBCOMMON_SUPPORT
88 #define CONFIG_SPL_GPIO_SUPPORT
90 /* specific .lds file */
91 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
93 /* Miscellaneous configurable options */
94 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
95 /* Boot Argument Buffer Size */
96 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
98 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
99 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
101 #define CONFIG_RD_LVL
103 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
104 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
105 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
106 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
107 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
108 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
109 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
110 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
111 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
112 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
113 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
114 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
115 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
116 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
117 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
118 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
120 #define CONFIG_SYS_MONITOR_BASE 0x00000000
122 #define CONFIG_SYS_MMC_ENV_DEV 0
124 #define CONFIG_SECURE_BL1_ONLY
126 /* Secure FW size configuration */
127 #ifdef CONFIG_SECURE_BL1_ONLY
128 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
130 #define CONFIG_SEC_FW_SIZE 0
133 /* Configuration of BL1, BL2, ENV Blocks on mmc */
134 #define CONFIG_RES_BLOCK_SIZE (512)
135 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
136 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
137 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
139 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
140 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
142 /* Store environment at the end of a 4 MB SPI flash */
143 #define FLASH_SIZE (0x4 << 20)
144 #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
146 /* U-boot copy size from boot Media to DRAM.*/
147 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
148 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
150 #define CONFIG_SPI_BOOTING
151 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
152 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
155 #define CONFIG_SYS_I2C_INIT_BOARD
156 #define CONFIG_SYS_I2C
157 #define CONFIG_CMD_I2C
158 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
159 #define CONFIG_SYS_I2C_S3C24X0
160 #define CONFIG_I2C_MULTI_BUS
161 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
162 #define CONFIG_I2C_EDID
165 #define CONFIG_ENV_IS_IN_SPI_FLASH
166 #define CONFIG_SPI_FLASH
167 #define CONFIG_ENV_SPI_BASE 0x12D30000
169 #ifdef CONFIG_SPI_FLASH
170 #define CONFIG_EXYNOS_SPI
171 #define CONFIG_CMD_SF
172 #define CONFIG_CMD_SPI
173 #define CONFIG_SPI_FLASH_WINBOND
174 #define CONFIG_SPI_FLASH_GIGADEVICE
175 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
176 #define CONFIG_SF_DEFAULT_SPEED 50000000
177 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
178 #define CONFIG_OF_SPI
181 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
182 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
183 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
184 #define CONFIG_ENV_SPI_BUS 1
185 #define CONFIG_ENV_SPI_MAX_HZ 50000000
190 #define CONFIG_POWER_I2C
191 #define CONFIG_POWER_TPS65090
193 /* Ethernet Controllor Driver */
194 #ifdef CONFIG_CMD_NET
195 #define CONFIG_SMC911X
196 #define CONFIG_SMC911X_BASE 0x5000000
197 #define CONFIG_SMC911X_16_BIT
198 #define CONFIG_ENV_SROM_BANK 1
199 #endif /*CONFIG_CMD_NET*/
201 /* Enable PXE Support */
202 #ifdef CONFIG_CMD_NET
203 #define CONFIG_CMD_PXE
208 #define CONFIG_CMD_HASH
209 #define CONFIG_HASH_VERIFY
211 #define CONFIG_SHA256
213 /* Enable Time Command */
214 #define CONFIG_CMD_TIME
216 #define CONFIG_CMD_BOOTZ
218 #define CONFIG_CMD_GPIO
221 #define CONFIG_USB_BOOTING
222 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
223 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
224 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
226 /* Enable FIT support and comparison */
228 #define CONFIG_FIT_BEST_MATCH
230 #endif /* __CONFIG_EXYNOS5_COMMON_H */