include/configs/km82xx.h

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15
  16 #define CONFIG_MPC8247
  17 /* MGCOGE */
  18 #if defined(CONFIG_MGCOGE)
  19 #define CONFIG_HOSTNAME         mgcoge
  20 #define CONFIG_KM_BOARD_EXTRA_ENV       ""
  21
  22 /* MGCOGE3NE */
  23 #elif defined(CONFIG_MGCOGE3NE)
  24 #define CONFIG_HOSTNAME         mgcoge3ne
  25 #define CONFIG_KM_82XX
  26 #define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
  27
  28 #else
  29 #error ("Board unsupported")
  30 #endif
  31
  32 #define CONFIG_SYS_GENERIC_BOARD
  33 #define CONFIG_DISPLAY_BOARDINFO
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  36
  37 #define CONFIG_MISC_INIT_R
  38
  39 /* include common defines/options for all Keymile boards */
  40 #include "km/keymile-common.h"
  41 #include "km/km-powerpc.h"
  42
  43 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  44 #define CONFIG_SYS_FLASH_BASE           0xFE000000
  45 #define CONFIG_SYS_FLASH_SIZE           32
  46 #define CONFIG_SYS_FLASH_CFI
  47 #define CONFIG_FLASH_CFI_DRIVER
  48
  49 /* MGCOGE */
  50 #if defined(CONFIG_MGCOGE)
  51 #define CONFIG_SYS_MAX_FLASH_BANKS      3
  52 /* max num of sects on one chip */
  53 #define CONFIG_SYS_MAX_FLASH_SECT       512
  54
  55 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  56 #define CONFIG_SYS_FLASH_SIZE_1 32
  57 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
  58 #define CONFIG_SYS_FLASH_SIZE_2 32
  59
  60 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  61                                         CONFIG_SYS_FLASH_BASE_1, \
  62                                         CONFIG_SYS_FLASH_BASE_2 }
  63 #define MTDIDS_DEFAULT          "nor3=app"
  64
  65 /*
  66  * Bank 1 - 60x bus SDRAM
  67  */
  68 #define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
  69 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
  70
  71 /* SDRAM initialization values
  72 */
  73
  74 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  75                            ORxS_SDAM_MSK)               |\
  76                         ORxS_BPD_8                      |\
  77                         ORxS_ROWST_PBI0_A7              |\
  78                         ORxS_NUMR_13)
  79
  80 #define CONFIG_SYS_PSDMR (                              \
  81                         PSDMR_SDAM_A14_IS_A5            |\
  82                         PSDMR_BSMA_A14_A16              |\
  83                         PSDMR_SDA10_PBI0_A9             |\
  84                         PSDMR_RFRC_5_CLK                |\
  85                         PSDMR_PRETOACT_2W               |\
  86                         PSDMR_ACTTORW_2W                |\
  87                         PSDMR_LDOTOPRE_1C               |\
  88                         PSDMR_WRC_1C                    |\
  89                         PSDMR_CL_2)
  90
  91 /* MGCOGE3NE */
  92 #elif defined(CONFIG_MGCOGE3NE)
  93 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
  94 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
  95                                                  * max num of sects on one
  96                                                  * chip
  97                                                  */
  98
  99 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
 100 #define CONFIG_SYS_FLASH_SIZE_1 128
 101
 102 #define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
 103
 104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 105                                         CONFIG_SYS_FLASH_BASE_1 }
 106
 107 #define MTDIDS_DEFAULT          "nor2=app"
 108
 109 /*
 110  * Bank 1 - 60x bus SDRAM
 111  * mgcoge3ne has 256MB
 112  * mgcoge2ne has 128MB
 113  */
 114 #define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
 115 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
 116
 117 #define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
 118                            ORxS_SDAM_MSK)               |\
 119                         ORxS_BPD_4                      |\
 120                         ORxS_NUMR_13                    |\
 121                         ORxS_IBID)
 122
 123 #define CONFIG_SYS_PSDMR (                              \
 124                         PSDMR_PBI                       |\
 125                         PSDMR_RFEN                      |\
 126                         PSDMR_BSMA_A13_A15              |\
 127                         PSDMR_RFRC_5_CLK                |\
 128                         PSDMR_PRETOACT_2W               |\
 129                         PSDMR_ACTTORW_2W                |\
 130                         PSDMR_LDOTOPRE_1C               |\
 131                         PSDMR_WRC_1C                    |\
 132                         PSDMR_CL_2)
 133
 134 #define CONFIG_SYS_SDRAM_LIST   {                                       \
 135         {       .size   = 256 << 20,                                    \
 136                 .or1    = ORxS_ROWST_PBI1_A4,                           \
 137                 .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
 138         },                                                              \
 139         {       .size   = 128 << 20,                                    \
 140                 .or1    = ORxS_ROWST_PBI1_A5,                           \
 141                 .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
 142         },                                                              \
 143 }
 144 #endif /* defined(CONFIG_MGCOGE3NE) */
 145
 146 /* include further common stuff for all keymile 82xx boards */
 147 /*
 148  * Select serial console configuration
 149  *
 150  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 151  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 152  * for SCC).
 153  */
 154 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
 155 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
 156 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
 157 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
 158 #define CONFIG_SYS_SMC_RXBUFLEN 128
 159 #define CONFIG_SYS_MAXIDLE      10
 160
 161 /*
 162  * Select ethernet configuration
 163  *
 164  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 165  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 166  * SCC, 1-3 for FCC)
 167  *
 168  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 169  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 170  * must be unset.
 171  */
 172 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
 173 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
 174 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
 175
 176 #define CONFIG_ETHER_INDEX      4
 177 #define CONFIG_HAS_ETH0
 178 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
 179
 180 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 181
 182 #ifndef CONFIG_8260_CLKIN
 183 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 184 #endif
 185
 186 #define BOOTFLASH_START         0xFE000000
 187
 188 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
 189
 190 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 191         "app:"                                                          \
 192                 "768k(u-boot),"                                         \
 193                 "128k(env),"                                            \
 194                 "128k(envred),"                                         \
 195                 "3072k(free),"                                          \
 196                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 197
 198 /*
 199  * Default environment settings
 200  */
 201 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 202         CONFIG_KM_BOARD_EXTRA_ENV                                       \
 203         CONFIG_KM_DEF_ENV                                               \
 204         "unlock=yes\0"                                                  \
 205         "newenv="                                                       \
 206                 "prot off 0xFE0C0000 +0x40000 && "                      \
 207                 "era 0xFE0C0000 +0x40000\0"                             \
 208         "arch=ppc_82xx\0"                                       \
 209         ""
 210
 211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 212
 213 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 214
 215 #define CONFIG_ENV_IS_IN_FLASH
 216
 217 #ifdef CONFIG_ENV_IS_IN_FLASH
 218 #define CONFIG_ENV_SECT_SIZE    0x20000
 219 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 220                                         CONFIG_SYS_MONITOR_LEN)
 221 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 222
 223 /* Address and size of Redundant Environment Sector     */
 224 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 225                                                 CONFIG_ENV_SECT_SIZE)
 226 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 227 #endif /* CONFIG_ENV_IS_IN_FLASH */
 228
 229 /* enable I2C and select the hardware/software driver */
 230 #define CONFIG_SYS_I2C
 231 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 232 #define CONFIG_SYS_I2C_INIT_BOARD
 233 #define CONFIG_SYS_NUM_I2C_BUSES        3
 234 #define CONFIG_SYS_I2C_MAX_HOPS         1
 235 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 236 #define CONFIG_SYS_I2C_SPEED            CONFIG_SYS_I2C_SOFT_SPEED
 237 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 238 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 239                         {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
 240                         {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
 241
 242 #define CONFIG_KM_IVM_BUS               1       /* I2C2 (Mux-Port 1)*/
 243 #define CONFIG_KM_I2C_ABORT
 244
 245 /*
 246  * Software (bit-bang) I2C driver configuration
 247  */
 248
 249 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 250 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 251 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 252 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 253 #define I2C_SDA(bit)    do { \
 254                                 if (bit) \
 255                                         iop->pdat |=  0x00010000; \
 256                                 else \
 257                                         iop->pdat &= ~0x00010000; \
 258                         } while (0)
 259 #define I2C_SCL(bit)    do { \
 260                                 if (bit) \
 261                                         iop->pdat |=  0x00020000; \
 262                                 else \
 263                                         iop->pdat &= ~0x00020000; \
 264                         } while (0)
 265 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 266
 267 #ifndef __ASSEMBLY__
 268 void set_sda(int state);
 269 void set_scl(int state);
 270 int get_sda(void);
 271 int get_scl(void);
 272 #endif
 273
 274 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 275 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 276 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 277 #define CONFIG_SYS_DTT_MAX_TEMP 70
 278 #define CONFIG_SYS_DTT_HYSTERESIS       3
 279 #define CONFIG_SYS_DTT_BUS_NUM          2
 280
 281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 282
 283 #define CONFIG_SYS_IMMR         0xF0000000
 284
 285 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 286 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 287 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 288                                                 GENERATED_GBL_DATA_SIZE)
 289 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 290
 291 /* Hard reset configuration word */
 292 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 293
 294 /* No slaves */
 295 #define CONFIG_SYS_HRCW_SLAVE1          0
 296 #define CONFIG_SYS_HRCW_SLAVE2          0
 297 #define CONFIG_SYS_HRCW_SLAVE3          0
 298 #define CONFIG_SYS_HRCW_SLAVE4          0
 299 #define CONFIG_SYS_HRCW_SLAVE5          0
 300 #define CONFIG_SYS_HRCW_SLAVE6          0
 301 #define CONFIG_SYS_HRCW_SLAVE7          0
 302
 303 /* Initial Memory map for Linux */
 304 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 305
 306 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 307 #if defined(CONFIG_CMD_KGDB)
 308 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 309 #endif
 310
 311 #define CONFIG_SYS_HID0_INIT            0
 312 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 313
 314 #define CONFIG_SYS_HID2         0
 315
 316 #define CONFIG_SYS_SIUMCR               0x4020c200
 317 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 318 #define CONFIG_SYS_BCR                  0x10000000
 319 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 320
 321 /*
 322  *-----------------------------------------------------------------------
 323  * RMR - Reset Mode Register                                     5-5
 324  *-----------------------------------------------------------------------
 325  * turn on Checkstop Reset Enable
 326  */
 327 #define CONFIG_SYS_RMR         0
 328
 329 /*
 330  *-----------------------------------------------------------------------
 331  * TMCNTSC - Time Counter Status and Control                     4-40
 332  *-----------------------------------------------------------------------
 333  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 334  * and enable Time Counter
 335  */
 336 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 337
 338 /*
 339  *-----------------------------------------------------------------------
 340  * PISCR - Periodic Interrupt Status and Control                 4-42
 341  *-----------------------------------------------------------------------
 342  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 343  * Periodic timer
 344  */
 345 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 346
 347 /*
 348  *-----------------------------------------------------------------------
 349  * RCCR - RISC Controller Configuration                         13-7
 350  *-----------------------------------------------------------------------
 351  */
 352 #define CONFIG_SYS_RCCR        0
 353
 354 /*
 355  * Init Memory Controller:
 356  *
 357  * Bank Bus     Machine PortSz  Device
 358  * ---- ---     ------- ------  ------
 359  *  0   60x     GPCM     8 bit  FLASH
 360  *  1   60x     SDRAM   32 bit  SDRAM
 361  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 362  *  5   60x     GPCM    16 bit  CFG-Flash
 363  *
 364  */
 365 /* Bank 0 - FLASH
 366  */
 367 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 368                          BRx_PS_8                       |\
 369                          BRx_MS_GPCM_P                  |\
 370                          BRx_V)
 371
 372 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 373                          ORxG_CSNT                      |\
 374                          ORxG_ACS_DIV2                  |\
 375                          ORxG_SCY_5_CLK                 |\
 376                          ORxG_TRLX)
 377
 378 #define CONFIG_SYS_MPTPR       0x1800
 379
 380 /*
 381  *-----------------------------------------------------------------------------
 382  * Address for Mode Register Set (MRS) command
 383  *-----------------------------------------------------------------------------
 384  */
 385 #define CONFIG_SYS_MRS_OFFS     0x00000110
 386 #define CONFIG_SYS_PSRT        0x0e
 387
 388 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 389                          BRx_PS_64              |\
 390                          BRx_MS_SDRAM_P         |\
 391                          BRx_V)
 392
 393 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 394
 395 /*
 396  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 397  */
 398 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 399 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 400
 401 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 402                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 403
 404 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 405                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 406                          ORxG_SCY_3_CLK | ORxG_TRLX)
 407
 408 /*
 409  * BFTICU board FPGA on CS4 initialization values
 410  */
 411 #define CONFIG_SYS_FPGA_BASE    0x40000000
 412 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 413
 414 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 415                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 416
 417 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 418                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 419                          ORxG_SCY_3_CLK | ORxG_TRLX)
 420
 421 /*
 422  * CFG-Flash on CS5 initialization values
 423  */
 424 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 425                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 426
 427 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 428                                  CONFIG_SYS_FLASH_SIZE_2) |\
 429                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 430                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 431
 432 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 433
 434 /* pass open firmware flat tree */
 435 #define CONFIG_FIT              1
 436 #define CONFIG_OF_LIBFDT        1
 437 #define CONFIG_OF_BOARD_SETUP   1
 438
 439 #define OF_TBCLK                (bd->bi_busfreq / 4)
 440 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 441
 442 #endif /* __CONFIG_H */