include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1 /* E300 family */
  27 #define CONFIG_QE               1 /* Has QE */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31 #define CONFIG_HOSTNAME         kmeter1
  32
  33 /* include common defines/options for all Keymile boards */
  34 #include "keymile-common.h"
  35
  36 #define CONFIG_KM_UBI_PARTITION_NAME    "ubi0"
  37
  38 #define MTDIDS_DEFAULT          "nor0=boot"
  39 #define MTDPARTS_DEFAULT        \
  40         "mtdparts=boot:768k(u-boot),128k(env),128k(envred),"    \
  41         "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  42
  43 #define CONFIG_MISC_INIT_R      1
  44 /*
  45  * System Clock Setup
  46  */
  47 #define CONFIG_83XX_CLKIN               66000000
  48 #define CONFIG_SYS_CLK_FREQ             66000000
  49 #define CONFIG_83XX_PCICLK              66000000
  50
  51 /*
  52  * Hardware Reset Configuration Word
  53  */
  54 #define CONFIG_SYS_HRCW_LOW (\
  55         HRCWL_CSB_TO_CLKIN_4X1 | \
  56         HRCWL_CORE_TO_CSB_2X1 | \
  57         HRCWL_CE_PLL_VCO_DIV_2 | \
  58         HRCWL_CE_TO_PLL_1X6 )
  59
  60 #define CONFIG_SYS_HRCW_HIGH (\
  61         HRCWH_CORE_ENABLE | \
  62         HRCWH_FROM_0X00000100 | \
  63         HRCWH_BOOTSEQ_DISABLE | \
  64         HRCWH_SW_WATCHDOG_DISABLE | \
  65         HRCWH_ROM_LOC_LOCAL_16BIT | \
  66         HRCWH_BIG_ENDIAN | \
  67         HRCWH_LALE_EARLY | \
  68         HRCWH_LDP_CLEAR )
  69
  70 /*
  71  * System IO Config
  72  */
  73 #define CONFIG_SYS_SICRH                0x00000006
  74 #define CONFIG_SYS_SICRL                0x00000000
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CONFIG_SYS_IMMR         0xE0000000
  80
  81 /*
  82  * Bus Arbitration Configuration Register (ACR)
  83  */
  84 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  85 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  86 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  87 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  88
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  96                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  97
  98 #define CFG_83XX_DDR_USES_CS0
  99
 100 #undef CONFIG_DDR_ECC
 101
 102 /*
 103  * DDRCDR - DDR Control Driver Register
 104  */
 105
 106 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 107
 108 /*
 109  * Manually set up DDR parameters
 110  */
 111 #define CONFIG_DDR_II
 112 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
 113 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 114 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 115                                          CSCONFIG_ROW_BIT_13 | \
 116                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 117
 118 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 119                                          SDRAM_CFG_SREN)
 120 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 121 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 122 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 123                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 124
 125 #define CONFIG_SYS_DDRCDR               0x40000001
 126 #define CONFIG_SYS_DDR_MODE             0x47860452
 127 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 128
 129 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 130                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 131                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 132                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 133                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 134                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 135                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 136                                  (0 << TIMING_CFG0_RWT_SHIFT))
 137
 138 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
 139                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 140                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 141                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 142                                  ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 143                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 144                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 145                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 146
 147 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 148                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 149                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 150                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 151                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 152                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 153                                  (5 << TIMING_CFG2_CPO_SHIFT))
 154
 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 156
 157 /*
 158  * The reserved memory
 159  */
 160 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 161 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 162 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 163 #define CONFIG_SYS_PIGGY_SIZE           128
 164 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 165 #define CONFIG_SYS_PAXE_SIZE            512
 166
 167 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 168 #define CONFIG_SYS_RAMBOOT
 169 #else
 170 #undef  CONFIG_SYS_RAMBOOT
 171 #endif
 172
 173 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 174
 175 /*
 176  * Initial RAM Base Address Setup
 177  */
 178 #define CONFIG_SYS_INIT_RAM_LOCK        1
 179 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 180 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 181 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 183
 184 /*
 185  * Local Bus Configuration & Clock Setup
 186  */
 187 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 188 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 189 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 190
 191 /*
 192  * Init Local Bus Memory Controller:
 193  *
 194  * Bank Bus     Machine PortSz  Size  Device
 195  * ---- ---     ------- ------  -----  ------
 196  *  0   Local   GPCM    16 bit  256MB FLASH
 197  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 198  *  3   Local   GPCM     8 bit  512MB PAXE
 199  *
 200  */
 201 /*
 202  * FLASH on the Local Bus
 203  */
 204 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 205 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 206 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 207 #define CONFIG_SYS_FLASH_PROTECTION     1
 208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 209
 210 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 211 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 212
 213 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 214                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 215                                 BR_V)
 216
 217 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 218                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 219                                 OR_GPCM_SCY_5 | \
 220                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 221
 222 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 223 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 224 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 225
 226 #undef  CONFIG_SYS_FLASH_CHECKSUM
 227
 228 /*
 229  * PRIO1/PIGGY on the local bus CS1
 230  */
 231 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 232 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 233
 234 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 235                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 236                                 BR_V)
 237 #define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 238                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 239                                 OR_GPCM_SCY_2 | \
 240                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 241
 242 /*
 243  * PAXE on the local bus CS3
 244  */
 245 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 246 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 247
 248 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 249                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 250                                 BR_V)
 251 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 252                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 253                                 OR_GPCM_SCY_2 | \
 254                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 255
 256 /*
 257  * Serial Port
 258  */
 259 #define CONFIG_CONS_INDEX       1
 260 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 261 #define CONFIG_SYS_NS16550
 262 #define CONFIG_SYS_NS16550_SERIAL
 263 #define CONFIG_SYS_NS16550_REG_SIZE     1
 264 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 265
 266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 268
 269 /* Pass open firmware flat tree */
 270 #define CONFIG_OF_LIBFDT        1
 271 #define CONFIG_OF_BOARD_SETUP   1
 272 #define CONFIG_OF_STDOUT_VIA_ALIAS
 273
 274 /*
 275  * General PCI
 276  * Addresses are mapped 1-1.
 277  */
 278 #undef CONFIG_PCI               /* No PCI */
 279
 280 #ifndef CONFIG_NET_MULTI
 281 #define CONFIG_NET_MULTI        1
 282 #endif
 283 /*
 284  * QE UEC ethernet configuration
 285  */
 286 #define CONFIG_UEC_ETH
 287 #define CONFIG_ETHPRIME         "FSL UEC0"
 288
 289 #define CONFIG_UEC_ETH1         /* GETH1 */
 290 #define UEC_VERBOSE_DEBUG       1
 291
 292 #ifdef CONFIG_UEC_ETH1
 293 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 294 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 295 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 296 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 297 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 298 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
 299 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 300 #endif
 301
 302 /*
 303  * Environment
 304  */
 305
 306 #ifndef CONFIG_SYS_RAMBOOT
 307 #define CONFIG_ENV_IS_IN_FLASH  1
 308 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 309 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 310 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 311
 312 /* Address and size of Redundant Environment Sector     */
 313 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 314 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 315
 316 #else /* CFG_RAMBOOT */
 317 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 318 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 319 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 320 #define CONFIG_ENV_SIZE         0x2000
 321 #endif /* CFG_RAMBOOT */
 322
 323 /* I2C */
 324 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 325 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 326 #define CONFIG_FSL_I2C
 327 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 328 #define CONFIG_SYS_I2C_SLAVE    0x7F
 329 #define CONFIG_SYS_I2C_OFFSET   0x3000
 330 #define CONFIG_I2C_MULTI_BUS    1
 331 #define CONFIG_I2C_MUX          1
 332
 333 /* EEprom support */
 334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 335
 336 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 337 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 338 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
 339 #define CONFIG_SYS_DTT_MAX_TEMP 70
 340 #define CONFIG_SYS_DTT_LOW_TEMP -30
 341 #define CONFIG_SYS_DTT_HYSTERESIS       3
 342 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 343
 344 #if defined(CONFIG_CMD_NAND)
 345 #define CONFIG_NAND_KMETER1
 346 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 347 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
 348 #endif
 349
 350 #if defined(CONFIG_PCI)
 351 #define CONFIG_CMD_PCI
 352 #endif
 353
 354 #if defined(CFG_RAMBOOT)
 355 #undef CONFIG_CMD_SAVEENV
 356 #undef CONFIG_CMD_LOADS
 357 #endif
 358
 359 /*
 360  * For booting Linux, the board info and command line data
 361  * have to be in the first 8 MB of memory, since this is
 362  * the maximum mapped by the Linux kernel during initialization.
 363  */
 364 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 365
 366 /*
 367  * Core HID Setup
 368  */
 369 #define CONFIG_SYS_HID0_INIT            0x000000000
 370 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 371                                          HID0_ENABLE_INSTRUCTION_CACHE)
 372 #define CONFIG_SYS_HID2                 HID2_HBE
 373
 374 /*
 375  * MMU Setup
 376  */
 377
 378 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 379
 380 /* DDR: cache cacheable */
 381 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 382                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 384 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 385 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 386
 387 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 388 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 389                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 390 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 391 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 392 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 393
 394 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 395 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 396 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 397 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 398                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 399 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 400
 401 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 402 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 403 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 404 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 405                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 406 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 407
 408 /* Stack in dcache: cacheable, no memory coherence */
 409 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 410 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 411 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 412 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 413
 414 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 415 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 416 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 417 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 418                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 419 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 420
 421 #ifdef CONFIG_PCI
 422 /* PCI MEM space: cacheable */
 423 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 424 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 425 #define CFG_DBAT6L      CFG_IBAT6L
 426 #define CFG_DBAT6U      CFG_IBAT6U
 427 /* PCI MMIO space: cache-inhibit and guarded */
 428 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 429                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 430 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 431 #define CFG_DBAT7L      CFG_IBAT7L
 432 #define CFG_DBAT7U      CFG_IBAT7U
 433 #else /* CONFIG_PCI */
 434 #define CONFIG_SYS_IBAT6L       (0)
 435 #define CONFIG_SYS_IBAT6U       (0)
 436 #define CONFIG_SYS_IBAT7L       (0)
 437 #define CONFIG_SYS_IBAT7U       (0)
 438 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 439 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 440 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 441 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 442 #endif /* CONFIG_PCI */
 443
 444 /*
 445  * Internal Definitions
 446  *
 447  * Boot Flags
 448  */
 449 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 450 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 451
 452 #define BOOTFLASH_START F0000000
 453
 454 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 455
 456 /*
 457  * Environment Configuration
 458  */
 459 #define CONFIG_ENV_OVERWRITE
 460 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 461 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 462 #endif
 463
 464 #define CONFIG_EXTRA_ENV_SETTINGS \
 465        CONFIG_KM_DEF_ENV                                                \
 466         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 467         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 468         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 469         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 470         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 471         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 472         "unlock=yes\0"                                                  \
 473         "fdt_addr=F0080000\0"                                           \
 474         "kernel_addr=F00a0000\0"                                        \
 475         "ramdisk_addr=F03a0000\0"                                       \
 476         "ramdisk_addr_r=F10000\0"                                       \
 477         "EEprom_ivm=pca9547:70:9\0"                                     \
 478         "dtt_bus=pca9547:70:a\0"                                        \
 479         "mtdids=nor0=app \0"                                            \
 480         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 481    ""
 482
 483 #if defined(CONFIG_UEC_ETH)
 484 #define CONFIG_HAS_ETH0
 485 #endif
 486
 487 #endif /* __CONFIG_H */