Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[karo-tx-uboot.git] / include / configs / ls1021aqds.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #include <config_cmd_default.h>
11
12 #define CONFIG_LS102XA
13
14 #define CONFIG_SYS_GENERIC_BOARD
15
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21
22 /*
23  * Size of malloc() pool
24  */
25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
29
30 /*
31  * Generic Timer Definitions
32  */
33 #define GENERIC_TIMER_CLK               12500000
34
35 #ifndef __ASSEMBLY__
36 unsigned long get_board_sys_clk(void);
37 unsigned long get_board_ddr_clk(void);
38 #endif
39
40 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
41 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
42
43 #ifndef CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_TEXT_BASE            0x67f80000
45 #endif
46
47 #define CONFIG_NR_DRAM_BANKS            1
48
49 #define CONFIG_DDR_SPD
50 #define SPD_EEPROM_ADDRESS              0x51
51 #define CONFIG_SYS_SPD_BUS_NUM          0
52
53 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
54 #ifndef CONFIG_SYS_FSL_DDR4
55 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
56 #define CONFIG_SYS_DDR_RAW_TIMING
57 #endif
58 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
59 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
60
61 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
63
64 #define CONFIG_DDR_ECC
65 #ifdef CONFIG_DDR_ECC
66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
67 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
68 #endif
69
70 #define CONFIG_SYS_HAS_SERDES
71
72 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
73
74 #if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
75 #define CONFIG_U_QE
76 #endif
77
78 /*
79  * IFC Definitions
80  */
81 #define CONFIG_FSL_IFC
82 #define CONFIG_SYS_FLASH_BASE           0x60000000
83 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
84
85 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
86 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
87                                 CSPR_PORT_SIZE_16 | \
88                                 CSPR_MSEL_NOR | \
89                                 CSPR_V)
90 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
91 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
92                                 + 0x8000000) | \
93                                 CSPR_PORT_SIZE_16 | \
94                                 CSPR_MSEL_NOR | \
95                                 CSPR_V)
96 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
97
98 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
99                                         CSOR_NOR_TRHZ_80)
100 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
101                                         FTIM0_NOR_TEADC(0x5) | \
102                                         FTIM0_NOR_TEAHC(0x5))
103 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
104                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
105                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
106 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
107                                         FTIM2_NOR_TCH(0x4) | \
108                                         FTIM2_NOR_TWPH(0xe) | \
109                                         FTIM2_NOR_TWP(0x1c))
110 #define CONFIG_SYS_NOR_FTIM3            0
111
112 #define CONFIG_FLASH_CFI_DRIVER
113 #define CONFIG_SYS_FLASH_CFI
114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
115 #define CONFIG_SYS_FLASH_QUIET_TEST
116 #define CONFIG_FLASH_SHOW_PROGRESS      45
117 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
118 #define CONFIG_SYS_WRITE_SWAPPED_DATA
119
120 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
121 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
122 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
123 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
124
125 #define CONFIG_SYS_FLASH_EMPTY_INFO
126 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
127                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
128
129 /*
130  * NAND Flash Definitions
131  */
132 #define CONFIG_NAND_FSL_IFC
133
134 #define CONFIG_SYS_NAND_BASE            0x7e800000
135 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
136
137 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
138
139 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
140                                 | CSPR_PORT_SIZE_8      \
141                                 | CSPR_MSEL_NAND        \
142                                 | CSPR_V)
143 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
144 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
145                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
146                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
147                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
148                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
149                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
150                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
151
152 #define CONFIG_SYS_NAND_ONFI_DETECTION
153
154 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
155                                         FTIM0_NAND_TWP(0x18)   | \
156                                         FTIM0_NAND_TWCHT(0x7) | \
157                                         FTIM0_NAND_TWH(0xa))
158 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
159                                         FTIM1_NAND_TWBE(0x39)  | \
160                                         FTIM1_NAND_TRR(0xe)   | \
161                                         FTIM1_NAND_TRP(0x18))
162 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
163                                         FTIM2_NAND_TREH(0xa) | \
164                                         FTIM2_NAND_TWHRE(0x1e))
165 #define CONFIG_SYS_NAND_FTIM3           0x0
166
167 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
168 #define CONFIG_SYS_MAX_NAND_DEVICE      1
169 #define CONFIG_MTD_NAND_VERIFY_WRITE
170 #define CONFIG_CMD_NAND
171
172 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
173
174 /*
175  * QIXIS Definitions
176  */
177 #define CONFIG_FSL_QIXIS
178
179 #ifdef CONFIG_FSL_QIXIS
180 #define QIXIS_BASE                      0x7fb00000
181 #define QIXIS_BASE_PHYS                 QIXIS_BASE
182 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
183 #define QIXIS_LBMAP_SWITCH              6
184 #define QIXIS_LBMAP_MASK                0x0f
185 #define QIXIS_LBMAP_SHIFT               0
186 #define QIXIS_LBMAP_DFLTBANK            0x00
187 #define QIXIS_LBMAP_ALTBANK             0x04
188 #define QIXIS_RST_CTL_RESET             0x44
189 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
190 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
191 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
192
193 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
194 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
195                                         CSPR_PORT_SIZE_8 | \
196                                         CSPR_MSEL_GPCM | \
197                                         CSPR_V)
198 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
199 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
200                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
201                                         CSOR_NOR_TRHZ_80)
202
203 /*
204  * QIXIS Timing parameters for IFC GPCM
205  */
206 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
207                                         FTIM0_GPCM_TEADC(0xe) | \
208                                         FTIM0_GPCM_TEAHC(0xe))
209 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
210                                         FTIM1_GPCM_TRAD(0x1f))
211 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
212                                         FTIM2_GPCM_TCH(0xe) | \
213                                         FTIM2_GPCM_TWP(0xf0))
214 #define CONFIG_SYS_FPGA_FTIM3           0x0
215 #endif
216
217 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
218 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
219 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
220 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
221 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
222 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
223 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
224 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
225 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
226 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
227 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
228 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
229 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
230 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
231 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
232 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
233 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
234 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
235 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
236 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
237 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
238 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
239 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
240 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
241 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
242 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
243 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
244 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
245 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
246 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
247 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
248 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
249
250 /*
251  * Serial Port
252  */
253 #define CONFIG_CONS_INDEX               1
254 #define CONFIG_SYS_NS16550
255 #define CONFIG_SYS_NS16550_SERIAL
256 #define CONFIG_SYS_NS16550_REG_SIZE     1
257 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
258
259 #define CONFIG_BAUDRATE                 115200
260
261 /*
262  * I2C
263  */
264 #define CONFIG_CMD_I2C
265 #define CONFIG_SYS_I2C
266 #define CONFIG_SYS_I2C_MXC
267
268 /*
269  * I2C bus multiplexer
270  */
271 #define I2C_MUX_PCA_ADDR_PRI            0x77
272 #define I2C_MUX_CH_DEFAULT              0x8
273
274 /*
275  * MMC
276  */
277 #define CONFIG_MMC
278 #define CONFIG_CMD_MMC
279 #define CONFIG_FSL_ESDHC
280 #define CONFIG_GENERIC_MMC
281
282 /*
283  * USB
284  */
285 #define CONFIG_HAS_FSL_DR_USB
286
287 #ifdef CONFIG_HAS_FSL_DR_USB
288 #define CONFIG_USB_EHCI
289
290 #ifdef CONFIG_USB_EHCI
291 #define CONFIG_CMD_USB
292 #define CONFIG_USB_STORAGE
293 #define CONFIG_USB_EHCI_FSL
294 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
295 #define CONFIG_CMD_EXT2
296 #endif
297 #endif
298
299 /*
300  * eTSEC
301  */
302 #define CONFIG_TSEC_ENET
303
304 #ifdef CONFIG_TSEC_ENET
305 #define CONFIG_MII
306 #define CONFIG_MII_DEFAULT_TSEC         3
307 #define CONFIG_TSEC1                    1
308 #define CONFIG_TSEC1_NAME               "eTSEC1"
309 #define CONFIG_TSEC2                    1
310 #define CONFIG_TSEC2_NAME               "eTSEC2"
311 #define CONFIG_TSEC3                    1
312 #define CONFIG_TSEC3_NAME               "eTSEC3"
313
314 #define TSEC1_PHY_ADDR                  1
315 #define TSEC2_PHY_ADDR                  2
316 #define TSEC3_PHY_ADDR                  3
317
318 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
319 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
320 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
321
322 #define TSEC1_PHYIDX                    0
323 #define TSEC2_PHYIDX                    0
324 #define TSEC3_PHYIDX                    0
325
326 #define CONFIG_ETHPRIME                 "eTSEC1"
327
328 #define CONFIG_PHY_GIGE
329 #define CONFIG_PHYLIB
330 #define CONFIG_PHY_REALTEK
331
332 #define CONFIG_HAS_ETH0
333 #define CONFIG_HAS_ETH1
334 #define CONFIG_HAS_ETH2
335
336 #define CONFIG_FSL_SGMII_RISER          1
337 #define SGMII_RISER_PHY_OFFSET          0x1b
338
339 #ifdef CONFIG_FSL_SGMII_RISER
340 #define CONFIG_SYS_TBIPA_VALUE          8
341 #endif
342
343 #endif
344 #define CONFIG_CMD_PING
345 #define CONFIG_CMD_DHCP
346 #define CONFIG_CMD_MII
347 #define CONFIG_CMD_NET
348
349 #define CONFIG_CMDLINE_TAG
350 #define CONFIG_CMDLINE_EDITING
351 #define CONFIG_CMD_IMLS
352
353 #define CONFIG_HWCONFIG
354 #define HWCONFIG_BUFFER_SIZE            128
355
356 #define CONFIG_BOOTDELAY                3
357
358 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
359
360 #define CONFIG_EXTRA_ENV_SETTINGS       \
361         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
362         "fdt_high=0xcfffffff\0"         \
363         "initrd_high=0xcfffffff\0"      \
364         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
365
366 /*
367  * Miscellaneous configurable options
368  */
369 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
370 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
371 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
372 #define CONFIG_AUTO_COMPLETE
373 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
374 #define CONFIG_SYS_PBSIZE               \
375                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
376 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
377 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
378
379 #define CONFIG_CMD_ENV_EXISTS
380 #define CONFIG_CMD_GREPENV
381 #define CONFIG_CMD_MEMINFO
382 #define CONFIG_CMD_MEMTEST
383 #define CONFIG_SYS_MEMTEST_START        0x80000000
384 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
385
386 #define CONFIG_SYS_LOAD_ADDR            0x82000000
387
388 /*
389  * Stack sizes
390  * The stack sizes are set up in start.S using the settings below
391  */
392 #define CONFIG_STACKSIZE                (30 * 1024)
393
394 #define CONFIG_SYS_INIT_SP_OFFSET \
395         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
396 #define CONFIG_SYS_INIT_SP_ADDR \
397         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
398
399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
400
401 /*
402  * Environment
403  */
404 #define CONFIG_ENV_OVERWRITE
405
406 #define CONFIG_ENV_IS_IN_FLASH
407 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
408 #define CONFIG_ENV_SIZE                 0x2000
409 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
410
411 #define CONFIG_OF_LIBFDT
412 #define CONFIG_OF_BOARD_SETUP
413 #define CONFIG_CMD_BOOTZ
414
415 #define CONFIG_MISC_INIT_R
416
417 /* Hash command with SHA acceleration supported in hardware */
418 #define CONFIG_CMD_HASH
419 #define CONFIG_SHA_HW_ACCEL
420
421 #ifdef CONFIG_SECURE_BOOT
422 #define CONFIG_CMD_BLOB
423 #endif
424
425 #endif