Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
[karo-tx-uboot.git] / include / configs / ls1021aqds.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #include <config_cmd_default.h>
11
12 #define CONFIG_LS102XA
13
14 #define CONFIG_SYS_GENERIC_BOARD
15
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21
22 /*
23  * Size of malloc() pool
24  */
25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
29
30 /*
31  * Generic Timer Definitions
32  */
33 #define GENERIC_TIMER_CLK               12500000
34
35 #ifndef __ASSEMBLY__
36 unsigned long get_board_sys_clk(void);
37 unsigned long get_board_ddr_clk(void);
38 #endif
39
40 #ifdef CONFIG_QSPI_BOOT
41 #define CONFIG_SYS_CLK_FREQ             100000000
42 #define CONFIG_DDR_CLK_FREQ             100000000
43 #define CONFIG_QIXIS_I2C_ACCESS
44 #else
45 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
46 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
47 #endif
48
49 #ifdef CONFIG_RAMBOOT_PBL
50 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
51 #endif
52
53 #ifdef CONFIG_SD_BOOT
54 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
55 #define CONFIG_SPL_FRAMEWORK
56 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
57 #define CONFIG_SPL_LIBCOMMON_SUPPORT
58 #define CONFIG_SPL_LIBGENERIC_SUPPORT
59 #define CONFIG_SPL_ENV_SUPPORT
60 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
61 #define CONFIG_SPL_I2C_SUPPORT
62 #define CONFIG_SPL_WATCHDOG_SUPPORT
63 #define CONFIG_SPL_SERIAL_SUPPORT
64 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
65 #define CONFIG_SPL_MMC_SUPPORT
66 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
67 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
68
69 #define CONFIG_SPL_TEXT_BASE            0x10000000
70 #define CONFIG_SPL_MAX_SIZE             0x1a000
71 #define CONFIG_SPL_STACK                0x1001d000
72 #define CONFIG_SPL_PAD_TO               0x1c000
73 #define CONFIG_SYS_TEXT_BASE            0x82000000
74
75 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
76 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
77 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
78 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
79 #define CONFIG_SYS_MONITOR_LEN          0x80000
80 #endif
81
82 #ifdef CONFIG_QSPI_BOOT
83 #define CONFIG_SYS_TEXT_BASE            0x40010000
84 #define CONFIG_SYS_NO_FLASH
85 #endif
86
87 #ifdef CONFIG_NAND_BOOT
88 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
89 #define CONFIG_SPL_FRAMEWORK
90 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
91 #define CONFIG_SPL_LIBCOMMON_SUPPORT
92 #define CONFIG_SPL_LIBGENERIC_SUPPORT
93 #define CONFIG_SPL_ENV_SUPPORT
94 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
95 #define CONFIG_SPL_I2C_SUPPORT
96 #define CONFIG_SPL_WATCHDOG_SUPPORT
97 #define CONFIG_SPL_SERIAL_SUPPORT
98 #define CONFIG_SPL_NAND_SUPPORT
99 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
100
101 #define CONFIG_SPL_TEXT_BASE            0x10000000
102 #define CONFIG_SPL_MAX_SIZE             0x1a000
103 #define CONFIG_SPL_STACK                0x1001d000
104 #define CONFIG_SPL_PAD_TO               0x1c000
105 #define CONFIG_SYS_TEXT_BASE            0x82000000
106
107 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
108 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
109 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
110 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
111 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
112
113 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
114 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
115 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
116 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
117 #define CONFIG_SYS_MONITOR_LEN          0x80000
118 #endif
119
120 #ifndef CONFIG_SYS_TEXT_BASE
121 #define CONFIG_SYS_TEXT_BASE            0x67f80000
122 #endif
123
124 #define CONFIG_NR_DRAM_BANKS            1
125
126 #define CONFIG_DDR_SPD
127 #define SPD_EEPROM_ADDRESS              0x51
128 #define CONFIG_SYS_SPD_BUS_NUM          0
129
130 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
131 #ifndef CONFIG_SYS_FSL_DDR4
132 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
133 #define CONFIG_SYS_DDR_RAW_TIMING
134 #endif
135 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
136 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
137
138 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
139 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
140
141 #define CONFIG_DDR_ECC
142 #ifdef CONFIG_DDR_ECC
143 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
144 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
145 #endif
146
147 #define CONFIG_SYS_HAS_SERDES
148
149 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
150
151 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
152         !defined(CONFIG_QSPI_BOOT)
153 #define CONFIG_U_QE
154 #endif
155
156 /*
157  * IFC Definitions
158  */
159 #ifndef CONFIG_QSPI_BOOT
160 #define CONFIG_FSL_IFC
161 #define CONFIG_SYS_FLASH_BASE           0x60000000
162 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
163
164 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
165 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
166                                 CSPR_PORT_SIZE_16 | \
167                                 CSPR_MSEL_NOR | \
168                                 CSPR_V)
169 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
170 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
171                                 + 0x8000000) | \
172                                 CSPR_PORT_SIZE_16 | \
173                                 CSPR_MSEL_NOR | \
174                                 CSPR_V)
175 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
176
177 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
178                                         CSOR_NOR_TRHZ_80)
179 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
180                                         FTIM0_NOR_TEADC(0x5) | \
181                                         FTIM0_NOR_TEAHC(0x5))
182 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
183                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
184                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
185 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
186                                         FTIM2_NOR_TCH(0x4) | \
187                                         FTIM2_NOR_TWPH(0xe) | \
188                                         FTIM2_NOR_TWP(0x1c))
189 #define CONFIG_SYS_NOR_FTIM3            0
190
191 #define CONFIG_FLASH_CFI_DRIVER
192 #define CONFIG_SYS_FLASH_CFI
193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
194 #define CONFIG_SYS_FLASH_QUIET_TEST
195 #define CONFIG_FLASH_SHOW_PROGRESS      45
196 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
197 #define CONFIG_SYS_WRITE_SWAPPED_DATA
198
199 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
200 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
201 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
203
204 #define CONFIG_SYS_FLASH_EMPTY_INFO
205 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
206                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
207
208 /*
209  * NAND Flash Definitions
210  */
211 #define CONFIG_NAND_FSL_IFC
212
213 #define CONFIG_SYS_NAND_BASE            0x7e800000
214 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
215
216 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
217
218 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
219                                 | CSPR_PORT_SIZE_8      \
220                                 | CSPR_MSEL_NAND        \
221                                 | CSPR_V)
222 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
223 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
224                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
225                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
226                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
227                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
228                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
229                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
230
231 #define CONFIG_SYS_NAND_ONFI_DETECTION
232
233 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
234                                         FTIM0_NAND_TWP(0x18)   | \
235                                         FTIM0_NAND_TWCHT(0x7) | \
236                                         FTIM0_NAND_TWH(0xa))
237 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
238                                         FTIM1_NAND_TWBE(0x39)  | \
239                                         FTIM1_NAND_TRR(0xe)   | \
240                                         FTIM1_NAND_TRP(0x18))
241 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
242                                         FTIM2_NAND_TREH(0xa) | \
243                                         FTIM2_NAND_TWHRE(0x1e))
244 #define CONFIG_SYS_NAND_FTIM3           0x0
245
246 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
247 #define CONFIG_SYS_MAX_NAND_DEVICE      1
248 #define CONFIG_MTD_NAND_VERIFY_WRITE
249 #define CONFIG_CMD_NAND
250
251 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
252 #endif
253
254 /*
255  * QIXIS Definitions
256  */
257 #define CONFIG_FSL_QIXIS
258
259 #ifdef CONFIG_FSL_QIXIS
260 #define QIXIS_BASE                      0x7fb00000
261 #define QIXIS_BASE_PHYS                 QIXIS_BASE
262 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
263 #define QIXIS_LBMAP_SWITCH              6
264 #define QIXIS_LBMAP_MASK                0x0f
265 #define QIXIS_LBMAP_SHIFT               0
266 #define QIXIS_LBMAP_DFLTBANK            0x00
267 #define QIXIS_LBMAP_ALTBANK             0x04
268 #define QIXIS_RST_CTL_RESET             0x44
269 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
270 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
271 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
272
273 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
274 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
275                                         CSPR_PORT_SIZE_8 | \
276                                         CSPR_MSEL_GPCM | \
277                                         CSPR_V)
278 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
279 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
280                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
281                                         CSOR_NOR_TRHZ_80)
282
283 /*
284  * QIXIS Timing parameters for IFC GPCM
285  */
286 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
287                                         FTIM0_GPCM_TEADC(0xe) | \
288                                         FTIM0_GPCM_TEAHC(0xe))
289 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
290                                         FTIM1_GPCM_TRAD(0x1f))
291 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
292                                         FTIM2_GPCM_TCH(0xe) | \
293                                         FTIM2_GPCM_TWP(0xf0))
294 #define CONFIG_SYS_FPGA_FTIM3           0x0
295 #endif
296
297 #if defined(CONFIG_NAND_BOOT)
298 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
299 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
300 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
301 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
302 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
303 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
304 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
305 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
306 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
307 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
308 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
309 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
310 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
311 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
312 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
313 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
314 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
315 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
316 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
317 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
318 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
319 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
320 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
321 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
322 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
323 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
324 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
325 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
326 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
327 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
328 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
329 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
330 #else
331 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
332 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
333 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
334 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
335 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
336 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
337 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
338 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
339 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
340 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
341 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
342 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
343 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
344 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
345 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
346 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
347 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
348 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
349 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
350 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
351 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
352 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
353 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
354 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
355 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
356 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
357 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
358 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
359 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
360 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
361 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
362 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
363 #endif
364
365 /*
366  * Serial Port
367  */
368 #define CONFIG_CONS_INDEX               1
369 #define CONFIG_SYS_NS16550
370 #define CONFIG_SYS_NS16550_SERIAL
371 #define CONFIG_SYS_NS16550_REG_SIZE     1
372 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
373
374 #define CONFIG_BAUDRATE                 115200
375
376 /*
377  * I2C
378  */
379 #define CONFIG_CMD_I2C
380 #define CONFIG_SYS_I2C
381 #define CONFIG_SYS_I2C_MXC
382
383 /*
384  * I2C bus multiplexer
385  */
386 #define I2C_MUX_PCA_ADDR_PRI            0x77
387 #define I2C_MUX_CH_DEFAULT              0x8
388
389 /*
390  * MMC
391  */
392 #define CONFIG_MMC
393 #define CONFIG_CMD_MMC
394 #define CONFIG_FSL_ESDHC
395 #define CONFIG_GENERIC_MMC
396
397 #define CONFIG_CMD_FAT
398 #define CONFIG_DOS_PARTITION
399
400 /* QSPI */
401 #ifdef CONFIG_QSPI_BOOT
402 #define CONFIG_FSL_QSPI
403 #define QSPI0_AMBA_BASE                 0x40000000
404 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
405 #define FSL_QSPI_FLASH_NUM              2
406
407 #define CONFIG_CMD_SF
408 #define CONFIG_SPI_FLASH
409 #define CONFIG_SPI_FLASH_SPANSION
410 #endif
411
412 /*
413  * USB
414  */
415 #define CONFIG_HAS_FSL_DR_USB
416
417 #ifdef CONFIG_HAS_FSL_DR_USB
418 #define CONFIG_USB_EHCI
419
420 #ifdef CONFIG_USB_EHCI
421 #define CONFIG_CMD_USB
422 #define CONFIG_USB_STORAGE
423 #define CONFIG_USB_EHCI_FSL
424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
425 #define CONFIG_CMD_EXT2
426 #endif
427 #endif
428
429 /*
430  * eTSEC
431  */
432 #define CONFIG_TSEC_ENET
433
434 #ifdef CONFIG_TSEC_ENET
435 #define CONFIG_MII
436 #define CONFIG_MII_DEFAULT_TSEC         3
437 #define CONFIG_TSEC1                    1
438 #define CONFIG_TSEC1_NAME               "eTSEC1"
439 #define CONFIG_TSEC2                    1
440 #define CONFIG_TSEC2_NAME               "eTSEC2"
441 #define CONFIG_TSEC3                    1
442 #define CONFIG_TSEC3_NAME               "eTSEC3"
443
444 #define TSEC1_PHY_ADDR                  1
445 #define TSEC2_PHY_ADDR                  2
446 #define TSEC3_PHY_ADDR                  3
447
448 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
449 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
450 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
451
452 #define TSEC1_PHYIDX                    0
453 #define TSEC2_PHYIDX                    0
454 #define TSEC3_PHYIDX                    0
455
456 #define CONFIG_ETHPRIME                 "eTSEC1"
457
458 #define CONFIG_PHY_GIGE
459 #define CONFIG_PHYLIB
460 #define CONFIG_PHY_REALTEK
461
462 #define CONFIG_HAS_ETH0
463 #define CONFIG_HAS_ETH1
464 #define CONFIG_HAS_ETH2
465
466 #define CONFIG_FSL_SGMII_RISER          1
467 #define SGMII_RISER_PHY_OFFSET          0x1b
468
469 #ifdef CONFIG_FSL_SGMII_RISER
470 #define CONFIG_SYS_TBIPA_VALUE          8
471 #endif
472
473 #endif
474
475 /* PCIe */
476 #define CONFIG_PCI              /* Enable PCI/PCIE */
477 #define CONFIG_PCIE1            /* PCIE controler 1 */
478 #define CONFIG_PCIE2            /* PCIE controler 2 */
479 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
480 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
481
482 #define CONFIG_CMD_PING
483 #define CONFIG_CMD_DHCP
484 #define CONFIG_CMD_MII
485 #define CONFIG_CMD_NET
486
487 #define CONFIG_CMDLINE_TAG
488 #define CONFIG_CMDLINE_EDITING
489
490 #ifdef CONFIG_QSPI_BOOT
491 #undef CONFIG_CMD_IMLS
492 #else
493 #define CONFIG_CMD_IMLS
494 #endif
495
496 #define CONFIG_ARMV7_NONSEC
497 #define CONFIG_ARMV7_VIRT
498 #define CONFIG_PEN_ADDR_BIG_ENDIAN
499 #define CONFIG_LS102XA_NS_ACCESS
500 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
501 #define CONFIG_TIMER_CLK_FREQ           12500000
502 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
503
504 #define CONFIG_HWCONFIG
505 #define HWCONFIG_BUFFER_SIZE            128
506
507 #define CONFIG_BOOTDELAY                3
508
509 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
510
511 #define CONFIG_EXTRA_ENV_SETTINGS       \
512         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
513         "fdt_high=0xcfffffff\0"         \
514         "initrd_high=0xcfffffff\0"      \
515         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
516
517 /*
518  * Miscellaneous configurable options
519  */
520 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
521 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
522 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
523 #define CONFIG_AUTO_COMPLETE
524 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
525 #define CONFIG_SYS_PBSIZE               \
526                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
527 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
528 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
529
530 #define CONFIG_CMD_ENV_EXISTS
531 #define CONFIG_CMD_GREPENV
532 #define CONFIG_CMD_MEMINFO
533 #define CONFIG_CMD_MEMTEST
534 #define CONFIG_SYS_MEMTEST_START        0x80000000
535 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
536
537 #define CONFIG_SYS_LOAD_ADDR            0x82000000
538
539 #define CONFIG_LS102XA_STREAM_ID
540
541 /*
542  * Stack sizes
543  * The stack sizes are set up in start.S using the settings below
544  */
545 #define CONFIG_STACKSIZE                (30 * 1024)
546
547 #define CONFIG_SYS_INIT_SP_OFFSET \
548         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
549 #define CONFIG_SYS_INIT_SP_ADDR \
550         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
551
552 #ifdef CONFIG_SPL_BUILD
553 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
554 #else
555 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
556 #endif
557
558 /*
559  * Environment
560  */
561 #define CONFIG_ENV_OVERWRITE
562
563 #if defined(CONFIG_SD_BOOT)
564 #define CONFIG_ENV_OFFSET               0x100000
565 #define CONFIG_ENV_IS_IN_MMC
566 #define CONFIG_SYS_MMC_ENV_DEV          0
567 #define CONFIG_ENV_SIZE                 0x2000
568 #elif defined(CONFIG_QSPI_BOOT)
569 #define CONFIG_ENV_IS_IN_SPI_FLASH
570 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
571 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
572 #define CONFIG_ENV_SECT_SIZE            0x10000
573 #elif defined(CONFIG_NAND_BOOT)
574 #define CONFIG_ENV_IS_IN_NAND
575 #define CONFIG_ENV_SIZE                 0x2000
576 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
577 #else
578 #define CONFIG_ENV_IS_IN_FLASH
579 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
580 #define CONFIG_ENV_SIZE                 0x2000
581 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
582 #endif
583
584 #define CONFIG_OF_LIBFDT
585 #define CONFIG_OF_BOARD_SETUP
586 #define CONFIG_CMD_BOOTZ
587
588 #define CONFIG_MISC_INIT_R
589
590 /* Hash command with SHA acceleration supported in hardware */
591 #define CONFIG_CMD_HASH
592 #define CONFIG_SHA_HW_ACCEL
593
594 #ifdef CONFIG_SECURE_BOOT
595 #define CONFIG_CMD_BLOB
596 #endif
597
598 #endif