include/configs/ls2085a_emu.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_EMU_H
   8 #define __LS2_EMU_H
   9
  10 #include "ls2085a_common.h"
  11
  12 #define CONFIG_IDENT_STRING             " LS2085A-EMU"
  13 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-EMU"
  14
  15 #define CONFIG_SYS_CLK_FREQ     100000000
  16 #define CONFIG_DDR_CLK_FREQ     133333333
  17
  18 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  19 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  20
  21 #define CONFIG_DDR_SPD
  22 #define CONFIG_SYS_FSL_DDR_EMU          /* Support emulator */
  23 #define SPD_EEPROM_ADDRESS1     0x51
  24 #define SPD_EEPROM_ADDRESS2     0x52
  25 #define SPD_EEPROM_ADDRESS3     0x53
  26 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  27 #define CONFIG_SYS_SPD_BUS_NUM  1       /* SPD on I2C bus 1 */
  28 #define CONFIG_DIMM_SLOTS_PER_CTLR              1
  29 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  30 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  31
  32 #define CONFIG_FSL_DDR_SYNC_REFRESH
  33
  34 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  35 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
  36 /*
  37  * NOR Flash Timing Params
  38  */
  39 #define CONFIG_SYS_NOR0_CSPR                                    \
  40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  45         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  50 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  51                                 FTIM0_NOR_TEADC(0x1) | \
  52                                 FTIM0_NOR_TEAHC(0x1))
  53 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  54                                 FTIM1_NOR_TRAD_NOR(0x1))
  55 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  56                                 FTIM2_NOR_TCH(0x0) | \
  57                                 FTIM2_NOR_TWP(0x1))
  58 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  59 #define CONFIG_SYS_IFC_CCR      0x01000000
  60
  61 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  62 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
  63 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
  64 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
  65 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
  66 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
  67 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
  68 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
  69 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
  70
  71 /* Debug Server firmware */
  72 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  73 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
  74
  75 /*
  76  * This trick allows users to load MC images into DDR directly without
  77  * copying from NOR flash. It dramatically improves speed.
  78  */
  79 #define CONFIG_SYS_LS_MC_FW_IN_DDR
  80 #define CONFIG_SYS_LS_MC_DPL_IN_DDR
  81 #define CONFIG_SYS_LS_MC_DPC_IN_DDR
  82
  83 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
  84
  85 /* Store environment at top of flash */
  86 #define CONFIG_ENV_IS_NOWHERE           1
  87 #define CONFIG_ENV_SIZE                 0x1000
  88
  89 #endif /* __LS2_EMU_H */