include/configs/mpc8308_p1m.h

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   4  *
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1 /* E300 family */
  32 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  33 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  34 #define CONFIG_MPC8308_P1M      1 /* mpc8308_p1m board specific */
  35
  36 #ifndef CONFIG_SYS_TEXT_BASE
  37 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  38 #endif
  39
  40 /*
  41  * On-board devices
  42  *
  43  * TSECs
  44  */
  45 #define CONFIG_TSEC1
  46 #define CONFIG_TSEC2
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  52 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  53
  54 /*
  55  * Hardware Reset Configuration Word
  56  * if CLKIN is 66.66MHz, then
  57  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  58  * We choose the A type silicon as default, so the core is 400Mhz.
  59  */
  60 #define CONFIG_SYS_HRCW_LOW (\
  61         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  62         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  63         HRCWL_SVCOD_DIV_2 |\
  64         HRCWL_CSB_TO_CLKIN_4X1 |\
  65         HRCWL_CORE_TO_CSB_3X1)
  66 /*
  67  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  68  * in 8308's HRCWH according to the manual, but original Freescale's
  69  * code has them and I've expirienced some problems using the board
  70  * with BDI3000 attached when I've tried to set these bits to zero
  71  * (UART doesn't work after the 'reset run' command).
  72  */
  73 #define CONFIG_SYS_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_CORE_ENABLE |\
  77         HRCWH_FROM_0X00000100 |\
  78         HRCWH_BOOTSEQ_DISABLE |\
  79         HRCWH_SW_WATCHDOG_DISABLE |\
  80         HRCWH_ROM_LOC_LOCAL_16BIT |\
  81         HRCWH_RL_EXT_LEGACY |\
  82         HRCWH_TSEC1M_IN_MII |\
  83         HRCWH_TSEC2M_IN_MII |\
  84         HRCWH_BIG_ENDIAN)
  85
  86 /*
  87  * System IO Config
  88  */
  89 #define CONFIG_SYS_SICRH (\
  90         SICRH_ESDHC_A_GPIO |\
  91         SICRH_ESDHC_B_GPIO |\
  92         SICRH_ESDHC_C_GTM |\
  93         SICRH_GPIO_A_TSEC2 |\
  94         SICRH_GPIO_B_TSEC2_TX_CLK |\
  95         SICRH_IEEE1588_A_GPIO |\
  96         SICRH_USB |\
  97         SICRH_GTM_GPIO |\
  98         SICRH_IEEE1588_B_GPIO |\
  99         SICRH_ETSEC2_CRS |\
 100         SICRH_GPIOSEL_1 |\
 101         SICRH_TMROBI_V3P3 |\
 102         SICRH_TSOBI1_V3P3 |\
 103         SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
 104 #define CONFIG_SYS_SICRL (\
 105         SICRL_SPI_PF0 |\
 106         SICRL_UART_PF0 |\
 107         SICRL_IRQ_PF0 |\
 108         SICRL_I2C2_PF0 |\
 109         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
 110
 111 #define CONFIG_SYS_GPIO1_PRELIM
 112 /* GPIO Default input/output settings */
 113 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
 114 /*
 115  * Default GPIO values:
 116  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
 117  */
 118 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
 119
 120 /*
 121  * IMMR new address
 122  */
 123 #define CONFIG_SYS_IMMR         0xE0000000
 124
 125 /*
 126  * SERDES
 127  */
 128 #define CONFIG_FSL_SERDES
 129 #define CONFIG_FSL_SERDES1      0xe3000
 130
 131 /*
 132  * Arbiter Setup
 133  */
 134 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 135 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 136 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 137
 138 /*
 139  * DDR Setup
 140  */
 141 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 142 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 143 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 144 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 145 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 146                                 | DDRCDR_PZ_LOZ \
 147                                 | DDRCDR_NZ_LOZ \
 148                                 | DDRCDR_ODT \
 149                                 | DDRCDR_Q_DRN)
 150                                 /* 0x7b880001 */
 151 /*
 152  * Manually set up DDR parameters
 153  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 154  */
 155
 156 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 157
 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 159 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 160                                 | 0x00010000  /* ODT_WR to CSn */ \
 161                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 162                                 /* 0x80010102 */
 163 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 164 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 165                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 166                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 167                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 168                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 169                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 170                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 171                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 172                                 /* 0x00220802 */
 173 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 174                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 175                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 176                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 177                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 178                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 179                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 180                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 181                                 /* 0x27256222 */
 182 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 183                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 184                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 185                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 186                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 187                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 188                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 189                                 /* 0x121048c5 */
 190 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 191                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 192                                 /* 0x03600100 */
 193 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 194                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 195                                 | SDRAM_CFG_32_BE)
 196                                 /* 0x43080000 */
 197
 198 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 199 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 200                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 201                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 202 #define CONFIG_SYS_DDR_MODE2            0x00000000
 203
 204 /*
 205  * Memory test
 206  */
 207 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 208 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 209
 210 /*
 211  * The reserved memory
 212  */
 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 214
 215 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 216 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 217
 218 /*
 219  * Initial RAM Base Address Setup
 220  */
 221 #define CONFIG_SYS_INIT_RAM_LOCK        1
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 223 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 224 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 225         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 226
 227 /*
 228  * Local Bus Configuration & Clock Setup
 229  */
 230 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 231 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 232 #define CONFIG_SYS_LBC_LBCR             0x00040000
 233
 234 /*
 235  * FLASH on the Local Bus
 236  */
 237 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 238 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 239 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 240
 241 #define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 242 #define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 243 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 244
 245 /* Window base at flash base */
 246 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 247 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 248
 249 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  /* Flash Base addr */ \
 250                                 | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
 251                                 | BR_V)                 /* valid */
 252 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 253                                 | OR_UPM_XAM \
 254                                 | OR_GPCM_CSNT \
 255                                 | OR_GPCM_ACS_DIV2 \
 256                                 | OR_GPCM_XACS \
 257                                 | OR_GPCM_SCY_4 \
 258                                 | OR_GPCM_TRLX \
 259                                 | OR_GPCM_EHTR \
 260                                 | OR_GPCM_EAD)
 261
 262 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 263 #define CONFIG_SYS_MAX_FLASH_SECT       512
 264
 265 /* Flash Erase Timeout (ms) */
 266 #define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 267 /* Flash Write Timeout (ms) */
 268 #define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 269
 270 /*
 271  * SJA1000 CAN controller on Local Bus
 272  */
 273 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 274 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_SJA1000_BASE \
 275                                 | (1 << BR_PS_SHIFT)    /* 8 bit port */ \
 276                                 | BR_V)                 /* valid */
 277 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000             /* length 32K */ \
 278                                 | OR_GPCM_SCY_5 \
 279                                 | OR_GPCM_EHTR)
 280                                 /* 0xFFFF8052 */
 281
 282 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_SJA1000_BASE
 283 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 284
 285 /*
 286  * CPLD on Local Bus
 287  */
 288 #define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 289 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_CPLD_BASE \
 290                                 | (1 << BR_PS_SHIFT)    /* 8 bit port */ \
 291                                 | BR_V)                 /* valid */
 292 #define CONFIG_SYS_OR2_PRELIM   (0xFFFF8000             /* length 32K */ \
 293                                 | OR_GPCM_SCY_4 \
 294                                 | OR_GPCM_EHTR)
 295                                 /* 0xFFFF8042 */
 296
 297 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_CPLD_BASE
 298 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 299
 300 /*
 301  * Serial Port
 302  */
 303 #define CONFIG_CONS_INDEX       1
 304 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 305 #define CONFIG_SYS_NS16550
 306 #define CONFIG_SYS_NS16550_SERIAL
 307 #define CONFIG_SYS_NS16550_REG_SIZE     1
 308 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 309
 310 #define CONFIG_SYS_BAUDRATE_TABLE  \
 311         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 312
 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 315
 316 /* Use the HUSH parser */
 317 #define CONFIG_SYS_HUSH_PARSER
 318 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 319
 320 /* Pass open firmware flat tree */
 321 #define CONFIG_OF_LIBFDT        1
 322 #define CONFIG_OF_BOARD_SETUP   1
 323 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 324
 325 /* I2C */
 326 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 327 #define CONFIG_FSL_I2C
 328 #define CONFIG_I2C_MULTI_BUS
 329 #define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
 330 #define CONFIG_SYS_I2C_SLAVE    0x7F
 331 #define CONFIG_SYS_I2C_OFFSET   0x3000
 332 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 333
 334 /*
 335  * General PCI
 336  * Addresses are mapped 1-1.
 337  */
 338 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 339 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 340 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 341 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 342 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 343 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 344 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 345 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 346 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 347
 348 /* enable PCIE clock */
 349 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 350
 351 #define CONFIG_PCI
 352 #define CONFIG_PCIE
 353
 354 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 355
 356 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 357 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 358
 359 /*
 360  * TSEC
 361  */
 362 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 363 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 364 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 365 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 366 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 367
 368 /*
 369  * TSEC ethernet configuration
 370  */
 371 #define CONFIG_MII              1 /* MII PHY management */
 372 #define CONFIG_TSEC1_NAME       "eTSEC0"
 373 #define CONFIG_TSEC2_NAME       "eTSEC1"
 374 #define TSEC1_PHY_ADDR          1
 375 #define TSEC2_PHY_ADDR          2
 376 #define TSEC1_PHYIDX            0
 377 #define TSEC2_PHYIDX            0
 378 #define TSEC1_FLAGS             0
 379 #define TSEC2_FLAGS             0
 380
 381 /* Options are: eTSEC[0-1] */
 382 #define CONFIG_ETHPRIME         "eTSEC0"
 383
 384 /*
 385  * Environment
 386  */
 387 #define CONFIG_ENV_IS_IN_FLASH  1
 388 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 389                                  CONFIG_SYS_MONITOR_LEN)
 390 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 391 #define CONFIG_ENV_SIZE         0x2000
 392 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 393 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 394
 395 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 397
 398 /*
 399  * BOOTP options
 400  */
 401 #define CONFIG_BOOTP_BOOTFILESIZE
 402 #define CONFIG_BOOTP_BOOTPATH
 403 #define CONFIG_BOOTP_GATEWAY
 404 #define CONFIG_BOOTP_HOSTNAME
 405
 406 /*
 407  * Command line configuration.
 408  */
 409 #include <config_cmd_default.h>
 410
 411 #define CONFIG_CMD_DHCP
 412 #define CONFIG_CMD_I2C
 413 #define CONFIG_CMD_MII
 414 #define CONFIG_CMD_NET
 415 #define CONFIG_CMD_PCI
 416 #define CONFIG_CMD_PING
 417
 418 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 419
 420 /*
 421  * Miscellaneous configurable options
 422  */
 423 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 424 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 425 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 426
 427 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 428
 429 /* Print Buffer Size */
 430 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 431 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 432 /* Boot Argument Buffer Size */
 433 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 434 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 435
 436 /*
 437  * For booting Linux, the board info and command line data
 438  * have to be in the first 8 MB of memory, since this is
 439  * the maximum mapped by the Linux kernel during initialization.
 440  */
 441 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 442
 443 /*
 444  * Core HID Setup
 445  */
 446 #define CONFIG_SYS_HID0_INIT    0x000000000
 447 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 448                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 449                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 450 #define CONFIG_SYS_HID2         HID2_HBE
 451
 452 /*
 453  * MMU Setup
 454  */
 455
 456 /* DDR: cache cacheable */
 457 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 458                                         BATL_MEMCOHERENCE)
 459 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 460                                         BATU_VS | BATU_VP)
 461 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 462 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 463
 464 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 465 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 466                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 467 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 468                                         BATU_VP)
 469 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 470 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 471
 472 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 473 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 474                                         BATL_MEMCOHERENCE)
 475 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 476                                         BATU_VS | BATU_VP)
 477 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 478                                         BATL_CACHEINHIBIT | \
 479                                         BATL_GUARDEDSTORAGE)
 480 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 481
 482 /* Stack in dcache: cacheable, no memory coherence */
 483 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 484 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 485                                         BATU_VS | BATU_VP)
 486 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 487 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 488
 489 /*
 490  * Environment Configuration
 491  */
 492
 493 #define CONFIG_ENV_OVERWRITE
 494
 495 #if defined(CONFIG_TSEC_ENET)
 496 #define CONFIG_HAS_ETH0
 497 #define CONFIG_HAS_ETH1
 498 #endif
 499
 500 #define CONFIG_BAUDRATE 115200
 501
 502 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 503
 504 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 505
 506 #define xstr(s) str(s)
 507 #define str(s)  #s
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 510         "netdev=eth0\0"                                                 \
 511         "consoledev=ttyS0\0"                                            \
 512         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 513                 "nfsroot=${serverip}:${rootpath}\0"                     \
 514         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 515         "addip=setenv bootargs ${bootargs} "                            \
 516                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 517                 ":${hostname}:${netdev}:off panic=1\0"                  \
 518         "addtty=setenv bootargs ${bootargs}"                            \
 519                 " console=${consoledev},${baudrate}\0"                  \
 520         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 521         "addmisc=setenv bootargs ${bootargs}\0"                         \
 522         "kernel_addr=FC0A0000\0"                                        \
 523         "fdt_addr=FC2A0000\0"                                           \
 524         "ramdisk_addr=FC2C0000\0"                                       \
 525         "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 526         "kernel_addr_r=1000000\0"                                       \
 527         "fdt_addr_r=C00000\0"                                           \
 528         "hostname=mpc8308_p1m\0"                                        \
 529         "bootfile=mpc8308_p1m/uImage\0"                                 \
 530         "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 531         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 532         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 533                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 534         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 535                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 536         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 537                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 538                 "run nfsargs addip addtty addmtd addmisc;"              \
 539                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 540         "bootcmd=run flash_self\0"                                      \
 541         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 542         "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)             \
 543                 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)      \
 544                 " +${filesize};cp.b ${fileaddr} "                       \
 545                 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"          \
 546         "upd=run load update\0"                                         \
 547
 548 #endif  /* __CONFIG_H */