2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX35 3stack Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/mx35.h>
28 /* for mfg firmware */
30 #define CONFIG_BOOTARGS "console=ttymxc0,115200 rdinit=/linuxrc"
31 #define CONFIG_ENV_IS_NOWHERE
32 /* High Level Configuration Options */
33 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35 #define CONFIG_MX35 1 /* in a mx31 */
36 #define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
38 #define CONFIG_ARCH_CPU_INIT
39 #define CONFIG_ARCH_MMU
41 #define CONFIG_DISPLAY_CPUINFO
42 #define CONFIG_DISPLAY_BOARDINFO
44 #define CONFIG_SYS_64BIT_VSPRINTF
46 #define BOARD_LATE_INIT
48 * Disabled for now due to build problems under Debian
49 * and a significant increase
50 * in the final file size: 144260 vs. 109536 Bytes.
53 #define CONFIG_OF_LIBFDT 1
55 #define CONFIG_FIT_VERBOSE 1
58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59 #define CONFIG_REVISION_TAG 1
60 #define CONFIG_SETUP_MEMORY_TAGS 1
61 #define CONFIG_INITRD_TAG 1
64 * Size of malloc() pool
66 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
67 /* size in bytes reserved for initial data */
68 #define CONFIG_SYS_GBL_DATA_SIZE 128
73 #define CONFIG_HARD_I2C 1
74 #define CONFIG_I2C_MXC 1
75 #define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
76 #define CONFIG_SYS_I2C_SPEED 100000
77 #define CONFIG_SYS_I2C_SLAVE 0xfe
79 #define CONFIG_MX35_UART UART1_BASE_ADDR
81 /* allow to overwrite serial and ethaddr */
82 #define CONFIG_ENV_OVERWRITE
83 #define CONFIG_CONS_INDEX 1
84 #define CONFIG_BAUDRATE 115200
85 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
87 /***********************************************************
89 ***********************************************************/
91 #include <config_cmd_default.h>
93 #define CONFIG_CMD_PING
94 #define CONFIG_CMD_DHCP
95 #define CONFIG_BOOTP_SUBNETMASK
96 #define CONFIG_BOOTP_GATEWAY
97 #define CONFIG_BOOTP_DNS
98 /*#define CONFIG_CMD_SPI*/
99 /*#define CONFIG_CMD_DATE*/
100 /*#define CONFIG_CMD_NAND*/
101 #define CONFIG_CMD_ENV
102 /* #define CONFIG_CMD_MMC */
104 #define CONFIG_CMD_I2C
105 #define CONFIG_CMD_MII
106 #define CONFIG_CMD_NET
107 #define CONFIG_NET_RETRY_COUNT 100
109 #define CONFIG_BOOTDELAY 0
111 #define CONFIG_LOADADDR 0x80100000 /* loadaddr env var */
112 #define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x80800000"
114 #define CONFIG_SMC911X 1
115 #define CONFIG_SMC911X_16_BIT 1
116 #define CONFIG_SMC911X_BASE CS5_BASE_ADDR
118 #define CONFIG_HAS_ETH1
119 #define CONFIG_NET_MULTI 1
120 #define CONFIG_ETHPRIME
121 #define CONFIG_MXC_FEC
123 #define CONFIG_DISCOVER_PHY
125 #define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
126 #define CONFIG_FEC0_PINMUX -1
127 #define CONFIG_FEC0_PHY_ADDR 0x1F
128 #define CONFIG_FEC0_MIIBASE -1
131 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
132 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
133 * controller inverted. The controller is capable of detecting and correcting
134 * this, but it needs 4 network packets for that. Which means, at startup, you
135 * will not receive answers to the first 4 packest, unless there have been some
136 * broadcasts on the network, or your board is on a hub. Reducing the ARP
137 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
138 * transfer, should the user wish one, significantly.
140 #define CONFIG_ARP_TIMEOUT 200UL
143 * Miscellaneous configurable options
145 #define CONFIG_SYS_LONGHELP /* undef to save memory */
146 #define CONFIG_SYS_PROMPT "MX35 U-Boot > "
147 #define CONFIG_AUTO_COMPLETE
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
149 /* Print Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x10000
157 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
159 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
161 #define CONFIG_SYS_HZ 1000
163 #define CONFIG_CMDLINE_EDITING 1
165 /*-----------------------------------------------------------------------
168 * The stack sizes are set up in start.S using the settings below
170 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
172 /*-----------------------------------------------------------------------
173 * Physical Memory Map
175 #define CONFIG_NR_DRAM_BANKS 1
176 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
177 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
178 #define iomem_valid_addr(addr, size) \
179 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
184 #ifdef CONFIG_CMD_MMC
186 #define CONFIG_GENERIC_MMC
187 #define CONFIG_IMX_MMC
188 #define CONFIG_SYS_FSL_ESDHC_NUM 2
189 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
190 #define CONFIG_SYS_MMC_ENV_DEV 0
191 #define CONFIG_DOS_PARTITION 1
192 #define CONFIG_CMD_FAT 1
195 #define CONFIG_DOS_PARTITION 1
196 #define CONFIG_CMD_FAT 1
198 /*-----------------------------------------------------------------------
199 * FLASH and environment organization
201 #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
204 /* Monitor at beginning of flash */
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
206 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
208 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
209 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
211 /* Address and size of Redundant Environment Sector */
212 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
213 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
216 * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
217 * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
218 * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
219 * for it. Putting it at the top of flash we use only 32KiB.
221 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
223 #if defined(CONFIG_CMD_MMC)
224 #define CONFIG_ENV_IS_IN_MMC 1
225 #define CONFIG_ENV_OFFSET (768 * 1024)
226 #elif defined(CONFIG_CMD_NAND)
227 #define CONFIG_ENV_IS_IN_NAND 1
228 #define CONFIG_ENV_OFFSET 0x100000
230 #define CONFIG_ENV_IS_IN_FLASH 1
233 /*-----------------------------------------------------------------------
234 * CFI FLASH driver setup
236 #define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
237 #define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
238 /* A non-standard buffered write algorithm */
239 #define CONFIG_FLASH_SPANSION_S29WS_N 1
240 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
241 #define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
243 /*-----------------------------------------------------------------------
244 * NAND FLASH driver setup
246 #define NAND_MAX_CHIPS 1
247 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #define CONFIG_SYS_NAND_BASE 0x40000000
252 #undef CONFIG_JFFS2_CMDLINE
253 #define CONFIG_JFFS2_DEV "nor0"
255 #endif /* __CONFIG_H */