2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/mx51.h>
29 /* High Level Configuration Options */
30 #define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
31 #define CONFIG_SYS_APCS_GNU
34 #define CONFIG_MX51_3DS 1 /* in a mx51 */
35 #define CONFIG_FLASH_HEADER 1
36 #define CONFIG_FLASH_HEADER_OFFSET 0x400
37 #define CONFIG_FLASH_HEADER_BARKER 0xB1
39 #define CONFIG_ARCH_CPU_INIT
40 #define CONFIG_ARCH_MMU
42 #define CONFIG_SKIP_RELOCATE_UBOOT
44 #define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
46 #define CONFIG_DISPLAY_CPUINFO
47 #define CONFIG_DISPLAY_BOARDINFO
49 #define CONFIG_SYS_64BIT_VSPRINTF
51 #define BOARD_LATE_INIT
53 * Disabled for now due to build problems under Debian and a significant
54 * increase in the final file size: 144260 vs. 109536 Bytes.
57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58 #define CONFIG_REVISION_TAG 1
59 #define CONFIG_SETUP_MEMORY_TAGS 1
60 #define CONFIG_INITRD_TAG 1
63 * Size of malloc() pool
65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * 1024 * 1024)
66 /* size in bytes reserved for initial data */
67 #define CONFIG_SYS_GBL_DATA_SIZE 128
72 #define CONFIG_MX51_UART 1
73 #define CONFIG_MX51_UART1 1
79 #define CONFIG_FSL_SF 1
80 #define CONFIG_CMD_SPI
82 #define CONFIG_SPI_FLASH_IMX_ATMEL 1
83 #define CONFIG_SPI_FLASH_CS 1
84 #define CONFIG_IMX_ECSPI
85 #define CONFIG_IMX_SPI_PMIC
86 #define CONFIG_IMX_SPI_PMIC_CS 0
87 #define IMX_CSPI_VER_2_3 1
88 #define MAX_SPI_BYTES (64 * 4)
92 #define CONFIG_CMD_PING
93 #define CONFIG_CMD_DHCP
94 #define CONFIG_BOOTP_SUBNETMASK
95 #define CONFIG_BOOTP_GATEWAY
96 #define CONFIG_BOOTP_DNS
97 #define CONFIG_CMD_MII
98 #define CONFIG_CMD_NET
99 #define CONFIG_NET_RETRY_COUNT 100
101 #define CONFIG_CMD_UBI
102 #define CONFIG_CMD_UBIFS
103 #define CONFIG_CMD_MTDPARTS
104 #define CONFIG_MTD_DEVICE
105 #define CONFIG_MTD_PARTITIONS
106 #define MTDIDS_DEFAULT "nand0=nand0"
107 #define MTDPARTS_DEFAULT "mtdparts=nand0:0x700000@0x0(BOOT),0x100000@0x700000(MISC),0x1400000@0x800000(RECOVERY),-@0x1c00000(ROOT)"
108 #define MTD_ACTIVE_PART "nand0,3"
109 #define CONFIG_RBTREE
113 * Android support Configs
115 #include <asm/arch/keypad.h>
117 #define CONFIG_FSL_ANDROID
119 #define CONFIG_MXC_KPD
120 #define CONFIG_MXC_KEYMAPPING \
122 KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \
123 KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \
124 KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \
125 KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \
127 #define CONFIG_MXC_KPD_COLMAX 6
128 #define CONFIG_MXC_KPD_ROWMAX 4
129 #define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \
130 "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3"
131 #define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
132 "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm"
133 #define CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND \
134 "setenv bootargs ${bootargs} ip=off rootfstype=ubifs root=ubi1:recovery init=/init ubi.mtd=3 ubi.mtd=2"
135 #define CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND \
136 "run bootargs_base bootargs_android;nand read ${loadaddr} 0x300000 0x250000;bootm"
137 #define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
138 #define CONFIG_ANDROID_BOOTMOD_DELAY 3
139 #define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
140 #define CONFIG_ANDROID_UBIFS_PARTITION_NM "ROOT"
141 #define CONFIG_ANDROID_CACHE_PARTITION_NAND "cache"
143 /* allow to overwrite serial and ethaddr */
144 #define CONFIG_ENV_OVERWRITE
145 #define CONFIG_CONS_INDEX 1
146 #define CONFIG_BAUDRATE 115200
147 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
149 /***********************************************************
151 ***********************************************************/
153 #include <config_cmd_default.h>
155 #define CONFIG_CMD_PING
156 #define CONFIG_CMD_DHCP
157 /* Enable below configure when supporting nand */
158 #define CONFIG_CMD_NAND
159 #define CONFIG_MXC_NAND
160 #define CONFIG_CMD_MMC
161 #define CONFIG_CMD_ENV
163 #undef CONFIG_CMD_IMLS
165 #define CONFIG_BOOTDELAY 3
167 #define CONFIG_PRIME "FEC0"
169 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
170 #define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
172 #define CONFIG_EXTRA_ENV_SETTINGS \
174 "ethprime=smc911x\0" \
175 "uboot_addr=0xa0000000\0" \
176 "uboot=u-boot.bin\0" \
178 "rd_loadaddr=0x90B00000\0" \
179 "nfsroot=/opt/eldk/arm\0" \
180 "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
181 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
182 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
183 "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \
184 "bootcmd=run bootcmd_android\0" \
185 "bootcmd_net=run bootargs_base bootargs_nfs; " \
186 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
187 "bootcmd_android=run bootargs_base bootargs_android; " \
188 "mmc read 0 ${loadaddr} 0x800 0x1280; " \
189 "mmc read 0 ${rd_loadaddr} 0x2000 0x258; " \
190 "bootm ${loadaddr} ${rd_loadaddr}\0" \
191 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
192 "protect off ${uboot_addr} 0xa003ffff; " \
193 "erase ${uboot_addr} 0xa003ffff; " \
194 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
195 "setenv filesize; saveenv\0"
198 #define CONFIG_SMC911X 1
199 #define CONFIG_SMC911X_16_BIT 1
200 #define CONFIG_SMC911X_BASE mx51_io_base_addr
205 #ifdef CONFIG_CMD_MMC
207 #define CONFIG_GENERIC_MMC
208 #define CONFIG_IMX_MMC
209 #define CONFIG_SYS_FSL_ESDHC_NUM 2
210 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
211 #define CONFIG_SYS_MMC_ENV_DEV 0
212 #define CONFIG_DOS_PARTITION 1
213 #define CONFIG_CMD_FAT 1
214 #define CONFIG_CMD_EXT2 1
215 #define CONFIG_SYS_FSL_ESDHC_NUM 1
221 #define CONFIG_HAS_ETH1
222 #define CONFIG_NET_MULTI 1
223 #define CONFIG_ETHPRIME
224 #define CONFIG_MXC_FEC
226 #define CONFIG_DISCOVER_PHY
228 #define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
229 #define CONFIG_FEC0_PINMUX -1
230 #define CONFIG_FEC0_PHY_ADDR 0x1F
231 #define CONFIG_FEC0_MIIBASE -1
234 * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
235 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
236 * controller inverted. The controller is capable of detecting and correcting
237 * this, but it needs 4 network packets for that. Which means, at startup, you
238 * will not receive answers to the first 4 packest, unless there have been some
239 * broadcasts on the network, or your board is on a hub. Reducing the ARP
240 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
241 * transfer, should the user wish one, significantly.
243 #define CONFIG_ARP_TIMEOUT 200UL
246 * Miscellaneous configurable options
248 #define CONFIG_SYS_LONGHELP /* undef to save memory */
249 #define CONFIG_SYS_PROMPT "MX51 U-Boot > "
250 #define CONFIG_AUTO_COMPLETE
251 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
252 /* Print Buffer Size */
253 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
254 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
255 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
257 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
258 #define CONFIG_SYS_MEMTEST_END 0x10000
260 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
262 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
264 #define CONFIG_SYS_HZ 1000
266 #define CONFIG_CMDLINE_EDITING 1
268 /*-----------------------------------------------------------------------
271 * The stack sizes are set up in start.S using the settings below
273 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
275 /*-----------------------------------------------------------------------
276 * Physical Memory Map
278 #define CONFIG_NR_DRAM_BANKS 1
279 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
280 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
281 #define iomem_valid_addr(addr, size) \
282 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
284 /*-----------------------------------------------------------------------
285 * FLASH and environment organization
287 #define CONFIG_SYS_NO_FLASH
289 /*-----------------------------------------------------------------------
290 * NAND FLASH driver setup
292 #define NAND_MAX_CHIPS 8
293 #define CONFIG_SYS_MAX_NAND_DEVICE 1
294 #define CONFIG_SYS_NAND_BASE 0x40000000
296 /* Monitor at beginning of flash */
297 /* #define CONFIG_FSL_ENV_IN_MMC */
298 #define CONFIG_FSL_ENV_IN_NAND
300 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
301 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
303 #if defined(CONFIG_FSL_ENV_IN_NAND)
304 #define CONFIG_ENV_IS_IN_NAND 1
305 #define CONFIG_ENV_OFFSET 0x100000
306 #elif defined(CONFIG_FSL_ENV_IN_MMC)
307 #define CONFIG_ENV_IS_IN_MMC 1
308 #define CONFIG_ENV_OFFSET (768 * 1024)
309 #elif defined(CONFIG_FSL_ENV_IN_SF)
310 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
311 #define CONFIG_ENV_SPI_CS 1
312 #define CONFIG_ENV_OFFSET (768 * 1024)
314 #define CONFIG_ENV_IS_NOWHERE 1
319 #undef CONFIG_JFFS2_CMDLINE
320 #define CONFIG_JFFS2_DEV "nand0"
322 #endif /* __CONFIG_H */