include/configs/palmld.h

   1 /*
   2  * Palm LifeDrive configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Board Configuration Options
  27  */
  28 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  29 #define CONFIG_PALMLD           1       /* Palm LifeDrive board */
  30
  31 /* we will never enable dcache, because we have to setup MMU first */
  32 #define CONFIG_SYS_DCACHE_OFF
  33
  34 /*
  35  * Environment settings
  36  */
  37 #define CONFIG_ENV_OVERWRITE
  38 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  39 #define CONFIG_SYS_TEXT_BASE    0x0
  40
  41 #define CONFIG_BOOTCOMMAND                                              \
  42         "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "   \
  43                 "source 0xa0000000; "                                   \
  44         "else "                                                         \
  45                 "bootm 0x0x60000; "                                     \
  46         "fi; "
  47 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,9600"
  48 #define CONFIG_TIMESTAMP
  49 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  50 #define CONFIG_CMDLINE_TAG
  51 #define CONFIG_SETUP_MEMORY_TAGS
  52
  53 #define CONFIG_LZMA                     /* LZMA compression support */
  54
  55 /*
  56  * Serial Console Configuration
  57  */
  58 #define CONFIG_PXA_SERIAL
  59 #define CONFIG_FFUART                   1
  60 #define CONFIG_CONS_INDEX               3
  61 #define CONFIG_BAUDRATE                 9600
  62
  63 /*
  64  * Bootloader Components Configuration
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #undef  CONFIG_CMD_NET
  69 #undef  CONFIG_CMD_NFS
  70 #define CONFIG_CMD_ENV
  71 #undef  CONFIG_CMD_IMLS
  72 #define CONFIG_CMD_MMC
  73 #define CONFIG_CMD_IDE
  74 #define CONFIG_LCD
  75 #define CONFIG_PXA_LCD
  76
  77 /*
  78  * MMC Card Configuration
  79  */
  80 #ifdef  CONFIG_CMD_MMC
  81 #define CONFIG_MMC
  82 #define CONFIG_GENERIC_MMC
  83 #define CONFIG_PXA_MMC_GENERIC
  84 #define CONFIG_SYS_MMC_BASE             0xF0000000
  85 #define CONFIG_CMD_FAT
  86 #define CONFIG_CMD_EXT2
  87 #define CONFIG_DOS_PARTITION
  88 #endif
  89
  90 /*
  91  * LCD
  92  */
  93 #ifdef CONFIG_LCD
  94 #define CONFIG_LQ038J7DH53
  95 #define CONFIG_VIDEO_LOGO
  96 #define CONFIG_CMD_BMP
  97 #define CONFIG_SPLASH_SCREEN
  98 #define CONFIG_SPLASH_SCREEN_ALIGN
  99 #define CONFIG_VIDEO_BMP_GZIP
 100 #define CONFIG_VIDEO_BMP_RLE8
 101 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
 102 #endif
 103
 104 /*
 105  * KGDB
 106  */
 107 #ifdef  CONFIG_CMD_KGDB
 108 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
 109 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 110 #endif
 111
 112 /*
 113  * HUSH Shell Configuration
 114  */
 115 #define CONFIG_SYS_HUSH_PARSER          1
 116
 117 #define CONFIG_SYS_LONGHELP
 118 #ifdef  CONFIG_SYS_HUSH_PARSER
 119 #define CONFIG_SYS_PROMPT               "$ "
 120 #else
 121 #define CONFIG_SYS_PROMPT               "=> "
 122 #endif
 123 #define CONFIG_SYS_CBSIZE               256
 124 #define CONFIG_SYS_PBSIZE               \
 125         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 126 #define CONFIG_SYS_MAXARGS              16
 127 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 128 #define CONFIG_SYS_DEVICE_NULLDEV       1
 129
 130 /*
 131  * Clock Configuration
 132  */
 133 #undef  CONFIG_SYS_CLKS_IN_HZ
 134 #define CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
 135 #define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
 136
 137 /*
 138  * DRAM Map
 139  */
 140 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
 141 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 142 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
 143
 144 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 145 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
 146
 147 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 148 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 149
 150 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 151
 152 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 153 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 154
 155 /*
 156  * NOR FLASH
 157  */
 158 #ifdef  CONFIG_CMD_FLASH
 159 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 160 #define PHYS_FLASH_SIZE                 0x00080000      /* 512 KB */
 161 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 162
 163 #define CONFIG_SYS_FLASH_CFI
 164 #define CONFIG_FLASH_CFI_DRIVER         1
 165
 166 #define CONFIG_FLASH_CFI_LEGACY
 167 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 168
 169 #define CONFIG_SYS_MONITOR_BASE         0
 170 #define CONFIG_SYS_MONITOR_LEN          0x40000
 171
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 173 #define CONFIG_SYS_MAX_FLASH_SECT       256
 174
 175 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 176
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
 178 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
 179 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25*CONFIG_SYS_HZ)
 180 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25*CONFIG_SYS_HZ)
 181 #define CONFIG_SYS_FLASH_PROTECTION
 182
 183 #define CONFIG_ENV_IS_IN_FLASH          1
 184 #define CONFIG_ENV_SECT_SIZE            0x10000
 185 #else
 186 #define CONFIG_SYS_NO_FLASH
 187 #define CONFIG_ENV_IS_NOWHERE
 188 #endif
 189
 190 #define CONFIG_ENV_ADDR                 0x40000
 191 #define CONFIG_ENV_SIZE                 0x4000
 192
 193 /*
 194  * IDE
 195  */
 196 #ifdef  CONFIG_CMD_IDE
 197 #define CONFIG_LBA48
 198 #undef  CONFIG_IDE_LED
 199 #undef  CONFIG_IDE_RESET
 200
 201 #define __io
 202
 203 #define CONFIG_SYS_IDE_MAXBUS           1
 204 #define CONFIG_SYS_IDE_MAXDEVICE        1
 205
 206 #define CONFIG_SYS_ATA_BASE_ADDR        0x20000000
 207 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
 208
 209 #define CONFIG_SYS_ATA_DATA_OFFSET      0x10
 210 #define CONFIG_SYS_ATA_REG_OFFSET       0x10
 211 #define CONFIG_SYS_ATA_ALT_OFFSET       0x10
 212
 213 #define CONFIG_SYS_ATA_STRIDE           1
 214 #endif
 215
 216 /*
 217  * GPIO settings
 218  */
 219 #define CONFIG_SYS_GAFR0_L_VAL  0x00000000
 220 #define CONFIG_SYS_GAFR0_U_VAL  0xa5180012
 221 #define CONFIG_SYS_GAFR1_L_VAL  0x69988056
 222 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa580aa
 223 #define CONFIG_SYS_GAFR2_L_VAL  0x6aaaaaaa
 224 #define CONFIG_SYS_GAFR2_U_VAL  0x01040001
 225 #define CONFIG_SYS_GAFR3_L_VAL  0x540a950c
 226 #define CONFIG_SYS_GAFR3_U_VAL  0x00000009
 227 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 228 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 229 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 230 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 231 #define CONFIG_SYS_GPDR0_VAL    0xc26b0000
 232 #define CONFIG_SYS_GPDR1_VAL    0xfcdfaa93
 233 #define CONFIG_SYS_GPDR2_VAL    0x7bbaffff
 234 #define CONFIG_SYS_GPDR3_VAL    0x006ff38d
 235 #define CONFIG_SYS_GPSR0_VAL    0x0d9e45ee
 236 #define CONFIG_SYS_GPSR1_VAL    0x03affdae
 237 #define CONFIG_SYS_GPSR2_VAL    0x07554000
 238 #define CONFIG_SYS_GPSR3_VAL    0x01bc0785
 239
 240 #define CONFIG_SYS_PSSR_VAL     0x30
 241
 242 /*
 243  * Clock settings
 244  */
 245 #define CONFIG_SYS_CKEN         0x01ffffff
 246 #define CONFIG_SYS_CCCR         0x02000210
 247
 248 /*
 249  * Memory settings
 250  */
 251 #define CONFIG_SYS_MSC0_VAL     0x7ff844c8
 252 #define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
 253 #define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
 254 #define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
 255 #define CONFIG_SYS_MDREFR_VAL   0x201fa031
 256 #define CONFIG_SYS_MDMRS_VAL    0x00320032
 257 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 258 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 259
 260 /*
 261  * PCMCIA and CF Interfaces
 262  */
 263 #define CONFIG_SYS_MECR_VAL     0x00000003
 264 #define CONFIG_SYS_MCMEM0_VAL   0x0001c391
 265 #define CONFIG_SYS_MCMEM1_VAL   0x0001c391
 266 #define CONFIG_SYS_MCATT0_VAL   0x0001c391
 267 #define CONFIG_SYS_MCATT1_VAL   0x0001c391
 268 #define CONFIG_SYS_MCIO0_VAL    0x00014611
 269 #define CONFIG_SYS_MCIO1_VAL    0x0001c391
 270
 271 #endif  /* __CONFIG_H */