include/configs/pm9g45.h

   1 /*
   2  * (C) Copyright 2010
   3  * Ilko Iliev <iliev@ronetix.at>
   4  * Asen Dimov <dimov@ronetix.at>
   5  * Ronetix GmbH <www.ronetix.at>
   6  *
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * Configuation settings for the PM9G45 board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * SoC must be defined first, before hardware.h is included.
  21  * In this case SoC is defined in boards.cfg.
  22  */
  23 #include <asm/hardware.h>
  24
  25 #define CONFIG_SYS_GENERIC_BOARD
  26
  27 #define CONFIG_PM9G45           1       /* It's an Ronetix PM9G45 */
  28 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9G45"
  29
  30 #define MACH_TYPE_PM9G45        2672
  31 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9G45
  32
  33 /* ARM asynchronous clock */
  34 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  35 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  36 #define CONFIG_SYS_TEXT_BASE            0x73f00000
  37
  38 #define CONFIG_ARCH_CPU_INIT
  39
  40 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
  41 #define CONFIG_SETUP_MEMORY_TAGS 1
  42 #define CONFIG_INITRD_TAG       1
  43
  44 #define CONFIG_SKIP_LOWLEVEL_INIT
  45 #define CONFIG_BOARD_EARLY_INIT_F
  46
  47 /*
  48  * Hardware drivers
  49  */
  50 #define CONFIG_AT91_GPIO        1
  51 #define CONFIG_ATMEL_USART      1
  52 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  53 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  54
  55 #define CONFIG_SYS_USE_NANDFLASH        1
  56
  57 /* LED */
  58 #define CONFIG_AT91_LED
  59 #define CONFIG_RED_LED          GPIO_PIN_PD(31) /* this is the user1 led */
  60 #define CONFIG_GREEN_LED        GPIO_PIN_PD(0)  /* this is the user2 led */
  61
  62 #define CONFIG_BOOTDELAY        3
  63
  64 /*
  65  * BOOTP options
  66  */
  67 #define CONFIG_BOOTP_BOOTFILESIZE       1
  68 #define CONFIG_BOOTP_BOOTPATH           1
  69 #define CONFIG_BOOTP_GATEWAY            1
  70 #define CONFIG_BOOTP_HOSTNAME           1
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #define CONFIG_CMD_CACHE
  76 #define CONFIG_CMD_PING         1
  77 #define CONFIG_CMD_DHCP         1
  78 #define CONFIG_CMD_NAND         1
  79 #define CONFIG_CMD_USB          1
  80
  81 #define CONFIG_CMD_JFFS2                1
  82 #define CONFIG_JFFS2_CMDLINE            1
  83 #define CONFIG_JFFS2_NAND               1
  84 #define CONFIG_JFFS2_DEV                "nand0" /* NAND dev jffs2 lives on */
  85 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
  86 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition */
  87
  88 /* SDRAM */
  89 #define CONFIG_NR_DRAM_BANKS            1
  90 #define PHYS_SDRAM                      0x70000000
  91 #define PHYS_SDRAM_SIZE                 0x08000000      /* 128 megs */
  92
  93 /* NOR flash, not available */
  94 #define CONFIG_SYS_NO_FLASH             1
  95
  96 /* NAND flash */
  97 #ifdef CONFIG_CMD_NAND
  98 #define CONFIG_NAND_ATMEL
  99 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 100 #define CONFIG_SYS_NAND_BASE            0x40000000
 101 #define CONFIG_SYS_NAND_DBW_8           1
 102 /* our ALE is AD21 */
 103 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 104 /* our CLE is AD22 */
 105 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 106 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
 107 #define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PD(3)
 108
 109 #endif
 110
 111 /* Ethernet */
 112 #define CONFIG_MACB                     1
 113 #define CONFIG_RMII                     1
 114 #define CONFIG_NET_RETRY_COUNT          20
 115 #define CONFIG_RESET_PHY_R              1
 116
 117 /* USB */
 118 #define CONFIG_USB_ATMEL
 119 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 120 #define CONFIG_USB_OHCI_NEW             1
 121 #define CONFIG_DOS_PARTITION            1
 122 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 123 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00700000 /* _UHP_OHCI_BASE */
 124 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9g45"
 125 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 126 #define CONFIG_USB_STORAGE              1
 127
 128 /* board specific(not enough SRAM) */
 129 #define CONFIG_AT91SAM9G45_LCD_BASE     PHYS_SDRAM + 0xE00000
 130
 131 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM + 0x2000000 /* load addr */
 132
 133 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM
 134 #define CONFIG_SYS_MEMTEST_END          CONFIG_AT91SAM9G45_LCD_BASE
 135
 136 /* bootstrap + u-boot + env + linux in nandflash */
 137 #define CONFIG_ENV_IS_IN_NAND           1
 138 #define CONFIG_ENV_OFFSET               0x60000
 139 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 140 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 141 #define CONFIG_BOOTCOMMAND      "nand read 0x72000000 0x200000 0x200000; bootm"
 142 #define CONFIG_BOOTARGS         "fbcon=rotate:3 console=tty0 " \
 143                                 "console=ttyS0,115200 " \
 144                                 "root=/dev/mtdblock4 " \
 145                                 "mtdparts=atmel_nand:128k(bootstrap)ro," \
 146                                 "256k(uboot)ro,1664k(env)," \
 147                                 "2M(linux)ro,-(root) rw " \
 148                                 "rootfstype=jffs2"
 149
 150 #define CONFIG_BAUDRATE                 115200
 151
 152 #define CONFIG_SYS_CBSIZE               256
 153 #define CONFIG_SYS_MAXARGS              16
 154 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 155                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 156 #define CONFIG_SYS_LONGHELP             1
 157 #define CONFIG_CMDLINE_EDITING          1
 158 #define CONFIG_AUTO_COMPLETE
 159 #define CONFIG_SYS_HUSH_PARSER
 160
 161 /*
 162  * Size of malloc() pool
 163  */
 164 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 165                                         0x1000)
 166
 167 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 168 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 169                                 GENERATED_GBL_DATA_SIZE)
 170
 171 #endif