include/configs/socfpga_arria5.h

   1 /*
   2  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_ARRIA5_H__
   7 #define __CONFIG_SOCFPGA_ARRIA5_H__
   8
   9 #include <asm/arch/socfpga_base_addrs.h>
  10
  11 /* U-Boot Commands */
  12 #define CONFIG_SYS_NO_FLASH
  13 #define CONFIG_DOS_PARTITION
  14 #define CONFIG_FAT_WRITE
  15 #define CONFIG_HW_WATCHDOG
  16
  17 #define CONFIG_CMD_ASKENV
  18 #define CONFIG_CMD_BOOTZ
  19 #define CONFIG_CMD_CACHE
  20 #define CONFIG_CMD_DFU
  21 #define CONFIG_CMD_DHCP
  22 #define CONFIG_CMD_EXT4
  23 #define CONFIG_CMD_EXT4_WRITE
  24 #define CONFIG_CMD_FAT
  25 #define CONFIG_CMD_FS_GENERIC
  26 #define CONFIG_CMD_GREPENV
  27 #define CONFIG_CMD_MII
  28 #define CONFIG_CMD_MMC
  29 #define CONFIG_CMD_PING
  30 #define CONFIG_CMD_USB
  31 #define CONFIG_CMD_USB_MASS_STORAGE
  32
  33
  34 /* Memory configurations */
  35 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1GiB on SoCDK */
  36
  37 /* Booting Linux */
  38 #define CONFIG_BOOTDELAY        3
  39 #define CONFIG_BOOTFILE         "zImage"
  40 #define CONFIG_BOOTARGS         "console=ttyS0," __stringify(CONFIG_BAUDRATE)
  41 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  42 #define CONFIG_BOOTCOMMAND      "run ramboot"
  43 #else
  44 #define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
  45 #endif
  46 #define CONFIG_LOADADDR         0x8000
  47 #define CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
  48
  49 /* Ethernet on SoC (EMAC) */
  50 #if defined(CONFIG_CMD_NET)
  51 #define CONFIG_EMAC_BASE                SOCFPGA_EMAC1_ADDRESS
  52 #define CONFIG_PHY_INTERFACE_MODE       PHY_INTERFACE_MODE_RGMII
  53
  54 /* PHY */
  55 #define CONFIG_PHY_MICREL
  56 #define CONFIG_PHY_MICREL_KSZ9021
  57 #define CONFIG_KSZ9021_CLK_SKEW_ENV     "micrel-ksz9021-clk-skew"
  58 #define CONFIG_KSZ9021_CLK_SKEW_VAL     0xf0f0
  59 #define CONFIG_KSZ9021_DATA_SKEW_ENV    "micrel-ksz9021-data-skew"
  60 #define CONFIG_KSZ9021_DATA_SKEW_VAL    0x0
  61
  62 #endif
  63
  64 /* USB */
  65 #ifdef CONFIG_CMD_USB
  66 #define CONFIG_USB_DWC2_REG_ADDR        SOCFPGA_USB1_ADDRESS
  67 #endif
  68 #define CONFIG_G_DNL_MANUFACTURER      "Altera"
  69
  70 /* Extra Environment */
  71 #define CONFIG_HOSTNAME         socfpga_arria5
  72
  73 #define CONFIG_EXTRA_ENV_SETTINGS \
  74         "verify=n\0" \
  75         "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  76         "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  77                 "bootm ${loadaddr} - ${fdt_addr}\0" \
  78         "bootimage=zImage\0" \
  79         "fdt_addr=100\0" \
  80         "fdtimage=socfpga.dtb\0" \
  81                 "fsloadcmd=ext2load\0" \
  82         "bootm ${loadaddr} - ${fdt_addr}\0" \
  83         "mmcroot=/dev/mmcblk0p2\0" \
  84         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  85                 " root=${mmcroot} rw rootwait;" \
  86                 "bootz ${loadaddr} - ${fdt_addr}\0" \
  87         "mmcload=mmc rescan;" \
  88                 "load mmc 0:1 ${loadaddr} ${bootimage};" \
  89                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  90         "qspiroot=/dev/mtdblock0\0" \
  91         "qspirootfstype=jffs2\0" \
  92         "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  93                 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  94                 "bootm ${loadaddr} - ${fdt_addr}\0"
  95
  96 /* The rest of the configuration is shared */
  97 #include <configs/socfpga_common.h>
  98
  99 #endif  /* __CONFIG_SOCFPGA_ARRIA5_H__ */