karo: reset fdtaddr to the original value due to prevent overlap with linux kernel
[karo-tx-uboot.git] / include / configs / tx48.h
1 /*
2  * tx48.h
3  *
4  * Copyright (C) 2012-2014 Lothar WaƟmann <LW@KARO-electronics.de>
5  *
6  * based on: am335x_evm
7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8  *
9  * SPDX-License-Identifier:      GPL-2.0
10  *
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 #define CONFIG_AM33XX                   /* must be set before including omap.h */
17
18 #include <asm/sizes.h>
19 #include <asm/arch/omap.h>
20
21 /*
22  * Ka-Ro TX48 board - SoC configuration
23  */
24 #define CONFIG_OMAP
25 #define CONFIG_AM33XX_GPIO
26 #define CONFIG_SYS_HZ                   1000    /* Ticks per second */
27
28 #ifndef CONFIG_SPL_BUILD
29 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_SHOW_ACTIVITY
31 #define CONFIG_DISPLAY_CPUINFO
32 #define CONFIG_DISPLAY_BOARDINFO
33 #define CONFIG_BOARD_LATE_INIT
34
35 /* LCD Logo and Splash screen support */
36 #define CONFIG_LCD
37 #ifdef CONFIG_LCD
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_SPLASH_SCREEN_ALIGN
40 #define CONFIG_VIDEO_DA8XX
41 #define DAVINCI_LCD_CNTL_BASE           0x4830e000
42 #define CONFIG_LCD_LOGO
43 #define LCD_BPP                         LCD_COLOR24
44 #define CONFIG_CMD_BMP
45 #define CONFIG_VIDEO_BMP_RLE8
46 #endif /* CONFIG_LCD */
47 #endif /* CONFIG_SPL_BUILD */
48
49 /* Clock Defines */
50 #define V_OSCK                          24000000  /* Clock output from T2 */
51 #define V_SCLK                          V_OSCK
52
53 /*
54  * Memory configuration options
55  */
56 #define CONFIG_SYS_SDRAM_DDR3
57 #define CONFIG_NR_DRAM_BANKS            1               /*  1 bank of SDRAM */
58 #define PHYS_SDRAM_1                    0x80000000      /* SDRAM Bank #1 */
59 #define CONFIG_MAX_RAM_BANK_SIZE        SZ_1G
60
61 #define CONFIG_STACKSIZE                SZ_64K
62 #define CONFIG_SYS_MALLOC_LEN           SZ_4M
63
64 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + SZ_64M)
65 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + SZ_8M)
66
67 #define CONFIG_SYS_CACHELINE_SIZE       64
68
69 /*
70  * U-Boot general configurations
71  */
72 #define CONFIG_SYS_LONGHELP
73 #define CONFIG_SYS_PROMPT               "TX48 U-Boot > "
74 #define CONFIG_SYS_CBSIZE               2048    /* Console I/O buffer size */
75 #define CONFIG_SYS_PBSIZE \
76         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
77                                                 /* Print buffer size */
78 #define CONFIG_SYS_MAXARGS              256     /* Max number of command args */
79 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
80                                                 /* Boot argument buffer size */
81 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
82 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
83 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
84
85 #define CONFIG_SYS_64BIT_VSPRINTF
86 #define CONFIG_SYS_NO_FLASH
87
88 /*
89  * Flattened Device Tree (FDT) support
90 */
91 #define CONFIG_OF_LIBFDT
92 #define CONFIG_OF_BOARD_SETUP
93
94 /*
95  * Boot Linux
96  */
97 #define xstr(s)                         str(s)
98 #define str(s)                          #s
99 #define __pfx(x, s)                     (x##s)
100 #define _pfx(x, s)                      __pfx(x, s)
101
102 #define CONFIG_CMDLINE_TAG
103 #define CONFIG_SETUP_MEMORY_TAGS
104 #define CONFIG_BOOTDELAY                3
105 #define CONFIG_ZERO_BOOTDELAY_CHECK
106 #define CONFIG_SYS_AUTOLOAD             "no"
107 #define CONFIG_BOOTFILE                 "uImage"
108 #define CONFIG_BOOTARGS                 "init=/linuxrc console=ttyO0,115200 ro debug panic=1"
109 #define CONFIG_BOOTCOMMAND              "run bootcmd_${boot_mode} bootm_cmd"
110 #define CONFIG_LOADADDR                 83000000
111 #define CONFIG_FDTADDR                  81000000
112 #define CONFIG_SYS_LOAD_ADDR            _pfx(0x, CONFIG_LOADADDR)
113 #define CONFIG_SYS_FDT_ADDR             _pfx(0x, CONFIG_FDTADDR)
114 #define CONFIG_U_BOOT_IMG_SIZE          SZ_1M
115 #define CONFIG_HW_WATCHDOG
116
117 /*
118  * Extra Environment Settings
119  */
120 #define CONFIG_SYS_CPU_CLK_STR          xstr(CONFIG_SYS_MPU_CLK)
121
122 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
123         "autostart=no\0"                                                \
124         "baseboard=stk5-v3\0"                                           \
125         "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}"  \
126         " root=/dev/mtdblock4 rootfstype=jffs2\0"                       \
127         "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}"    \
128         " root=/dev/mmcblk0p2 rootwait\0"                               \
129         "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}"    \
130         " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock"        \
131         " ip=dhcp\0"                                                    \
132         "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}"  \
133         " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0"           \
134         "bootcmd_jffs2=set autostart no;run bootargs_jffs2"             \
135         ";nboot linux\0"                                                \
136         "bootcmd_mmc=set autostart no;run bootargs_mmc"                 \
137         ";fatload mmc 0 ${loadaddr} uImage\0"                           \
138         "bootcmd_nand=set autostart no;run bootargs_ubifs"              \
139         ";nboot linux\0"                                                \
140         "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs"   \
141         ";dhcp\0"                                                       \
142         "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"                    \
143         "boot_mode=nand\0"                                              \
144         "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0"                          \
145         "default_bootargs=set bootargs " CONFIG_BOOTARGS                \
146         " ${append_bootargs}\0"                                         \
147         "fdtaddr=" xstr(CONFIG_FDTADDR) "\0"                            \
148         "fdtsave=fdt resize;nand erase.part dtb"                        \
149         ";nand write ${fdtaddr} dtb ${fdtsize}\0"                       \
150         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
151         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
152         "nfsroot=/tftpboot/rootfs\0"                                    \
153         "otg_mode=device\0"                                             \
154         "touchpanel=tsc2007\0"                                          \
155         "video_mode=VGA\0"
156
157 #define MTD_NAME                        "omap2-nand.0"
158 #define MTDIDS_DEFAULT                  "nand0=" MTD_NAME
159 #define CONFIG_FDT_FIXUP_PARTITIONS
160
161 /*
162  * U-Boot Commands
163  */
164 #include <config_cmd_default.h>
165 #define CONFIG_CMD_CACHE
166 #define CONFIG_CMD_MMC
167 #define CONFIG_CMD_NAND
168 #define CONFIG_CMD_MTDPARTS
169 #define CONFIG_CMD_BOOTCE
170 #define CONFIG_CMD_TIME
171 #define CONFIG_CMD_MEMTEST
172
173 /*
174  * Serial Driver
175  */
176 #define CONFIG_SYS_NS16550
177 #define CONFIG_SYS_NS16550_SERIAL
178 #define CONFIG_SYS_NS16550_MEM32
179 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
180 #define CONFIG_SYS_NS16550_CLK          48000000
181 #define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
182 #define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
183 #define CONFIG_SYS_NS16550_COM6         0x481aa000      /* UART5 */
184
185 #define CONFIG_SYS_NS16550_COM3         0x481aa000      /* UART2 */
186 #define CONFIG_SYS_NS16550_COM4         0x481aa000      /* UART3 */
187 #define CONFIG_SYS_NS16550_COM5         0x481aa000      /* UART4 */
188 #define CONFIG_CONS_INDEX               1               /* one based! */
189 #define CONFIG_BAUDRATE                 115200          /* Default baud rate */
190 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, }
191 #define CONFIG_SYS_CONSOLE_INFO_QUIET
192
193 /*
194  * Ethernet Driver
195  */
196 #ifdef CONFIG_CMD_NET
197 #define CONFIG_DRIVER_TI_CPSW
198 #define CONFIG_NET_MULTI
199 #define CONFIG_PHY_GIGE
200 #define CONFIG_PHY_SMSC
201 #define CONFIG_PHYLIB
202 #define CONFIG_MII
203 #define CONFIG_CMD_MII
204 #define CONFIG_CMD_DHCP
205 #define CONFIG_CMD_PING
206 /* Add for working with "strict" DHCP server */
207 #define CONFIG_BOOTP_SUBNETMASK
208 #define CONFIG_BOOTP_GATEWAY
209 #define CONFIG_BOOTP_DNS
210 #define CONFIG_BOOTP_DNS2
211 #endif
212
213 /*
214  * NAND flash driver
215  */
216 #ifdef CONFIG_CMD_NAND
217 #define CONFIG_MTD_DEVICE
218 #define CONFIG_ENV_IS_IN_NAND
219 #define CONFIG_NAND_OMAP_GPMC
220 #ifndef CONFIG_SPL_BUILD
221 #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
222 #endif
223 #define GPMC_NAND_ECC_LP_x8_LAYOUT
224 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL  GPMC_NAND_HW_ECC_LAYOUT
225 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
226 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
227 #define CONFIG_SYS_NAND_OOBSIZE         64
228 #define CONFIG_SYS_NAND_ECCSIZE         512
229 #define CONFIG_SYS_NAND_ECCBYTES        14
230 #define CONFIG_CMD_NAND_TRIMFFS
231 #define CONFIG_SYS_NAND_MAX_CHIPS       1
232 #define CONFIG_SYS_NAND_MAXBAD          20 /* Max. number of bad blocks guaranteed by manufacturer */
233 #define CONFIG_SYS_MAX_NAND_DEVICE      1
234 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
235 #define CONFIG_SYS_NAND_USE_FLASH_BBT
236 #ifdef CONFIG_ENV_IS_IN_NAND
237 #define CONFIG_ENV_OVERWRITE
238 #define CONFIG_ENV_OFFSET               (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
239 #define CONFIG_ENV_SIZE                 SZ_128K
240 #define CONFIG_ENV_RANGE                0x60000
241 #endif /* CONFIG_ENV_IS_IN_NAND */
242 #define CONFIG_SYS_NAND_BASE            0x00100000
243 #define CONFIG_SYS_NAND_SIZE            SZ_128M
244 #define NAND_BASE                       CONFIG_SYS_NAND_BASE
245 #endif /* CONFIG_CMD_NAND */
246
247 /*
248  * MMC Driver
249  */
250 #ifdef CONFIG_CMD_MMC
251 #ifndef CONFIG_ENV_IS_IN_NAND
252 #define CONFIG_ENV_IS_IN_MMC
253 #endif
254 #define CONFIG_MMC
255 #define CONFIG_GENERIC_MMC
256 #define CONFIG_OMAP_HSMMC
257 #define CONFIG_OMAP_MMC_DEV_1
258
259 #define CONFIG_DOS_PARTITION
260 #define CONFIG_CMD_FAT
261 #define CONFIG_FAT_WRITE
262 #define CONFIG_CMD_EXT2
263
264 /*
265  * Environments on MMC
266  */
267 #ifdef CONFIG_ENV_IS_IN_MMC
268 #define CONFIG_SYS_MMC_ENV_DEV          0
269 #define CONFIG_ENV_OVERWRITE
270 /* Associated with the MMC layout defined in mmcops.c */
271 #define CONFIG_ENV_OFFSET               SZ_1K
272 #define CONFIG_ENV_SIZE                 (SZ_128K - CONFIG_ENV_OFFSET)
273 #define CONFIG_DYNAMIC_MMC_DEVNO
274 #endif /* CONFIG_ENV_IS_IN_MMC */
275 #endif /* CONFIG_CMD_MMC */
276
277 #ifdef CONFIG_ENV_OFFSET_REDUND
278 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
279         "128k(u-boot-spl),"                                             \
280         "1m(u-boot),"                                                   \
281         xstr(CONFIG_ENV_RANGE)                                          \
282         "(env),"                                                        \
283         xstr(CONFIG_ENV_RANGE)                                          \
284         "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
285 #else
286 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
287         "128k(u-boot-spl),"                                             \
288         "1m(u-boot),"                                                   \
289         xstr(CONFIG_ENV_RANGE)                                          \
290         "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
291 #endif
292
293 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
294 #define SRAM0_SIZE                      SZ_64K
295 #define OCMC_SRAM_BASE                  0x40300000
296 #define CONFIG_SPL_STACK                (OCMC_SRAM_BASE + 0xb800)
297 #define CONFIG_SYS_INIT_SP_ADDR         (PHYS_SDRAM_1 + SZ_32K)
298
299  /* Platform/Board specific defs */
300 #define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
301 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
302
303 /* Defines for SPL */
304 #define CONFIG_SPL
305 #define CONFIG_SPL_FRAMEWORK
306 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
307 #define CONFIG_SPL_GPIO_SUPPORT
308 #ifdef CONFIG_NAND_OMAP_GPMC
309 #define CONFIG_SPL_NAND_SUPPORT
310 #define CONFIG_SPL_NAND_DRIVERS
311 #define CONFIG_SPL_NAND_BASE
312 #define CONFIG_SPL_NAND_ECC
313 #define CONFIG_SPL_NAND_AM33XX_BCH
314 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
315 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE /   \
316                                         CONFIG_SYS_NAND_PAGE_SIZE)
317 #define CONFIG_SYS_NAND_BLOCK_SIZE      SZ_128K
318 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
319 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
320                                          10, 11, 12, 13, 14, 15, 16, 17, \
321                                          18, 19, 20, 21, 22, 23, 24, 25, \
322                                          26, 27, 28, 29, 30, 31, 32, 33, \
323                                          34, 35, 36, 37, 38, 39, 40, 41, \
324                                          42, 43, 44, 45, 46, 47, 48, 49, \
325                                          50, 51, 52, 53, 54, 55, 56, 57, }
326 #endif
327
328 #define CONFIG_SPL_BSS_START_ADDR       PHYS_SDRAM_1
329 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_512K
330
331 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
332
333 #define CONFIG_SPL_LIBCOMMON_SUPPORT
334 #define CONFIG_SPL_LIBGENERIC_SUPPORT
335 #define CONFIG_SPL_SERIAL_SUPPORT
336 #define CONFIG_SPL_YMODEM_SUPPORT
337 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
338
339 /*
340  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
341  * 64 bytes before this address should be set aside for u-boot.img's
342  * header. That is 0x800FFFC0--0x80100000 should not be used for any
343  * other needs.
344  */
345 #define CONFIG_SYS_SPL_MALLOC_START     (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
346 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
347
348 #endif  /* __CONFIG_H */