10e2e2fa2a1a606df1246b982cd23fc831e873a5
[karo-tx-uboot.git] / include / configs / tx48.h
1 /*
2  * tx48.h
3  *
4  * Copyright (C) 2012-2014 Lothar WaƟmann <LW@KARO-electronics.de>
5  *
6  * based on: am335x_evm
7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8  *
9  * SPDX-License-Identifier:      GPL-2.0
10  *
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 #define CONFIG_AM33XX                   /* must be set before including omap.h */
17
18 #include <asm/sizes.h>
19 #include <asm/arch/omap.h>
20
21 /*
22  * Ka-Ro TX48 board - SoC configuration
23  */
24 #define CONFIG_OMAP
25 #define CONFIG_AM33XX_GPIO
26 #define CONFIG_SYS_HZ                   1000    /* Ticks per second */
27
28 #ifndef CONFIG_SPL_BUILD
29 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_SHOW_ACTIVITY
31 #define CONFIG_DISPLAY_CPUINFO
32 #define CONFIG_DISPLAY_BOARDINFO
33 #define CONFIG_BOARD_LATE_INIT
34
35 /* LCD Logo and Splash screen support */
36 #define CONFIG_LCD
37 #ifdef CONFIG_LCD
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_SPLASH_SCREEN_ALIGN
40 #define CONFIG_VIDEO_DA8XX
41 #define DAVINCI_LCD_CNTL_BASE           0x4830e000
42 #define CONFIG_LCD_LOGO
43 #define LCD_BPP                         LCD_COLOR24
44 #define CONFIG_CMD_BMP
45 #define CONFIG_VIDEO_BMP_RLE8
46 #endif /* CONFIG_LCD */
47 #endif /* CONFIG_SPL_BUILD */
48
49 /* Clock Defines */
50 #define V_OSCK                          24000000  /* Clock output from T2 */
51 #define V_SCLK                          V_OSCK
52
53 /*
54  * Memory configuration options
55  */
56 #define CONFIG_SYS_SDRAM_DDR3
57 #define CONFIG_NR_DRAM_BANKS            1               /*  1 bank of SDRAM */
58 #define PHYS_SDRAM_1                    0x80000000      /* SDRAM Bank #1 */
59 #define CONFIG_MAX_RAM_BANK_SIZE        SZ_1G
60
61 #define CONFIG_STACKSIZE                SZ_64K
62 #define CONFIG_SYS_MALLOC_LEN           SZ_4M
63
64 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + SZ_64M)
65 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + SZ_8M)
66
67 #define CONFIG_SYS_CACHELINE_SIZE       64
68
69 /*
70  * U-Boot general configurations
71  */
72 #define CONFIG_SYS_LONGHELP
73 #define CONFIG_SYS_PROMPT               "TX48 U-Boot > "
74 #define CONFIG_SYS_CBSIZE               2048    /* Console I/O buffer size */
75 #define CONFIG_SYS_PBSIZE \
76         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
77                                                 /* Print buffer size */
78 #define CONFIG_SYS_MAXARGS              256     /* Max number of command args */
79 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
80                                                 /* Boot argument buffer size */
81 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
82 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
83 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
84
85 #define CONFIG_SYS_64BIT_VSPRINTF
86 #define CONFIG_SYS_NO_FLASH
87
88 /*
89  * Flattened Device Tree (FDT) support
90 */
91 #define CONFIG_OF_LIBFDT
92 #define CONFIG_OF_BOARD_SETUP
93 #define CONFIG_SYS_FDT_ADDR             (PHYS_SDRAM_1 + SZ_16M)
94
95 /*
96  * Boot Linux
97  */
98 #define xstr(s)                         str(s)
99 #define str(s)                          #s
100 #define __pfx(x, s)                     (x##s)
101 #define _pfx(x, s)                      __pfx(x, s)
102
103 #define CONFIG_CMDLINE_TAG
104 #define CONFIG_SETUP_MEMORY_TAGS
105 #define CONFIG_BOOTDELAY                3
106 #define CONFIG_ZERO_BOOTDELAY_CHECK
107 #define CONFIG_SYS_AUTOLOAD             "no"
108 #define CONFIG_BOOTFILE                 "uImage"
109 #define CONFIG_BOOTARGS                 "init=/linuxrc console=ttyO0,115200 ro debug panic=1"
110 #define CONFIG_BOOTCOMMAND              "run bootcmd_${boot_mode} bootm_cmd"
111 #define CONFIG_LOADADDR                 83000000
112 #define CONFIG_SYS_LOAD_ADDR            _pfx(0x, CONFIG_LOADADDR)
113 #define CONFIG_U_BOOT_IMG_SIZE          SZ_1M
114 #define CONFIG_HW_WATCHDOG
115
116 /*
117  * Extra Environment Settings
118  */
119 #define CONFIG_SYS_CPU_CLK_STR          xstr(CONFIG_SYS_MPU_CLK)
120
121 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
122         "autostart=no\0"                                                \
123         "baseboard=stk5-v3\0"                                           \
124         "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}"  \
125         " root=/dev/mtdblock4 rootfstype=jffs2\0"                       \
126         "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}"    \
127         " root=/dev/mmcblk0p2 rootwait\0"                               \
128         "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}"    \
129         " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock"        \
130         " ip=dhcp\0"                                                    \
131         "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}"  \
132         " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0"           \
133         "bootcmd_jffs2=set autostart no;run bootargs_jffs2"             \
134         ";nboot linux\0"                                                \
135         "bootcmd_mmc=set autostart no;run bootargs_mmc"                 \
136         ";fatload mmc 0 ${loadaddr} uImage\0"                           \
137         "bootcmd_nand=set autostart no;run bootargs_ubifs"              \
138         ";nboot linux\0"                                                \
139         "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs"   \
140         ";dhcp\0"                                                       \
141         "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"                    \
142         "boot_mode=nand\0"                                              \
143         "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0"                          \
144         "default_bootargs=set bootargs " CONFIG_BOOTARGS                \
145         " ${append_bootargs}\0"                                         \
146         "fdtaddr=81000000\0"                                            \
147         "fdtsave=fdt resize;nand erase.part dtb"                                        \
148         ";nand write ${fdtaddr} dtb ${fdtsize}\0"                       \
149         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
150         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
151         "nfsroot=/tftpboot/rootfs\0"                                    \
152         "otg_mode=device\0"                                             \
153         "touchpanel=tsc2007\0"                                          \
154         "video_mode=VGA\0"
155
156 #define MTD_NAME                        "omap2-nand.0"
157 #define MTDIDS_DEFAULT                  "nand0=" MTD_NAME
158 #define CONFIG_FDT_FIXUP_PARTITIONS
159
160 /*
161  * U-Boot Commands
162  */
163 #include <config_cmd_default.h>
164 #define CONFIG_CMD_CACHE
165 #define CONFIG_CMD_MMC
166 #define CONFIG_CMD_NAND
167 #define CONFIG_CMD_MTDPARTS
168 #define CONFIG_CMD_BOOTCE
169 #define CONFIG_CMD_TIME
170 #define CONFIG_CMD_MEMTEST
171
172 /*
173  * Serial Driver
174  */
175 #define CONFIG_SYS_NS16550
176 #define CONFIG_SYS_NS16550_SERIAL
177 #define CONFIG_SYS_NS16550_MEM32
178 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
179 #define CONFIG_SYS_NS16550_CLK          48000000
180 #define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
181 #define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
182 #define CONFIG_SYS_NS16550_COM6         0x481aa000      /* UART5 */
183
184 #define CONFIG_SYS_NS16550_COM3         0x481aa000      /* UART2 */
185 #define CONFIG_SYS_NS16550_COM4         0x481aa000      /* UART3 */
186 #define CONFIG_SYS_NS16550_COM5         0x481aa000      /* UART4 */
187 #define CONFIG_CONS_INDEX               1               /* one based! */
188 #define CONFIG_BAUDRATE                 115200          /* Default baud rate */
189 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, }
190 #define CONFIG_SYS_CONSOLE_INFO_QUIET
191
192 /*
193  * Ethernet Driver
194  */
195 #ifdef CONFIG_CMD_NET
196 #define CONFIG_DRIVER_TI_CPSW
197 #define CONFIG_NET_MULTI
198 #define CONFIG_PHY_GIGE
199 #define CONFIG_PHY_SMSC
200 #define CONFIG_PHYLIB
201 #define CONFIG_MII
202 #define CONFIG_CMD_MII
203 #define CONFIG_CMD_DHCP
204 #define CONFIG_CMD_PING
205 /* Add for working with "strict" DHCP server */
206 #define CONFIG_BOOTP_SUBNETMASK
207 #define CONFIG_BOOTP_GATEWAY
208 #define CONFIG_BOOTP_DNS
209 #define CONFIG_BOOTP_DNS2
210 #endif
211
212 /*
213  * NAND flash driver
214  */
215 #ifdef CONFIG_CMD_NAND
216 #define CONFIG_MTD_DEVICE
217 #define CONFIG_ENV_IS_IN_NAND
218 #define CONFIG_NAND_OMAP_GPMC
219 #ifndef CONFIG_SPL_BUILD
220 #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
221 #endif
222 #define GPMC_NAND_ECC_LP_x8_LAYOUT
223 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL  GPMC_NAND_HW_ECC_LAYOUT
224 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
225 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
226 #define CONFIG_SYS_NAND_OOBSIZE         64
227 #define CONFIG_SYS_NAND_ECCSIZE         512
228 #define CONFIG_SYS_NAND_ECCBYTES        14
229 #define CONFIG_CMD_NAND_TRIMFFS
230 #define CONFIG_SYS_NAND_MAX_CHIPS       1
231 #define CONFIG_SYS_NAND_MAXBAD          20 /* Max. number of bad blocks guaranteed by manufacturer */
232 #define CONFIG_SYS_MAX_NAND_DEVICE      1
233 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
234 #define CONFIG_SYS_NAND_USE_FLASH_BBT
235 #ifdef CONFIG_ENV_IS_IN_NAND
236 #define CONFIG_ENV_OVERWRITE
237 #define CONFIG_ENV_OFFSET               (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
238 #define CONFIG_ENV_SIZE                 SZ_128K
239 #define CONFIG_ENV_RANGE                0x60000
240 #endif /* CONFIG_ENV_IS_IN_NAND */
241 #define CONFIG_SYS_NAND_BASE            0x00100000
242 #define CONFIG_SYS_NAND_SIZE            SZ_128M
243 #define NAND_BASE                       CONFIG_SYS_NAND_BASE
244 #endif /* CONFIG_CMD_NAND */
245
246 /*
247  * MMC Driver
248  */
249 #ifdef CONFIG_CMD_MMC
250 #ifndef CONFIG_ENV_IS_IN_NAND
251 #define CONFIG_ENV_IS_IN_MMC
252 #endif
253 #define CONFIG_MMC
254 #define CONFIG_GENERIC_MMC
255 #define CONFIG_OMAP_HSMMC
256 #define CONFIG_OMAP_MMC_DEV_1
257
258 #define CONFIG_DOS_PARTITION
259 #define CONFIG_CMD_FAT
260 #define CONFIG_FAT_WRITE
261 #define CONFIG_CMD_EXT2
262
263 /*
264  * Environments on MMC
265  */
266 #ifdef CONFIG_ENV_IS_IN_MMC
267 #define CONFIG_SYS_MMC_ENV_DEV          0
268 #define CONFIG_ENV_OVERWRITE
269 /* Associated with the MMC layout defined in mmcops.c */
270 #define CONFIG_ENV_OFFSET               SZ_1K
271 #define CONFIG_ENV_SIZE                 (SZ_128K - CONFIG_ENV_OFFSET)
272 #define CONFIG_DYNAMIC_MMC_DEVNO
273 #endif /* CONFIG_ENV_IS_IN_MMC */
274 #endif /* CONFIG_CMD_MMC */
275
276 #ifdef CONFIG_ENV_OFFSET_REDUND
277 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
278         "128k(u-boot-spl),"                                             \
279         "1m(u-boot),"                                                   \
280         xstr(CONFIG_ENV_RANGE)                                          \
281         "(env),"                                                        \
282         xstr(CONFIG_ENV_RANGE)                                          \
283         "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
284 #else
285 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
286         "128k(u-boot-spl),"                                             \
287         "1m(u-boot),"                                                   \
288         xstr(CONFIG_ENV_RANGE)                                          \
289         "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
290 #endif
291
292 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
293 #define SRAM0_SIZE                      SZ_64K
294 #define OCMC_SRAM_BASE                  0x40300000
295 #define CONFIG_SPL_STACK                (OCMC_SRAM_BASE + 0xb800)
296 #define CONFIG_SYS_INIT_SP_ADDR         (PHYS_SDRAM_1 + SZ_32K)
297
298  /* Platform/Board specific defs */
299 #define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
300 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
301
302 /* Defines for SPL */
303 #define CONFIG_SPL
304 #define CONFIG_SPL_FRAMEWORK
305 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
306 #define CONFIG_SPL_GPIO_SUPPORT
307 #ifdef CONFIG_NAND_OMAP_GPMC
308 #define CONFIG_SPL_NAND_SUPPORT
309 #define CONFIG_SPL_NAND_DRIVERS
310 #define CONFIG_SPL_NAND_BASE
311 #define CONFIG_SPL_NAND_ECC
312 #define CONFIG_SPL_NAND_AM33XX_BCH
313 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
314 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE /   \
315                                         CONFIG_SYS_NAND_PAGE_SIZE)
316 #define CONFIG_SYS_NAND_BLOCK_SIZE      SZ_128K
317 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
318 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
319                                          10, 11, 12, 13, 14, 15, 16, 17, \
320                                          18, 19, 20, 21, 22, 23, 24, 25, \
321                                          26, 27, 28, 29, 30, 31, 32, 33, \
322                                          34, 35, 36, 37, 38, 39, 40, 41, \
323                                          42, 43, 44, 45, 46, 47, 48, 49, \
324                                          50, 51, 52, 53, 54, 55, 56, 57, }
325 #endif
326
327 #define CONFIG_SPL_BSS_START_ADDR       PHYS_SDRAM_1
328 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_512K
329
330 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
331
332 #define CONFIG_SPL_LIBCOMMON_SUPPORT
333 #define CONFIG_SPL_LIBGENERIC_SUPPORT
334 #define CONFIG_SPL_SERIAL_SUPPORT
335 #define CONFIG_SPL_YMODEM_SUPPORT
336 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
337
338 /*
339  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
340  * 64 bytes before this address should be set aside for u-boot.img's
341  * header. That is 0x800FFFC0--0x80100000 should not be used for any
342  * other needs.
343  */
344 #define CONFIG_SYS_SPL_MALLOC_START     (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
345 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
346
347 #endif  /* __CONFIG_H */