2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX51 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX51 board - SoC configuration
19 #define CONFIG_SYS_MX5_IOMUX_V3
20 #define CONFIG_MXC_GPIO /* GPIO control */
21 #define CONFIG_SYS_MX5_HCLK 24000000
22 #define CONFIG_SYS_DDR_CLKSEL 0
23 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
24 #define CONFIG_SHOW_ACTIVITY
25 #define CONFIG_DISPLAY_BOARDINFO
26 #define CONFIG_BOARD_LATE_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
29 #if CONFIG_SYS_CPU_CLK == 600
30 #define TX51_MOD_PREFIX "6"
31 #elif CONFIG_SYS_CPU_CLK == 800
32 #define TX51_MOD_PREFIX "8"
33 #define CONFIG_MX51_PLL_ERRATA
35 #error Invalid CPU clock
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_IPUV3
44 #define CONFIG_IPUV3_CLK 200000000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
52 * Memory configurations
54 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
55 #define PHYS_SDRAM_1_SIZE SZ_128M
56 #if CONFIG_NR_DRAM_BANKS > 1
57 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
58 #define PHYS_SDRAM_2_SIZE SZ_128M
60 #define TX51_MOD_SUFFIX "0"
62 #define CONFIG_STACKSIZE SZ_128K
63 #define CONFIG_SYS_MALLOC_LEN SZ_8M
64 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
65 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
66 #if CONFIG_SYS_SDRAM_CLK == 200
67 #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
68 #define TX51_MOD_SUFFIX "1"
69 #elif CONFIG_SYS_SDRAM_CLK == 166
70 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
71 #ifndef TX51_MOD_SUFFIX
72 #define TX51_MOD_SUFFIX "2"
75 #error Invalid SDRAM clock
79 * U-Boot general configurations
81 #define CONFIG_SYS_LONGHELP
82 #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
83 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
84 #define CONFIG_SYS_PBSIZE \
85 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
86 /* Print buffer size */
87 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
88 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
89 /* Boot argument buffer size */
90 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
91 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
92 #define CONFIG_CMDLINE_EDITING /* Command history etc */
94 #define CONFIG_SYS_64BIT_VSPRINTF
95 #define CONFIG_SYS_NO_FLASH
98 * Flattened Device Tree (FDT) support
100 #define CONFIG_OF_LIBFDT
101 #define CONFIG_OF_BOARD_SETUP
102 #define CONFIG_DEFAULT_DEVICE_TREE tx51
103 #define CONFIG_ARCH_DEVICE_TREE mx51
104 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
109 #define xstr(s) str(s)
111 #define __pfx(x, s) (x##s)
112 #define _pfx(x, s) __pfx(x, s)
114 #define CONFIG_CMDLINE_TAG
115 #define CONFIG_SETUP_MEMORY_TAGS
116 #define CONFIG_BOOTDELAY 3
117 #define CONFIG_ZERO_BOOTDELAY_CHECK
118 #define CONFIG_SYS_AUTOLOAD "no"
119 #define CONFIG_BOOTFILE "uImage"
120 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
121 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
122 #define CONFIG_LOADADDR 94000000
123 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
124 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
125 #define CONFIG_HW_WATCHDOG
130 #define CONFIG_EXTRA_ENV_SETTINGS \
132 "baseboard=stk5-v3\0" \
133 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
134 " root=/dev/mmcblk0p3 rootwait\0" \
135 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
136 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
137 "nfsroot=/tftpboot/rootfs\0" \
138 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
139 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
140 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
141 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
142 "bootcmd_nand=set autostart no;run bootargs_nand;" \
143 "nboot linux;run bootm_cmd\0" \
144 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
146 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
147 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
148 " ${append_bootargs}\0" \
149 "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
150 "fdtaddr=91000000\0" \
151 "mtdids=" MTDIDS_DEFAULT "\0" \
152 "mtdparts=" MTDPARTS_DEFAULT "\0" \
153 "otg_mode=device\0" \
154 "touchpanel=tsc2007\0" \
157 #define MTD_NAME "mxc_nand"
158 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
159 #define CONFIG_FDT_FIXUP_PARTITIONS
164 #include <config_cmd_default.h>
165 #define CONFIG_CMD_CACHE
166 #define CONFIG_CMD_MMC
167 #define CONFIG_CMD_NAND
168 #define CONFIG_CMD_MTDPARTS
169 #define CONFIG_CMD_BOOTCE
170 #define CONFIG_CMD_TIME
171 #define CONFIG_CMD_MEMTEST
176 #define CONFIG_MXC_UART
177 #define CONFIG_MXC_UART_BASE UART1_BASE
178 #define CONFIG_MXC_GPIO
179 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
180 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
181 #define CONFIG_SYS_CONSOLE_INFO_QUIET
186 #define CONFIG_FEC_MXC
187 #ifdef CONFIG_FEC_MXC
188 #define IMX_FEC_BASE FEC_BASE_ADDR
189 #define CONFIG_FEC_MXC_PHYADDR 0x1f
190 #define CONFIG_PHYLIB
191 #define CONFIG_PHY_SMSC
193 #define CONFIG_FEC_XCV_TYPE MII100
194 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
195 #define CONFIG_CMD_MII
196 #define CONFIG_CMD_DHCP
197 #define CONFIG_CMD_PING
198 /* Add for working with "strict" DHCP server */
199 #define CONFIG_BOOTP_SUBNETMASK
200 #define CONFIG_BOOTP_GATEWAY
201 #define CONFIG_BOOTP_DNS
207 #ifdef CONFIG_CMD_NAND
208 #define CONFIG_MTD_DEVICE
209 #define CONFIG_ENV_IS_IN_NAND
210 #define CONFIG_NAND_MXC
211 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
212 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
213 #define CONFIG_MXC_NAND_HWECC
214 #define CONFIG_CMD_NAND_TRIMFFS
215 #define CONFIG_SYS_MAX_FLASH_SECT 1024
216 #define CONFIG_SYS_MAX_FLASH_BANKS 1
217 #define CONFIG_SYS_NAND_MAX_CHIPS 1
218 #define CONFIG_SYS_MAX_NAND_DEVICE 1
219 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
220 #define CONFIG_SYS_NAND_USE_FLASH_BBT
221 #ifdef CONFIG_ENV_IS_IN_NAND
222 #define CONFIG_ENV_OVERWRITE
223 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
224 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
225 #define CONFIG_ENV_RANGE 0x60000
227 #ifndef CONFIG_SYS_NO_FLASH
228 #define CONFIG_CMD_FLASH
229 #define CONFIG_SYS_NAND_BASE 0xa0000000
232 #define CONFIG_SYS_NAND_BASE 0x00000000
233 #define CONFIG_CMD_ROMUPDATE
235 #endif /* CONFIG_CMD_NAND */
240 #ifdef CONFIG_CMD_MMC
241 #ifndef CONFIG_ENV_IS_IN_NAND
242 #define CONFIG_ENV_IS_IN_MMC
245 #define CONFIG_GENERIC_MMC
246 #define CONFIG_FSL_ESDHC
247 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
248 #define CONFIG_SYS_FSL_ESDHC_NUM 2
250 #define CONFIG_DOS_PARTITION
251 #define CONFIG_CMD_FAT
252 #define CONFIG_CMD_EXT2
255 * Environments on MMC
257 #ifdef CONFIG_ENV_IS_IN_MMC
258 #define CONFIG_SYS_MMC_ENV_DEV 0
259 #define CONFIG_ENV_OVERWRITE
260 /* Associated with the MMC layout defined in mmcops.c */
261 #define CONFIG_ENV_OFFSET SZ_1K
262 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
263 #define CONFIG_DYNAMIC_MMC_DEVNO
264 #endif /* CONFIG_ENV_IS_IN_MMC */
265 #endif /* CONFIG_CMD_MMC */
267 #ifdef CONFIG_ENV_OFFSET_REDUND
268 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
270 xstr(CONFIG_ENV_RANGE) \
272 xstr(CONFIG_ENV_RANGE) \
273 "(env2),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
275 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
277 xstr(CONFIG_ENV_RANGE) \
278 "(env),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
281 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
282 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
283 GENERATED_GBL_DATA_SIZE)
285 #ifdef CONFIG_CMD_IIM
286 #define CONFIG_FSL_IIM
289 #endif /* __CONFIG_H */