2 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * Copyright 2008-2010, Freescale Semiconductor, Inc
7 * Based (loosely) on the Linux code
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <linux/list.h>
33 #define SD_VERSION_SD 0x20000
34 #define SD_VERSION_2 (SD_VERSION_SD | 0x20)
35 #define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
36 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
37 #define MMC_VERSION_MMC 0x10000
38 #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
39 #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
40 #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
41 #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
42 #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
43 #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
45 #define MMC_MODE_HS 0x001
46 #define MMC_MODE_HS_52MHz 0x010
47 #define MMC_MODE_4BIT 0x100
48 #define MMC_MODE_8BIT 0x200
49 #define EMMC_MODE_4BIT_DDR 0x400
50 #define EMMC_MODE_8BIT_DDR 0x800
52 #define SD_DATA_4BIT 0x00040000
54 #define IS_SD(x) (x->version & SD_VERSION_SD)
56 #define MMC_DATA_READ 1
57 #define MMC_DATA_WRITE 2
59 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */
60 #define UNUSABLE_ERR -17 /* Unusable Card */
61 #define COMM_ERR -18 /* Communications Error */
64 #define MMC_CMD_GO_IDLE_STATE 0
65 #define MMC_CMD_SEND_OP_COND 1
66 #define MMC_CMD_ALL_SEND_CID 2
67 #define MMC_CMD_SET_RELATIVE_ADDR 3
68 #define MMC_CMD_SET_DSR 4
69 #define MMC_CMD_SWITCH 6
70 #define MMC_CMD_SELECT_CARD 7
71 #define MMC_CMD_SEND_EXT_CSD 8
72 #define MMC_CMD_SEND_CSD 9
73 #define MMC_CMD_SEND_CID 10
74 #define MMC_CMD_STOP_TRANSMISSION 12
75 #define MMC_CMD_SEND_STATUS 13
76 #define MMC_CMD_SET_BLOCKLEN 16
77 #define MMC_CMD_READ_SINGLE_BLOCK 17
78 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
79 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
80 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
81 #define MMC_CMD_APP_CMD 55
83 #define SD_CMD_SEND_RELATIVE_ADDR 3
84 #define SD_CMD_SWITCH_FUNC 6
85 #define SD_CMD_SEND_IF_COND 8
86 #define SD_CMD_SELECT_PARTITION 43
88 #define SD_CMD_APP_SET_BUS_WIDTH 6
89 #define SD_CMD_APP_SEND_OP_COND 41
90 #define SD_CMD_APP_SEND_SCR 51
92 /* SCR definitions in different words */
93 #define SD_HIGHSPEED_BUSY 0x00020000
94 #define SD_HIGHSPEED_SUPPORTED 0x00020000
96 #define MMC_HS_TIMING 0x00000100
97 #define MMC_HS_52MHZ 0x2
98 #define EMMC_MODE_DDR_3V 0x4
99 #define OCR_BUSY 0x80000000
100 #define OCR_HCS 0x40000000
102 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
103 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
104 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
105 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
106 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
107 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
108 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
109 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
110 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
111 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
112 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
113 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
114 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
115 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
116 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
117 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
118 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
120 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
121 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
122 addressed by index which are
124 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
125 addressed by index, which are
127 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
129 #define SD_SWITCH_CHECK 0
130 #define SD_SWITCH_SWITCH 1
136 #define EXT_CSD_BOOT_BUS_WIDTH 177 /* RW */
137 #define EXT_CSD_BOOT_CONFIG 179 /* RW */
138 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
139 #define EXT_CSD_HS_TIMING 185 /* R/W */
140 #define EXT_CSD_CARD_TYPE 196 /* RO */
141 #define EXT_CSD_REV 192 /* RO */
142 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
143 #define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
146 * EXT_CSD field definitions
149 #define EXT_CSD_CMD_SET_NORMAL (1<<0)
150 #define EXT_CSD_CMD_SET_SECURE (1<<1)
151 #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
153 #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
154 #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
156 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
157 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
158 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
159 #define EXT_CSD_BUS_WIDTH_4_DDR 5 /* eMMC 4.4 in 4-bit DDR mode */
160 #define EXT_CSD_BUS_WIDTH_8_DDR 6 /* eMMC 4.4 in 8-bit DDR mode */
162 #define EXT_CSD_BOOT_BUS_WIDTH_1BIT 0
163 #define EXT_CSD_BOOT_BUS_WIDTH_4BIT 1
164 #define EXT_CSD_BOOT_BUS_WIDTH_8BIT 2
165 #define EXT_CSD_BOOT_BUS_WIDTH_DDR (1 << 4)
167 #define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3)
168 #define EXT_CSD_BOOT_PARTITION_DISABLE (0x0)
169 #define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3)
170 #define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3)
171 #define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3)
173 #define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7)
174 #define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0)
175 #define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1)
176 #define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2)
178 #define R1_ILLEGAL_COMMAND (1 << 22)
179 #define R1_APP_CMD (1 << 5)
181 #define MMC_RSP_PRESENT (1 << 0)
182 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
183 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
184 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
185 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
187 #define MMC_RSP_NONE (0)
188 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
189 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
191 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
192 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
193 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
194 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
195 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
196 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
217 u64 read_bl_partial:1,
218 write_blk_misalign:1,
237 u8 file_format_grp:1,
239 perm_write_protect:1,
258 const char *src; /* src buffers don't get written to */
266 struct list_head link;
287 #ifdef CONFIG_BOOT_PARTITION_ACCESS
291 block_dev_desc_t block_dev;
292 int (*send_cmd)(struct mmc *mmc,
293 struct mmc_cmd *cmd, struct mmc_data *data);
294 void (*set_ios)(struct mmc *mmc);
295 int (*init)(struct mmc *mmc);
298 int mmc_register(struct mmc *mmc);
299 int mmc_initialize(bd_t *bis);
300 int mmc_init(struct mmc *mmc);
301 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
302 struct mmc *find_mmc_device(int dev_num);
303 void print_mmc_devices(char separator);
304 #ifdef CONFIG_BOOT_PARTITION_ACCESS
305 int mmc_switch_partition(struct mmc *mmc, uint part, uint enable_boot);
306 int sd_switch_partition(struct mmc *mmc, uint part);
309 #ifndef CONFIG_GENERIC_MMC
310 int mmc_legacy_init(int verbose);