nand_spl/nand_boot.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24
  25 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  26
  27 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  28 /*
  29  * NAND command for small page NAND devices (512)
  30  */
  31 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  32 {
  33         struct nand_chip *this = mtd->priv;
  34         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  35
  36         if (this->dev_ready)
  37                 while (!this->dev_ready(mtd))
  38                         ;
  39         else
  40                 CONFIG_SYS_NAND_READ_DELAY;
  41
  42         /* Begin command latch cycle */
  43         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  44         /* Set ALE and clear CLE to start address cycle */
  45         /* Column address */
  46         this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  47         this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  48         this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
  49                        NAND_CTRL_ALE); /* A[24:17] */
  50 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  51         /* One more address cycle for devices > 32MiB */
  52         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
  53                        NAND_CTRL_ALE); /* A[28:25] */
  54 #endif
  55         /* Latch in address */
  56         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  57
  58         /*
  59          * Wait a while for the data to be ready
  60          */
  61         while (!this->dev_ready(mtd))
  62                 ;
  63
  64         return 0;
  65 }
  66 #else
  67 /*
  68  * NAND command for large page NAND devices (2k)
  69  */
  70 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  71 {
  72         struct nand_chip *this = mtd->priv;
  73         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  74         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  75                         unsigned int ctrl) = this->cmd_ctrl;
  76
  77         while (!this->dev_ready(mtd))
  78                 ;
  79
  80         /* Emulate NAND_CMD_READOOB */
  81         if (cmd == NAND_CMD_READOOB) {
  82                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  83                 cmd = NAND_CMD_READ0;
  84         }
  85
  86         /* Shift the offset from byte addressing to word addressing. */
  87         if (this->options & NAND_BUSWIDTH_16)
  88                 offs >>= 1;
  89
  90         /* Begin command latch cycle */
  91         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  92         /* Set ALE and clear CLE to start address cycle */
  93         /* Column address */
  94         hwctrl(mtd, offs & 0xff,
  95                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  96         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  97         /* Row address */
  98         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  99         hwctrl(mtd, ((page_addr >> 8) & 0xff),
 100                        NAND_CTRL_ALE); /* A[27:20] */
 101 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 102         /* One more address cycle for devices > 128MiB */
 103         hwctrl(mtd, (page_addr >> 16) & 0x0f,
 104                        NAND_CTRL_ALE); /* A[31:28] */
 105 #endif
 106         /* Latch in address */
 107         hwctrl(mtd, NAND_CMD_READSTART,
 108                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 109         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 110
 111         /*
 112          * Wait a while for the data to be ready
 113          */
 114         while (!this->dev_ready(mtd))
 115                 ;
 116
 117         return 0;
 118 }
 119 #endif
 120
 121 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 122 {
 123         struct nand_chip *this = mtd->priv;
 124
 125         nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 126
 127         /*
 128          * Read one byte
 129          */
 130         if (readb(this->IO_ADDR_R) != 0xff)
 131                 return 1;
 132
 133         return 0;
 134 }
 135
 136 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 137 {
 138         struct nand_chip *this = mtd->priv;
 139         u_char *ecc_calc;
 140         u_char *ecc_code;
 141         u_char *oob_data;
 142         int i;
 143         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 144         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 145         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 146         uint8_t *p = dst;
 147         int stat;
 148
 149         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 150
 151         /* No malloc available for now, just use some temporary locations
 152          * in SDRAM
 153          */
 154         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 155         ecc_code = ecc_calc + 0x100;
 156         oob_data = ecc_calc + 0x200;
 157
 158         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 159                 this->ecc.hwctl(mtd, NAND_ECC_READ);
 160                 this->read_buf(mtd, p, eccsize);
 161                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
 162         }
 163         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 164
 165         /* Pick the ECC bytes out of the oob data */
 166         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 167                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 168
 169         eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 170         p = dst;
 171
 172         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 173                 /* No chance to do something with the possible error message
 174                  * from correct_data(). We just hope that all possible errors
 175                  * are corrected by this routine.
 176                  */
 177                 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int nand_load(struct mtd_info *mtd, unsigned int offs,
 184                      unsigned int uboot_size, uchar *dst)
 185 {
 186         unsigned int block, lastblock;
 187         unsigned int page;
 188
 189         /*
 190          * offs has to be aligned to a page address!
 191          */
 192         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 193         lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 194         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 195
 196         while (block <= lastblock) {
 197                 if (!nand_is_bad_block(mtd, block)) {
 198                         /*
 199                          * Skip bad blocks
 200                          */
 201                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 202                                 nand_read_page(mtd, block, page, dst);
 203                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 204                                 page++;
 205                         }
 206
 207                         page = 0;
 208                 } else {
 209                         lastblock++;
 210                 }
 211
 212                 block++;
 213         }
 214
 215         return 0;
 216 }
 217
 218 /*
 219  * The main entry for NAND booting. It's necessary that SDRAM is already
 220  * configured and available since this code loads the main U-Boot image
 221  * from NAND into SDRAM and starts it from there.
 222  */
 223 void nand_boot(void)
 224 {
 225         struct nand_chip nand_chip;
 226         nand_info_t nand_info;
 227         int ret;
 228         __attribute__((noreturn)) void (*uboot)(void);
 229
 230         /*
 231          * Init board specific nand support
 232          */
 233         nand_chip.select_chip = NULL;
 234         nand_info.priv = &nand_chip;
 235         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
 236         nand_chip.dev_ready = NULL;     /* preset to NULL */
 237         nand_chip.options = 0;
 238         board_nand_init(&nand_chip);
 239
 240         if (nand_chip.select_chip)
 241                 nand_chip.select_chip(&nand_info, 0);
 242
 243         /*
 244          * Load U-Boot image from NAND into RAM
 245          */
 246         ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 247                         (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 248
 249 #ifdef CONFIG_NAND_ENV_DST
 250         nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 251                   (uchar *)CONFIG_NAND_ENV_DST);
 252
 253 #ifdef CONFIG_ENV_OFFSET_REDUND
 254         nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 255                   (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 256 #endif
 257 #endif
 258
 259         if (nand_chip.select_chip)
 260                 nand_chip.select_chip(&nand_info, -1);
 261
 262         /*
 263          * Jump to U-Boot image
 264          */
 265         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 266         (*uboot)();
 267 }