1 From 5f7373e548c7862364511891596a97f18b945978 Mon Sep 17 00:00:00 2001
2 From: Fred Fan <r01011@freescale.com>
3 Date: Mon, 23 Feb 2009 14:08:23 +0800
4 Subject: [PATCH] ENGR00104583 MX35 can not boot up kernel
6 uboot can not boot kernel.
7 There are no more messages excepts uncompression message.
8 The root cause is wrong romfile version offset.
10 Signed-off-by: Fred Fan <r01011@freescale.com>
12 board/freescale/mx35_3stack/lowlevel_init.S | 15 +++++++++++----
13 board/freescale/mx35_3stack/mx35_3stack.c | 10 ++++++----
14 drivers/net/smc911x.c | 2 ++
15 include/asm-arm/arch-mx35/mx35.h | 12 +++++++++++-
16 4 files changed, 30 insertions(+), 9 deletions(-)
18 diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S
19 index 0b47ef1..c255e98 100644
20 --- a/board/freescale/mx35_3stack/lowlevel_init.S
21 +++ b/board/freescale/mx35_3stack/lowlevel_init.S
23 ldr \tmp, =IIM_BASE_ADDR
24 ldr \ret, [\tmp, #IIM_SREV]
26 - moveq \tmp, #ROMPATCH_BASE_ADDR
27 - ldreq \ret, [\tmp, #ROMPATCH_REV]
28 + moveq \tmp, #ROMPATCH_REV
30 moveq \ret, \ret, lsl #4
31 addne \ret, \ret, #0x10
35 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
37 + /* Workaournd for TO1 DDR issue:WT*/
38 + check_soc_version r1, r2
39 + cmp r1, #CHIP_REV_2_0
40 + ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
42 + strlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
46 str r1, [r0, #L2_CACHE_INV_WAY_REG]
48 str r2, [r0, #CLKCTL_CCMR]
50 check_soc_version r1, r2
52 + cmp r1, #CHIP_REV_2_0
53 ldrhs r3, =CCM_MPLL_399_HZ
55 ldr r2, [r0, #CLKCTL_PDR0]
59 check_soc_version r3, r4
61 + cmp r1, #CHIP_REV_2_0
64 movne r3, #L2CC_BASE_ADDR
65 diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
66 index 7854f86..267e9f1 100644
67 --- a/board/freescale/mx35_3stack/mx35_3stack.c
68 +++ b/board/freescale/mx35_3stack/mx35_3stack.c
69 @@ -43,19 +43,20 @@ static inline void setup_soc_rev(void)
71 reg = __REG(IIM_BASE_ADDR + IIM_SREV);
73 - reg = __REG(ROMPATCH_BASE_ADDR + ROMPATCH_REV);
74 + reg = __REG(ROMPATCH_REV);
78 + reg += CHIP_REV_1_0;
79 system_rev = 0x35000 + (reg & 0xFF);
82 static inline void set_board_rev(int rev)
84 - system_rev |= (rev & 0xF) << 8;
86 + system_rev = (system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
89 -static inline int is_soc_rev(int rev)
90 +int is_soc_rev(int rev)
92 return (system_rev & 0xFF) - rev;
94 @@ -171,6 +172,7 @@ static inline int board_detect(void)
102 diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
103 index 5c00028..13cb6ea 100644
104 --- a/drivers/net/smc911x.c
105 +++ b/drivers/net/smc911x.c
106 @@ -711,3 +711,5 @@ int smc911x_initialize(u8 dev_num, int base_addr)
112 diff --git a/include/asm-arm/arch-mx35/mx35.h b/include/asm-arm/arch-mx35/mx35.h
113 index 2ed85d3..c96092c 100644
114 --- a/include/asm-arm/arch-mx35/mx35.h
115 +++ b/include/asm-arm/arch-mx35/mx35.h
117 #define FDO_PAGE_SPARE_VAL 0x8
118 #define NAND_BUF_NUM 8
120 +#define CHIP_REV_1_0 0x10
121 +#define CHIP_REV_2_0 0x20
123 +#define BOARD_REV_1_0 0x0
124 +#define BOARD_REV_2_0 0x1
126 #ifndef __ASSEMBLER__
129 @@ -239,12 +245,16 @@ MXC_UART_CLK,
130 #define NFMS_NF_DWIDTH 14
131 #define NFMS_NF_PG_SZ 8
134 extern unsigned int mxc_get_clock(enum mxc_clock clk);
135 +extern unsigned int get_board_rev(void);
136 +extern int is_soc_rev(int rev);
138 #define fixup_before_linux \
140 volatile unsigned long *l2cc_ctl = (unsigned long *)0x30000100;\
142 + if (is_soc_rev(CHIP_REV_2_0) < 0) \
145 #endif /* __ASSEMBLER__*/
146 #endif /* __ASM_ARCH_MX35_H */