patches/0013-ENGR00109851-Add-nand-driver-for-MX51-uboot.patch

   1 From 512c7938d979e2b0cdc9271c6745ef1d7a2cf213 Mon Sep 17 00:00:00 2001
   2 From: Jason <r64343@freescale.com>
   3 Date: Wed, 18 Mar 2009 18:24:24 +0800
   4 Subject: [PATCH] ENGR00109851 Add nand driver for MX51 uboot
   5
   6 Add nand driver for MX51 uboot
   7
   8 Signed-off-by:Jason Liu <r64343@freescale.com>
   9 ---
  10  drivers/mtd/nand/mxc_nand.c          |  461 +++++++++++++++++++---------------
  11  drivers/mtd/nand/nand_base.c         |    8 +-
  12  include/asm-arm/arch-mx35/mxc_nand.h |    1 -
  13  include/asm-arm/arch-mx51/mx51.h     |    8 -
  14  include/asm-arm/arch-mx51/mxc_nand.h |  396 +++++++++++++++++++++---------
  15  include/configs/mx51_3stack.h        |   14 +-
  16  include/linux/mtd/nand.h             |    4 +-
  17  7 files changed, 548 insertions(+), 344 deletions(-)
  18
  19 diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
  20 index 7e224b7..953131d 100644
  21 --- a/drivers/mtd/nand/mxc_nand.c
  22 +++ b/drivers/mtd/nand/mxc_nand.c
  23 @@ -15,7 +15,7 @@
  24  #include <malloc.h>
  25  #include <asm/io.h>
  26  #include <asm/errno.h>
  27 -#include <nand.h>
  28 +#include <linux/mtd/nand.h>
  29  #include <asm-arm/arch/mxc_nand.h>
  30
  31  struct nand_info {
  32 @@ -143,6 +143,96 @@ static void wait_op_done(int max_retries)
  33                 MTDDEBUG(MTD_DEBUG_LEVEL0, "wait: INT not set\n");
  34  }
  35
  36 +/*!
  37 + * This function sends an address (or partial address) to the
  38 + * NAND device.  The address is used to select the source/destination for
  39 + * a NAND command.
  40 + *
  41 + * @param       addr    address to be written to NFC.
  42 + * @param       useirq  True if IRQ should be used rather than polling
  43 + */
  44 +static void send_addr(u16 addr)
  45 +{
  46 +       MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x)\n", addr);
  47 +
  48 +       /* fill address */
  49 +       raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR);
  50 +
  51 +       /* clear status */
  52 +       ACK_OPS;
  53 +
  54 +       /* send out address */
  55 +       raw_write(NFC_ADDR, REG_NFC_OPS);
  56 +
  57 +       /* Wait for operation to complete */
  58 +       wait_op_done(TROP_US_DELAY);
  59 +}
  60 +
  61 +static void mxc_do_addr_cycle_auto(struct mtd_info *mtd, int column,
  62 +                                                       int page_addr)
  63 +{
  64 +#ifdef CONFIG_MXC_NFC_SP_AUTO
  65 +       if (page_addr != -1 && column != -1) {
  66 +               u32 mask = 0xFFFF;
  67 +               /* the column address */
  68 +               raw_write(column & mask, NFC_FLASH_ADDR0);
  69 +               raw_write((raw_read(NFC_FLASH_ADDR0) |
  70 +                          ((page_addr & mask) << 16)), NFC_FLASH_ADDR0);
  71 +               /* the row address */
  72 +               raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) |
  73 +                          ((page_addr & (mask << 16)) >> 16)),
  74 +                         NFC_FLASH_ADDR8);
  75 +       } else if (page_addr != -1) {
  76 +               raw_write(page_addr, NFC_FLASH_ADDR0);
  77 +       }
  78 +
  79 +       MTDDEBUG(MTD_DEBUG_LEVEL3,
  80 +             "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n",
  81 +             raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8));
  82 +#endif
  83 +}
  84 +
  85 +static void mxc_do_addr_cycle_atomic(struct mtd_info *mtd, int column,
  86 +                                                       int page_addr)
  87 +{
  88 +       struct nand_chip *this = mtd->priv;
  89 +       struct nand_info *info = this->priv;
  90 +
  91 +       u32 page_mask = info->page_mask;
  92 +
  93 +       if (column != -1) {
  94 +               send_addr(column & 0xFF);
  95 +               if (IS_2K_PAGE_NAND) {
  96 +                       /* another col addr cycle for 2k page */
  97 +                       send_addr((column >> 8) & 0xF);
  98 +               } else if (IS_4K_PAGE_NAND) {
  99 +                       /* another col addr cycle for 4k page */
 100 +                       send_addr((column >> 8) & 0x1F);
 101 +               }
 102 +       }
 103 +       if (page_addr != -1) {
 104 +               do {
 105 +                       send_addr(page_addr & 0xff);
 106 +                       page_mask >>= 8;
 107 +                       page_addr >>= 8;
 108 +               } while (page_mask != 0);
 109 +       }
 110 +}
 111 +
 112 +/*
 113 + * Function to perform the address cycles.
 114 + */
 115 +static void mxc_nand_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 116 +{
 117 +       struct nand_chip *this = mtd->priv;
 118 +       struct nand_info *info = this->priv;
 119 +
 120 +       if (info->auto_mode)
 121 +               mxc_do_addr_cycle_auto(mtd, column, page_addr);
 122 +       else
 123 +               mxc_do_addr_cycle_atomic(mtd, column, page_addr);
 124 +}
 125 +
 126  static void send_cmd_atomic(struct mtd_info *mtd, u16 cmd)
 127  {
 128         /* fill command */
 129 @@ -158,37 +248,42 @@ static void send_cmd_atomic(struct mtd_info *mtd, u16 cmd)
 130         wait_op_done(TROP_US_DELAY);
 131  }
 132
 133 -static void send_cmd_auto(struct mtd_info *mtd, u16 cmd)
 134 +/*
 135 + * Function to record the ECC corrected/uncorrected errors resulted
 136 + * after a page read. This NFC detects and corrects upto to 4 symbols
 137 + * of 9-bits each.
 138 + */
 139 +static int mxc_nand_ecc_status(struct mtd_info *mtd)
 140  {
 141 -#ifdef CONFIG_MXC_NFC_SP_AUTO
 142 -       switch (cmd) {
 143 -       case NAND_CMD_READ0:
 144 -       case NAND_CMD_READOOB:
 145 -               raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD);
 146 -               break;
 147 -       case NAND_CMD_SEQIN:
 148 -       case NAND_CMD_ERASE1:
 149 -               raw_write(cmd, REG_NFC_FLASH_CMD);
 150 -               break;
 151 -       case NAND_CMD_PAGEPROG:
 152 -       case NAND_CMD_ERASE2:
 153 -       case NAND_CMD_READSTART:
 154 -               raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT,
 155 -                         REG_NFC_FLASH_CMD);
 156 -               send_cmd_interleave(mtd, cmd);
 157 -               break;
 158 -       case NAND_CMD_READID:
 159 -               send_atomic_cmd(cmd);
 160 -               send_addr(0);
 161 -               break;
 162 -       case NAND_CMD_RESET:
 163 -               send_cmd_interleave(mtd, cmd);
 164 -       case NAND_CMD_STATUS:
 165 -               break;
 166 -       default:
 167 -               break;
 168 -       }
 169 -#endif
 170 +       u32 ecc_stat, err;
 171 +       int no_subpages = 1;
 172 +       int ret = 0;
 173 +       u8 ecc_bit_mask, err_limit;
 174 +       struct nand_chip *this = mtd->priv;
 175 +       struct nand_info *info = this->priv;
 176 +
 177 +       ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf);
 178 +       err_limit = (IS_4BIT_ECC ? 0x4 : 0x8);
 179 +
 180 +       no_subpages = mtd->writesize >> 9;
 181 +
 182 +       no_subpages /= info->num_of_intlv;
 183 +
 184 +       ecc_stat = GET_NFC_ECC_STATUS();
 185 +       do {
 186 +               err = ecc_stat & ecc_bit_mask;
 187 +               if (err > err_limit) {
 188 +                       printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 189 +                       return -1;
 190 +               } else {
 191 +                       ret += err;
 192 +               }
 193 +               ecc_stat >>= 4;
 194 +       } while (--no_subpages);
 195 +
 196 +       MTDDEBUG(MTD_DEBUG_LEVEL3, "%d Symbol Correctable RS-ECC Error\n", ret);
 197 +
 198 +       return ret;
 199  }
 200
 201  /*!
 202 @@ -199,14 +294,15 @@ static void send_cmd_auto(struct mtd_info *mtd, u16 cmd)
 203  static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 204  {
 205  #ifdef CONFIG_MXC_NFC_SP_AUTO
 206 -       u32 i;
 207 -       u32 j = num_of_intlv;
 208 +
 209         struct nand_chip *this = mtd->priv;
 210 +       struct nand_info *info = this->priv;
 211         u32 addr_low = raw_read(NFC_FLASH_ADDR0);
 212         u32 addr_high = raw_read(NFC_FLASH_ADDR8);
 213         u32 page_addr = addr_low >> 16 | addr_high << 16;
 214 -       u8 *dbuf = mtd->info.data_buf;
 215 -       u8 *obuf = mtd->info.oob_buf;
 216 +       u32 i, j = info->num_of_intlv;
 217 +       u8 *dbuf = info->data_buf;
 218 +       u8 *obuf = info->oob_buf;
 219         u32 dlen = mtd->writesize / j;
 220         u32 olen = mtd->oobsize / j;
 221
 222 @@ -218,9 +314,9 @@ static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 223         else
 224                 page_addr *= this->numchips;
 225
 226 -       for (i = 0; i < j; i++) {
 227 -               if (cmd == NAND_CMD_PAGEPROG) {
 228 -
 229 +       switch (cmd) {
 230 +       case NAND_CMD_PAGEPROG:
 231 +               for (i = 0; i < j; i++) {
 232                         /* reset addr cycle */
 233                         if (j > 1)
 234                                 mxc_nand_addr_cycle(mtd, 0, page_addr++);
 235 @@ -238,14 +334,16 @@ static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 236                         raw_write(NFC_AUTO_PROG, REG_NFC_OPS);
 237
 238                         /* wait auto_prog_done bit set */
 239 -                       if (i < j - 1) {
 240 -                               while (!
 241 -                                      (raw_read(REG_NFC_OPS_STAT) & 1 << 30))
 242 -                                       ;
 243 -                       } else {
 244 -                               wait_op_done(TROP_US_DELAY);
 245 -                       }
 246 -               } else if (cmd == NAND_CMD_READSTART) {
 247 +                       while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE))
 248 +                               ;
 249 +               }
 250 +
 251 +               wait_op_done(TROP_US_DELAY);
 252 +               while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB));
 253 +
 254 +               break;
 255 +       case NAND_CMD_READSTART:
 256 +               for (i = 0; i < j; i++) {
 257                         /* reset addr cycle */
 258                         if (j > 1)
 259                                 mxc_nand_addr_cycle(mtd, 0, page_addr++);
 260 @@ -265,18 +363,62 @@ static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 261                         /* update the value */
 262                         dbuf += dlen;
 263                         obuf += olen;
 264 -               } else if (cmd == NAND_CMD_ERASE2) {
 265 +               }
 266 +               break;
 267 +       case NAND_CMD_ERASE2:
 268 +               for (i = 0; i < j; i++) {
 269                         if (!i) {
 270                                 page_addr = addr_low;
 271                                 page_addr *= (j > 1 ? j : this->numchips);
 272                         }
 273                         mxc_nand_addr_cycle(mtd, -1, page_addr++);
 274 +                       raw_write(0, REG_NFC_OPS_STAT);
 275                         raw_write(NFC_AUTO_ERASE, REG_NFC_OPS);
 276                         wait_op_done(TROP_US_DELAY);
 277 -               } else if (cmd == NAND_CMD_RESET) {
 278 -                       NFC_SET_NFC_ACTIVE_CS(i);
 279 -                       send_atomic_cmd(cmd);
 280                 }
 281 +               break;
 282 +       case NAND_CMD_RESET:
 283 +               for (i = 0; i < j; i++) {
 284 +                       if (j > 1)
 285 +                               NFC_SET_NFC_ACTIVE_CS(i);
 286 +                       send_cmd_atomic(mtd, cmd);
 287 +               }
 288 +               break;
 289 +       default:
 290 +               break;
 291 +       }
 292 +#endif
 293 +}
 294 +
 295 +static void send_cmd_auto(struct mtd_info *mtd, u16 cmd)
 296 +{
 297 +#ifdef CONFIG_MXC_NFC_SP_AUTO
 298 +       switch (cmd) {
 299 +       case NAND_CMD_READ0:
 300 +       case NAND_CMD_READOOB:
 301 +               raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD);
 302 +               break;
 303 +       case NAND_CMD_SEQIN:
 304 +       case NAND_CMD_ERASE1:
 305 +               raw_write(cmd, REG_NFC_FLASH_CMD);
 306 +               break;
 307 +       case NAND_CMD_PAGEPROG:
 308 +       case NAND_CMD_ERASE2:
 309 +       case NAND_CMD_READSTART:
 310 +               raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT,
 311 +                         REG_NFC_FLASH_CMD);
 312 +               send_cmd_interleave(mtd, cmd);
 313 +               break;
 314 +       case NAND_CMD_READID:
 315 +               send_cmd_atomic(mtd, cmd);
 316 +               send_addr(0);
 317 +               break;
 318 +       case NAND_CMD_RESET:
 319 +               send_cmd_interleave(mtd, cmd);
 320 +       case NAND_CMD_STATUS:
 321 +               break;
 322 +       default:
 323 +               break;
 324         }
 325  #endif
 326  }
 327 @@ -299,32 +441,7 @@ static void send_cmd(struct mtd_info *mtd, u16 cmd)
 328         else
 329                 send_cmd_atomic(mtd, cmd);
 330
 331 -       MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd);
 332 -}
 333 -
 334 -/*!
 335 - * This function sends an address (or partial address) to the
 336 - * NAND device.  The address is used to select the source/destination for
 337 - * a NAND command.
 338 - *
 339 - * @param       addr    address to be written to NFC.
 340 - * @param       useirq  True if IRQ should be used rather than polling
 341 - */
 342 -static void send_addr(u16 addr)
 343 -{
 344 -       MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr);
 345 -
 346 -       /* fill address */
 347 -       raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR);
 348 -
 349 -       /* clear status */
 350 -       ACK_OPS;
 351 -
 352 -       /* send out address */
 353 -       raw_write(NFC_ADDR, REG_NFC_OPS);
 354 -
 355 -       /* Wait for operation to complete */
 356 -       wait_op_done(TROP_US_DELAY);
 357 +       MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x)\n", cmd);
 358  }
 359
 360  /*!
 361 @@ -420,7 +537,8 @@ static u16 mxc_do_status_auto(struct mtd_info *mtd)
 362                 /* set ative cs */
 363                 NFC_SET_NFC_ACTIVE_CS(i);
 364
 365 -               raw_write(NFC_AUTO_STATE, REG_NFC_OPS);
 366 +               /* clear status */
 367 +               ACK_OPS;
 368
 369                 /* FIXME, NFC Auto erase may have
 370                  * problem, have to pollingit until
 371 @@ -428,6 +546,12 @@ static u16 mxc_do_status_auto(struct mtd_info *mtd)
 372                  * it may get error
 373                  */
 374                 do {
 375 +                       raw_write(NFC_AUTO_STATE, REG_NFC_OPS);
 376 +               #ifdef CONFIG_MX51
 377 +                       /* mx51to2 NFC need wait the op done */
 378 +                       if (is_soc_rev(CHIP_REV_2_0) == 0)
 379 +                               wait_op_done(TROP_US_DELAY);
 380 +               #endif
 381                         status = (raw_read(NFC_CONFIG1) & mask) >> 16;
 382                 } while ((status & NAND_STATUS_READY) == 0);
 383
 384 @@ -491,44 +615,6 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 385  }
 386
 387  /*
 388 - * Function to record the ECC corrected/uncorrected errors resulted
 389 - * after a page read. This NFC detects and corrects upto to 4 symbols
 390 - * of 9-bits each.
 391 - */
 392 -static int mxc_nand_ecc_status(struct mtd_info *mtd)
 393 -{
 394 -       u32 ecc_stat, err;
 395 -       int no_subpages = 1;
 396 -       int ret = 0;
 397 -       u8 ecc_bit_mask, err_limit;
 398 -       struct nand_chip *this = mtd->priv;
 399 -       struct nand_info *info = this->priv;
 400 -
 401 -       ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf);
 402 -       err_limit = (IS_4BIT_ECC ? 0x4 : 0x8);
 403 -
 404 -       no_subpages = mtd->writesize >> 9;
 405 -
 406 -       no_subpages /= info->num_of_intlv;
 407 -
 408 -       ecc_stat = GET_NFC_ECC_STATUS();
 409 -       do {
 410 -               err = ecc_stat & ecc_bit_mask;
 411 -               if (err > err_limit) {
 412 -                       printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 413 -                       return -1;
 414 -               } else {
 415 -                       ret += err;
 416 -               }
 417 -               ecc_stat >>= 4;
 418 -       } while (--no_subpages);
 419 -
 420 -       MTDDEBUG(MTD_DEBUG_LEVEL3, "%d Symbol Correctable RS-ECC Error\n", ret);
 421 -
 422 -       return ret;
 423 -}
 424 -
 425 -/*
 426   * Function to correct the detected errors. This NFC corrects all the errors
 427   * detected. So this function just return 0.
 428   */
 429 @@ -645,25 +731,6 @@ static u16 mxc_nand_read_word(struct mtd_info *mtd)
 430  }
 431
 432  /*!
 433 - * This function reads byte from the NAND Flash
 434 - *
 435 - * @param     mtd     MTD structure for the NAND Flash
 436 - *
 437 - * @return    data read from the NAND Flash
 438 - */
 439 -static u_char mxc_nand_read_byte16(struct mtd_info *mtd)
 440 -{
 441 -       struct nand_chip *this = mtd->priv;
 442 -       struct nand_info *info = this->priv;
 443 -
 444 -       /* Check for status request */
 445 -       if (info->status_req)
 446 -               return mxc_nand_get_status(mtd) & 0xFF;
 447 -
 448 -       return mxc_nand_read_word(mtd) & 0xFF;
 449 -}
 450 -
 451 -/*!
 452   * This function writes data of length \b len from buffer \b buf to the NAND
 453   * internal RAM buffer's MAIN area 0.
 454   *
 455 @@ -751,72 +818,6 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 456         }
 457  }
 458
 459 -static void mxc_do_addr_cycle_auto(struct mtd_info *mtd, int column,
 460 -                                                       int page_addr)
 461 -{
 462 -#ifdef CONFIG_MXC_NFC_SP_AUTO
 463 -       if (page_addr != -1 && column != -1) {
 464 -               u32 mask = 0xFFFF;
 465 -               /* the column address */
 466 -               raw_write(column & mask, NFC_FLASH_ADDR0);
 467 -               raw_write((raw_read(NFC_FLASH_ADDR0) |
 468 -                          ((page_addr & mask) << 16)), NFC_FLASH_ADDR0);
 469 -               /* the row address */
 470 -               raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) |
 471 -                          ((page_addr & (mask << 16)) >> 16)),
 472 -                         NFC_FLASH_ADDR8);
 473 -       } else if (page_addr != -1) {
 474 -               raw_write(page_addr, NFC_FLASH_ADDR0);
 475 -       }
 476 -
 477 -       MTDDEBUG(MTD_DEBUG_LEVEL3,
 478 -             "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n",
 479 -             raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8));
 480 -#endif
 481 -}
 482 -
 483 -static void mxc_do_addr_cycle_atomic(struct mtd_info *mtd, int column,
 484 -                                                       int page_addr)
 485 -{
 486 -       struct nand_chip *this = mtd->priv;
 487 -       struct nand_info *info = this->priv;
 488 -
 489 -       u32 page_mask = info->page_mask;
 490 -
 491 -       if (column != -1) {
 492 -               send_addr(column & 0xFF);
 493 -               if (IS_2K_PAGE_NAND) {
 494 -                       /* another col addr cycle for 2k page */
 495 -                       send_addr((column >> 8) & 0xF);
 496 -               } else if (IS_4K_PAGE_NAND) {
 497 -                       /* another col addr cycle for 4k page */
 498 -                       send_addr((column >> 8) & 0x1F);
 499 -               }
 500 -       }
 501 -       if (page_addr != -1) {
 502 -               do {
 503 -                       send_addr(page_addr & 0xff);
 504 -                       page_mask >>= 8;
 505 -                       page_addr >>= 8;
 506 -               } while (page_mask != 0);
 507 -       }
 508 -}
 509 -
 510 -
 511 -/*
 512 - * Function to perform the address cycles.
 513 - */
 514 -static void mxc_nand_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 515 -{
 516 -       struct nand_chip *this = mtd->priv;
 517 -       struct nand_info *info = this->priv;
 518 -
 519 -       if (info->auto_mode)
 520 -               mxc_do_addr_cycle_auto(mtd, column, page_addr);
 521 -       else
 522 -               mxc_do_addr_cycle_atomic(mtd, column, page_addr);
 523 -}
 524 -
 525  /*!
 526   * This function is used by the upper layer to write command to NAND Flash for
 527   * different operations to be carried out on NAND Flash
 528 @@ -933,6 +934,50 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 529         }
 530  }
 531
 532 +static int mxc_nand_read_oob(struct mtd_info *mtd,
 533 +                            struct nand_chip *chip, int page, int sndcmd)
 534 +{
 535 +       struct nand_chip *this = mtd->priv;
 536 +       struct nand_info *info = this->priv;
 537 +
 538 +       if (sndcmd) {
 539 +
 540 +               chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 541 +               sndcmd = 0;
 542 +       }
 543 +
 544 +       memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize);
 545 +
 546 +       return sndcmd;
 547 +}
 548 +
 549 +static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 550 +                             uint8_t *buf)
 551 +{
 552 +       struct nand_chip *this = mtd->priv;
 553 +       struct nand_info *info = this->priv;
 554 +
 555 +#ifndef CONFIG_MXC_NFC_SP_AUTO
 556 +       mxc_nand_ecc_status(mtd);
 557 +#endif
 558 +
 559 +       memcpy(buf, info->data_buf, mtd->writesize);
 560 +       memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize);
 561 +
 562 +       return 0;
 563 +}
 564 +
 565 +static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 566 +                               const uint8_t *buf)
 567 +{
 568 +       struct nand_chip *this = mtd->priv;
 569 +       struct nand_info *info = this->priv;
 570 +
 571 +       memcpy(info->data_buf, buf, mtd->writesize);
 572 +       memcpy(info->oob_buf, chip->oob_poi, mtd->oobsize);
 573 +
 574 +}
 575 +
 576  /* Define some generic bad / good block scan pattern which are used
 577   * while scanning a device for factory marked good / bad blocks. */
 578  static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 579 @@ -1014,7 +1059,7 @@ static int mxc_nand_scan_bbt(struct mtd_info *mtd)
 580                 this->bbt_erase_shift =
 581                 this->phys_erase_shift = ffs(mtd->erasesize) - 1;
 582                 this->chip_shift = ffs(this->chipsize) - 1;
 583 -               /*this->oob_poi = this->buffers->databuf + mtd->writesize;*/
 584 +               this->oob_poi = this->buffers->databuf + mtd->writesize;
 585         }
 586
 587         /* propagate ecc.layout to mtd_info */
 588 @@ -1055,6 +1100,9 @@ static void mxc_nfc_init(void)
 589
 590         /* Unlock Block Command for given address range */
 591         raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
 592 +
 593 +       /* Enable hw ecc */
 594 +       raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN);
 595  }
 596
 597  static int mxc_alloc_buf(struct nand_info *info)
 598 @@ -1080,12 +1128,6 @@ static int mxc_alloc_buf(struct nand_info *info)
 599         return err;
 600  }
 601
 602 -static void mxc_free_buf(struct nand_info *info)
 603 -{
 604 -       kfree(info->data_buf);
 605 -       kfree(info->oob_buf);
 606 -}
 607 -
 608  /*!
 609   * This function is called during the driver binding process.
 610   *
 611 @@ -1132,13 +1174,16 @@ int board_nand_init(struct nand_chip *nand)
 612         this->read_buf = mxc_nand_read_buf;
 613         this->verify_buf = mxc_nand_verify_buf;
 614         this->scan_bbt = mxc_nand_scan_bbt;
 615 +       this->ecc.read_page = mxc_nand_read_page;
 616 +       this->ecc.write_page = mxc_nand_write_page;
 617 +       this->ecc.read_oob = mxc_nand_read_oob;
 618         this->ecc.calculate = mxc_nand_calculate_ecc;
 619         this->ecc.correct = mxc_nand_correct_data;
 620         this->ecc.hwctl = mxc_nand_enable_hwecc;
 621 +       this->ecc.layout = &nand_hw_eccoob_512;
 622         this->ecc.mode = NAND_ECC_HW;
 623         this->ecc.bytes = 9;
 624         this->ecc.size = 512;
 625
 626         return 0;
 627 -
 628  }
 629 diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
 630 index 29c0d2d..0478740 100644
 631 --- a/drivers/mtd/nand/nand_base.c
 632 +++ b/drivers/mtd/nand/nand_base.c
 633 @@ -2529,7 +2529,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 634                 mtd->writesize = 1024 << (extid & 0x3);
 635                 extid >>= 2;
 636                 /* Calc oobsize */
 637 -               mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
 638 +               mtd->oobsize = (*maf_id == 0x2c && dev_id == 0xd5) ?
 639 +                       218 : (8 << (extid & 0x01)) * (mtd->writesize >> 9);
 640                 extid >>= 2;
 641                 /* Calc blocksize. Blocksize is multiples of 64KiB */
 642                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
 643 @@ -2866,10 +2867,9 @@ int nand_scan_tail(struct mtd_info *mtd)
 644         mtd->ecclayout = chip->ecc.layout;
 645
 646         /* Check, if we should skip the bad block table scan */
 647 -       if (chip->options & NAND_SKIP_BBTSCAN)
 648 -               chip->options |= NAND_BBT_SCANNED;
 649 +       chip->options |= NAND_BBT_SCANNED;
 650
 651 -       return 0;
 652 +       return chip->scan_bbt(mtd);
 653  }
 654
 655  /* module_text_address() isn't exported, and it's mostly a pointless
 656 diff --git a/include/asm-arm/arch-mx35/mxc_nand.h b/include/asm-arm/arch-mx35/mxc_nand.h
 657 index bc04c09..047b232 100644
 658 --- a/include/asm-arm/arch-mx35/mxc_nand.h
 659 +++ b/include/asm-arm/arch-mx35/mxc_nand.h
 660 @@ -33,7 +33,6 @@
 661
 662  #define NAND_PAGESIZE_2KB      2048
 663  #define NAND_PAGESIZE_4KB      4096
 664 -#define NAND_MAX_PAGESIZE      4096
 665
 666  /*
 667   * Addresses for NFC registers
 668 diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
 669 index d9d8ef7..566251b 100644
 670 --- a/include/asm-arm/arch-mx51/mx51.h
 671 +++ b/include/asm-arm/arch-mx51/mx51.h
 672 @@ -406,14 +406,6 @@ MXC_IPG_PERCLK,
 673  MXC_UART_CLK,
 674  };
 675
 676 -/*!
 677 - * NFMS bit in RCSR register for pagesize of nandflash
 678 - */
 679 -#define NFMS            (*((volatile u32 *)(CCM_BASE_ADDR+0x18)))
 680 -#define NFMS_BIT                8
 681 -#define NFMS_NF_DWIDTH          14
 682 -#define NFMS_NF_PG_SZ           8
 683 -
 684  extern unsigned int mxc_get_clock(enum mxc_clock clk);
 685  extern unsigned int get_board_rev(void);
 686  extern int is_soc_rev(int rev);
 687 diff --git a/include/asm-arm/arch-mx51/mxc_nand.h b/include/asm-arm/arch-mx51/mxc_nand.h
 688 index aad93d1..539d0fd 100644
 689 --- a/include/asm-arm/arch-mx51/mxc_nand.h
 690 +++ b/include/asm-arm/arch-mx51/mxc_nand.h
 691 @@ -12,7 +12,7 @@
 692   */
 693
 694  /*!
 695 - * @file mxc_nd2.h
 696 + * @file mxc_nand.h
 697   *
 698   * @brief This file contains the NAND Flash Controller register information.
 699   *
 700 @@ -25,99 +25,100 @@
 701
 702  #include <asm/arch/mx51.h>
 703
 704 -#define IS_2K_PAGE_NAND         ((mtd->oobblock / info->num_of_intlv) \
 705 +#define IS_2K_PAGE_NAND         ((mtd->writesize / info->num_of_intlv) \
 706                                                 == NAND_PAGESIZE_2KB)
 707 -#define IS_4K_PAGE_NAND         ((mtd->oobblock / info->num_of_intlv) \
 708 +#define IS_4K_PAGE_NAND         ((mtd->writesize / info->num_of_intlv) \
 709                                                 == NAND_PAGESIZE_4KB)
 710 -#define IS_LARGE_PAGE_NAND      ((mtd->oobblock / info->num_of_intlv) > 512)
 711 +#define IS_LARGE_PAGE_NAND      ((mtd->writesize / info->num_of_intlv) > 512)
 712 +
 713 +#define GET_NAND_OOB_SIZE      (mtd->oobsize / info->num_of_intlv)
 714
 715  #define NAND_PAGESIZE_2KB      2048
 716  #define NAND_PAGESIZE_4KB      4096
 717 -#define NAND_MAX_PAGESIZE      4096
 718
 719 -/*
 720 - * Addresses for NFC registers
 721 - */
 722 -#define NFC_REG_BASE                   (NFC_BASE_ADDR + 0x1000)
 723 -#define NFC_BUF_ADDR                   (NFC_REG_BASE + 0xE04)
 724 -#define NFC_FLASH_ADDR                 (NFC_REG_BASE + 0xE06)
 725 -#define NFC_FLASH_CMD                  (NFC_REG_BASE + 0xE08)
 726 -#define NFC_CONFIG                     (NFC_REG_BASE + 0xE0A)
 727 -#define NFC_ECC_STATUS_RESULT          (NFC_REG_BASE + 0xE0C)
 728 -#define NFC_SPAS                       (NFC_REG_BASE + 0xE10)
 729 -#define NFC_WRPROT                     (NFC_REG_BASE + 0xE12)
 730 -#define NFC_UNLOCKSTART_BLKADDR        (NFC_REG_BASE + 0xE20)
 731 -#define NFC_UNLOCKEND_BLKADDR          (NFC_REG_BASE + 0xE22)
 732 -#define NFC_CONFIG1                    (NFC_REG_BASE + 0xE1A)
 733 -#define NFC_CONFIG2                    (NFC_REG_BASE + 0xE1C)
 734 +#define NFC_AXI_BASE_ADDR              NFC_BASE_ADDR_AXI
 735 +#define NFC_IP_BASE_ADDR               NFC_BASE_ADDR
 736 +#define MXC_INT_NANDFC                 MXC_INT_NFC
 737 +#define CONFIG_MXC_NFC_SP_AUTO
 738 +#define NFC_FLASH_CMD                  (NFC_AXI_BASE_ADDR + 0x1E00)
 739 +#define NFC_FLASH_ADDR0                (NFC_AXI_BASE_ADDR + 0x1E04)
 740 +#define NFC_FLASH_ADDR8                        (NFC_AXI_BASE_ADDR + 0x1E24)
 741 +#define NFC_CONFIG1                    (NFC_AXI_BASE_ADDR + 0x1E34)
 742 +#define NFC_ECC_STATUS_RESULT          (NFC_AXI_BASE_ADDR + 0x1E38)
 743 +#define NFC_ECC_STATUS_SUM             (NFC_AXI_BASE_ADDR + 0x1E3C)
 744 +#define LAUNCH_NFC                     (NFC_AXI_BASE_ADDR + 0x1E40)
 745 +#define NFC_WRPROT                     (NFC_IP_BASE_ADDR + 0x00)
 746 +#define NFC_WRPROT_UNLOCK_BLK_ADD0     (NFC_IP_BASE_ADDR + 0x04)
 747 +#define NFC_CONFIG2                    (NFC_IP_BASE_ADDR + 0x24)
 748 +#define NFC_CONFIG3                    (NFC_IP_BASE_ADDR + 0x28)
 749 +#define NFC_IPC                                (NFC_IP_BASE_ADDR + 0x2C)
 750
 751  /*!
 752   * Addresses for NFC RAM BUFFER Main area 0
 753   */
 754 -#define MAIN_AREA0                     (u16 *)(NFC_BASE_ADDR + 0x000)
 755 -#define MAIN_AREA1                     (u16 *)(NFC_BASE_ADDR + 0x200)
 756 +#define MAIN_AREA0                     ((u16 *)(NFC_AXI_BASE_ADDR + 0x000))
 757 +#define MAIN_AREA1                     ((u16 *)(NFC_AXI_BASE_ADDR + 0x200))
 758
 759  /*!
 760   * Addresses for NFC SPARE BUFFER Spare area 0
 761   */
 762 -#define SPARE_AREA0                    (u16 *)(NFC_BASE_ADDR + 0x1000)
 763 +#define SPARE_AREA0                    ((u16 *)(NFC_AXI_BASE_ADDR + 0x1000))
 764  #define SPARE_LEN                      64
 765  #define SPARE_COUNT                    8
 766 -#define SPARE_SIZE                     (SPARE_LEN * SPARE_COUNT)
 767 +#define SPARE_SIZE                     (SPARE_LEN * SPARE_COUNT)
 768
 769 +#define NFC_SPAS_WIDTH 8
 770 +#define NFC_SPAS_SHIFT 16
 771
 772 -#define SPAS_SHIFT     (0)
 773 -#define SPAS_MASK      (0xFF00)
 774 -#define IS_4BIT_ECC    \
 775 -       ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0)
 776 +#define IS_4BIT_ECC \
 777 +( \
 778 +       is_soc_rev(CHIP_REV_2_0) == 0 ? \
 779 +               !((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) : \
 780 +               ((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) \
 781 +)
 782
 783  #define NFC_SET_SPAS(v)                        \
 784 -       raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \
 785 -       ((v<<SPAS_SHIFT))), \
 786 -       REG_NFC_SPAS)
 787 +       raw_write((((raw_read(NFC_CONFIG2) & \
 788 +       NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \
 789 +       NFC_CONFIG2)
 790
 791 -#define NFC_SET_ECC_MODE(v) \
 792 +#define NFC_SET_ECC_MODE(v)            \
 793  do { \
 794 -       if ((v) == NFC_SPAS_218)  { \
 795 -               raw_write((raw_read(REG_NFC_ECC_MODE) & \
 796 -               NFC_ECC_MODE_8), \
 797 -               REG_NFC_ECC_MODE); \
 798 +       if (is_soc_rev(CHIP_REV_2_0) == 0) { \
 799 +               if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
 800 +                       raw_write(((raw_read(NFC_CONFIG2) & \
 801 +                                       NFC_ECC_MODE_MASK) | \
 802 +                                       NFC_ECC_MODE_4), NFC_CONFIG2); \
 803 +               else \
 804 +                       raw_write(((raw_read(NFC_CONFIG2) & \
 805 +                                       NFC_ECC_MODE_MASK) & \
 806 +                                       NFC_ECC_MODE_8), NFC_CONFIG2); \
 807         } else { \
 808 -               raw_write((raw_read(REG_NFC_ECC_MODE) | \
 809 -               NFC_ECC_MODE_4), \
 810 -               REG_NFC_ECC_MODE); \
 811 -       } \
 812 -} while (0)
 813 -
 814 -#define GET_ECC_STATUS() \
 815 -       __raw_readl(REG_NFC_ECC_STATUS_RESULT);
 816 -
 817 -#define NFC_SET_NFMS(v)        \
 818 -do { \
 819 -       (NFMS |= (v)); \
 820 -       if (((v) & (1 << NFMS_NF_PG_SZ))) { \
 821 -               if (IS_2K_PAGE_NAND) { \
 822 -                       NFC_SET_SPAS(NFC_SPAS_64); \
 823 -               } else if (IS_4K_PAGE_NAND) { \
 824 -                       NFC_SET_SPAS(NFC_SPAS_128); \
 825 -               } else { \
 826 -                       NFC_SET_SPAS(NFC_SPAS_16); \
 827 -               } \
 828 -               NFC_SET_ECC_MODE(NFC_SPAS_128); \
 829 +               if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
 830 +                       raw_write(((raw_read(NFC_CONFIG2) & \
 831 +                                       NFC_ECC_MODE_MASK) & \
 832 +                                       NFC_ECC_MODE_8), NFC_CONFIG2); \
 833 +               else \
 834 +                       raw_write(((raw_read(NFC_CONFIG2) & \
 835 +                                       NFC_ECC_MODE_MASK) | \
 836 +                                       NFC_ECC_MODE_4), NFC_CONFIG2); \
 837         } \
 838  } while (0)
 839
 840 +#define WRITE_NFC_IP_REG(val, reg)                     \
 841 +       do {                                            \
 842 +               raw_write(NFC_IPC_CREQ, NFC_IPC);       \
 843 +               while (!((raw_read(NFC_IPC) & NFC_IPC_ACK)>>1)) \
 844 +                       ; \
 845 +               raw_write(val, reg);                    \
 846 +               raw_write(0, NFC_IPC);                  \
 847 +       } while (0)
 848
 849 -#define WRITE_NFC_IP_REG(val, reg) \
 850 -       raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
 851 -       REG_NFC_OPS_STAT)
 852 -
 853 -#define GET_NFC_ECC_STATUS() \
 854 -       raw_read(REG_NFC_ECC_STATUS_RESULT);
 855 +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT);
 856
 857  /*!
 858 - * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC
 859 - * Register for Specific operation
 860 + * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for
 861 + * Specific operation
 862   */
 863  #define NFC_CMD                        0x1
 864  #define NFC_ADDR                       0x2
 865 @@ -125,74 +126,241 @@ do { \
 866  #define NFC_OUTPUT                     0x8
 867  #define NFC_ID                         0x10
 868  #define NFC_STATUS                     0x20
 869 +#define NFC_AUTO_PROG                  0x40
 870 +#define NFC_AUTO_READ                  0x80
 871 +#define NFC_AUTO_ERASE                 0x200
 872 +#define NFC_COPY_BACK_0                        0x400
 873 +#define NFC_COPY_BACK_1                0x800
 874 +#define NFC_AUTO_STATE                 0x1000
 875 +
 876 +/* Bit Definitions for NFC_IPC*/
 877 +#define NFC_OPS_STAT                   (1 << 31)
 878 +#define NFC_OP_DONE                    (1 << 30)
 879 +#define NFC_RB                         (1 << 28)
 880 +#define NFC_PS_WIDTH                   2
 881 +#define NFC_PS_SHIFT                   0
 882 +#define NFC_PS_512                     0
 883 +#define NFC_PS_2K                      1
 884 +#define NFC_PS_4K                      2
 885 +
 886 +
 887 +#define NFC_ONE_CYCLE                  (1 << 2)
 888 +#define NFC_INT_MSK                    (1 << 15)
 889 +#define NFC_AUTO_PROG_DONE_MSK                 (1 << 14)
 890 +#define NFC_NUM_ADDR_PHASE1_WIDTH      2
 891 +#define NFC_NUM_ADDR_PHASE1_SHIFT      12
 892 +#define NFC_NUM_ADDR_PHASE0_WIDTH      1
 893 +#define NFC_NUM_ADDR_PHASE0_SHIFT      5
 894 +#define NFC_ONE_LESS_PHASE1            0
 895 +#define NFC_TWO_LESS_PHASE1            1
 896 +#define NFC_FLASH_ADDR_SHIFT           0
 897 +#define NFC_UNLOCK_END_ADDR_SHIFT      16
 898 +
 899 +/* Bit definition for NFC_CONFIGRATION_1 */
 900 +#define NFC_SP_EN                      (1 << 0)
 901 +#define NFC_CE                         (1 << 1)
 902 +#define NFC_RST                                (1 << 2)
 903 +#define NFC_ECC_EN                     (1 << 3)
 904
 905 -/* Bit Definitions */
 906 -#define NFC_OPS_STAT                   (1 << 15)
 907 -#define NFC_SP_EN                      (1 << 2)
 908 -#define NFC_ECC_EN                     (1 << 3)
 909 -#define NFC_INT_MSK                    (1 << 4)
 910 -#define NFC_BIG                        (1 << 5)
 911 -#define NFC_RST                        (1 << 6)
 912 -#define NFC_CE                         (1 << 7)
 913 -#define NFC_ONE_CYCLE                  (1 << 8)
 914 -#define NFC_BLS_LOCKED                 0
 915 -#define NFC_BLS_LOCKED_DEFAULT         1
 916 -#define NFC_BLS_UNLCOKED               2
 917 +#define NFC_FIELD_RESET(width, shift) (~(((1 << (width)) - 1) << (shift)))
 918 +
 919 +#define NFC_RBA_SHIFT                  4
 920 +#define NFC_RBA_WIDTH                  3
 921 +
 922 +#define NFC_ITERATION_SHIFT 8
 923 +#define NFC_ITERATION_WIDTH 4
 924 +#define NFC_ACTIVE_CS_SHIFT 12
 925 +#define NFC_ACTIVE_CS_WIDTH 3
 926 +/* bit definition for CONFIGRATION3 */
 927 +#define NFC_NO_SDMA                    (1 << 20)
 928 +#define NFC_FMP_SHIFT                  16
 929 +#define NFC_FMP_WIDTH                  4
 930 +#define NFC_RBB_MODE                   (1 << 15)
 931 +#define NFC_NUM_OF_DEVICES_SHIFT       12
 932 +#define NFC_NUM_OF_DEVICES_WIDTH       4
 933 +#define NFC_DMA_MODE_SHIFT             11
 934 +#define NFC_DMA_MODE_WIDTH             1
 935 +#define NFC_SBB_SHIFT                  8
 936 +#define NFC_SBB_WIDTH                  3
 937 +#define NFC_BIG                                (1 << 7)
 938 +#define NFC_SB2R_SHIFT                         4
 939 +#define NFC_SB2R_WIDTH                 3
 940 +#define NFC_FW_SHIFT                   3
 941 +#define NFC_FW_WIDTH                   1
 942 +#define NFC_TOO                                (1 << 2)
 943 +#define NFC_ADD_OP_SHIFT               0
 944 +#define NFC_ADD_OP_WIDTH               2
 945 +#define NFC_FW_8                       1
 946 +#define NFC_FW_16                      0
 947 +#define NFC_ST_CMD_SHITF               24
 948 +#define NFC_ST_CMD_WIDTH               8
 949 +
 950 +#define NFC_PPB_32                     (0 << 7)
 951 +#define NFC_PPB_64                     (1 << 7)
 952 +#define NFC_PPB_128                    (2 << 7)
 953 +#define NFC_PPB_256                    (3 << 7)
 954 +#define NFC_PPB_RESET                  (~(3 << 7))
 955 +
 956 +#define NFC_BLS_LOCKED                 (0 << 16)
 957 +#define NFC_BLS_LOCKED_DEFAULT         (1 << 16)
 958 +#define NFC_BLS_UNLCOKED               (2 << 16)
 959 +#define NFC_BLS_RESET                  (~(3 << 16))
 960  #define NFC_WPC_LOCK_TIGHT             1
 961  #define NFC_WPC_LOCK                   (1 << 1)
 962  #define NFC_WPC_UNLOCK                 (1 << 2)
 963 -#define NFC_FLASH_ADDR_SHIFT           0
 964 -#define NFC_UNLOCK_END_ADDR_SHIFT      0
 965 -
 966 -#define NFC_ECC_MODE_4                  (1<<0)
 967 -#define NFC_ECC_MODE_8                  (~(1<<0))
 968 -#define NFC_SPAS_16                     8
 969 -#define NFC_SPAS_64                     32
 970 -#define NFC_SPAS_128                    64
 971 -#define NFC_SPAS_218                    109
 972 -
 973 -/* NFC Register Mapping */
 974 -#define REG_NFC_OPS_STAT               NFC_CONFIG2
 975 -#define REG_NFC_INTRRUPT               NFC_CONFIG1
 976 -#define REG_NFC_FLASH_ADDR             NFC_FLASH_ADDR
 977 +#define NFC_WPC_RESET                  (~(7))
 978 +#define NFC_ECC_MODE_4                 (1 << 6)
 979 +#define NFC_ECC_MODE_8                 (~(1 << 6))
 980 +#define NFC_ECC_MODE_MASK              (~(1 << 6))
 981 +#define NFC_SPAS_16                    8
 982 +#define NFC_SPAS_64                    32
 983 +#define NFC_SPAS_128                   64
 984 +#define NFC_SPAS_112                   56
 985 +#define NFC_SPAS_218                   109
 986 +#define NFC_IPC_CREQ                   (1 << 0)
 987 +#define NFC_IPC_ACK                    (1 << 1)
 988 +
 989 +#define REG_NFC_OPS_STAT               NFC_IPC
 990 +#define REG_NFC_INTRRUPT               NFC_CONFIG2
 991 +#define REG_NFC_FLASH_ADDR             NFC_FLASH_ADDR0
 992  #define REG_NFC_FLASH_CMD              NFC_FLASH_CMD
 993 -#define REG_NFC_OPS                    NFC_CONFIG2
 994 -#define REG_NFC_SET_RBA                        NFC_BUF_ADDR
 995 -#define REG_NFC_ECC_EN                 NFC_CONFIG1
 996 -#define REG_NFC_ECC_STATUS_RESULT      NFC_ECC_STATUS_RESULT
 997 +#define REG_NFC_OPS                    LAUNCH_NFC
 998 +#define REG_NFC_SET_RBA                        NFC_CONFIG1
 999 +#define REG_NFC_RB                     NFC_IPC
1000 +#define REG_NFC_ECC_EN                 NFC_CONFIG2
1001 +#define REG_NFC_ECC_STATUS_RESULT      NFC_ECC_STATUS_RESULT
1002  #define REG_NFC_CE                     NFC_CONFIG1
1003 +#define REG_NFC_RST                    NFC_CONFIG1
1004 +#define REG_NFC_PPB                    NFC_CONFIG2
1005  #define REG_NFC_SP_EN                  NFC_CONFIG1
1006 -#define REG_NFC_BLS                    NFC_CONFIG
1007 +#define REG_NFC_BLS                    NFC_WRPROT
1008 +#define REG_UNLOCK_BLK_ADD0            NFC_WRPROT_UNLOCK_BLK_ADD0
1009 +#define REG_UNLOCK_BLK_ADD1            NFC_WRPROT_UNLOCK_BLK_ADD1
1010 +#define REG_UNLOCK_BLK_ADD2            NFC_WRPROT_UNLOCK_BLK_ADD2
1011 +#define REG_UNLOCK_BLK_ADD3            NFC_WRPROT_UNLOCK_BLK_ADD3
1012  #define REG_NFC_WPC                    NFC_WRPROT
1013 -#define REG_START_BLKADDR                      NFC_UNLOCKSTART_BLKADDR
1014 -#define REG_END_BLKADDR                        NFC_UNLOCKEND_BLKADDR
1015 -#define REG_NFC_RST                    NFC_CONFIG1
1016 -#define REG_NFC_ECC_MODE               NFC_CONFIG1
1017 -#define REG_NFC_SPAS                   NFC_SPAS
1018 +#define REG_NFC_ONE_CYCLE              NFC_CONFIG2
1019 +
1020 +/* NFC V3 Specific MACRO functions definitions */
1021 +#define raw_write(v, a)                __raw_writel(v, a)
1022 +#define raw_read(a)            __raw_readl(a)
1023 +
1024 +/* Explcit ack ops status (if any), before issue of any command  */
1025 +#define ACK_OPS        \
1026 +       raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
1027 +       REG_NFC_OPS_STAT);
1028 +
1029 +/* Set RBA buffer id*/
1030 +#define NFC_SET_RBA(val)       \
1031 +       raw_write((raw_read(REG_NFC_SET_RBA) & \
1032 +       (NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \
1033 +       ((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA);
1034 +
1035 +#define NFC_SET_PS(val)       \
1036 +       raw_write((raw_read(NFC_CONFIG2) & \
1037 +       (NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \
1038 +       ((val) << NFC_PS_SHIFT), NFC_CONFIG2);
1039 +
1040 +#define UNLOCK_ADDR(start_addr, end_addr)     \
1041 +{ \
1042 +       int i = 0; \
1043 +       for (; i < NAND_MAX_CHIPS; i++)  \
1044 +               raw_write(start_addr | \
1045 +               (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \
1046 +               REG_UNLOCK_BLK_ADD0 + (i << 2)); \
1047 +}
1048
1049 +#define NFC_SET_NFC_ACTIVE_CS(val) \
1050 +       raw_write((raw_read(NFC_CONFIG1) & \
1051 +       (NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \
1052 +       ((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1);
1053
1054 -/* NFC V1/V2 Specific MACRO functions definitions */
1055 +#define NFC_GET_MAXCHIP_SP()           8
1056
1057 -#define raw_write(v, a)                 __raw_writew(v, a)
1058 -#define raw_read(a)                     __raw_readw(a)
1059 +#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val)
1060 +#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val)
1061 +#define CHECK_NFC_RB    (raw_read(REG_NFC_RB) & NFC_RB)
1062
1063 -#define NFC_SET_BLS(val)               val
1064 +#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \
1065 +       raw_write((raw_read(NFC_CONFIG2) & \
1066 +       (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \
1067 +       NFC_NUM_ADDR_PHASE1_SHIFT))) | \
1068 +       ((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2);
1069
1070 -#define UNLOCK_ADDR(start_addr, end_addr) \
1071 +#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \
1072 +       raw_write((raw_read(NFC_CONFIG2) & \
1073 +       (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \
1074 +       NFC_NUM_ADDR_PHASE0_SHIFT))) | \
1075 +       ((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2);
1076 +
1077 +#define NFC_SET_NFC_ITERATION(val) \
1078 +       raw_write((raw_read(NFC_CONFIG1) & \
1079 +       (NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \
1080 +       ((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1);
1081 +
1082 +#define NFC_SET_FW(val) \
1083 +       raw_write((raw_read(NFC_CONFIG3) & \
1084 +       (NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \
1085 +       ((val) << NFC_FW_SHIFT), NFC_CONFIG3);
1086 +
1087 +#define NFC_SET_NUM_OF_DEVICE(val) \
1088 +       raw_write((raw_read(NFC_CONFIG3) & \
1089 +       (NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \
1090 +       NFC_NUM_OF_DEVICES_SHIFT))) | \
1091 +       ((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3);
1092 +
1093 +#define NFC_SET_ADD_OP_MODE(val) \
1094 +        raw_write((raw_read(NFC_CONFIG3) & \
1095 +       (NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \
1096 +       ((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3);
1097 +
1098 +#define NFC_SET_ADD_CS_MODE(val) \
1099  { \
1100 -       raw_write(start_addr, REG_START_BLKADDR); \
1101 -       raw_write(end_addr, REG_END_BLKADDR); \
1102 +       NFC_SET_ADD_OP_MODE(val); \
1103 +       NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \
1104  }
1105
1106 -#define NFC_SET_NFC_ACTIVE_CS(val)
1107 -#define NFC_SET_WPC(val)       val
1108 +#define NFC_SET_ST_CMD(val) \
1109 +       raw_write((raw_read(NFC_CONFIG2) & \
1110 +       (NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \
1111 +       NFC_ST_CMD_SHITF))) | \
1112 +       ((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2);
1113
1114 -/* NULL Definitions */
1115 -#define ACK_OPS
1116 -#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA);
1117 +#define NFMS_NF_DWIDTH 0
1118 +#define NFMS_NF_PG_SZ  1
1119 +#define NFC_CMD_1_SHIFT 8
1120 +
1121 +#define NUM_OF_ADDR_CYCLE ((ffs(~(info->page_mask)) - 1) >> 3)
1122 +
1123 +/*should set the fw,ps,spas,ppb*/
1124 +#define NFC_SET_NFMS(v)        \
1125 +do {   \
1126 +       NFC_SET_FW(NFC_FW_8);   \
1127 +       if (((v) & (1 << NFMS_NF_DWIDTH)))      \
1128 +               NFC_SET_FW(NFC_FW_16);  \
1129 +       if (((v) & (1 << NFMS_NF_PG_SZ))) {     \
1130 +               if (IS_2K_PAGE_NAND) {  \
1131 +                       NFC_SET_PS(NFC_PS_2K);  \
1132 +                       NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
1133 +                       NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
1134 +               } else if (IS_4K_PAGE_NAND) {       \
1135 +                       NFC_SET_PS(NFC_PS_4K);  \
1136 +                       NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
1137 +                       NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
1138 +               } else {        \
1139 +                       NFC_SET_PS(NFC_PS_512); \
1140 +                       NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \
1141 +                       NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \
1142 +               }       \
1143 +               NFC_SET_ADD_CS_MODE(1); \
1144 +               NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1);   \
1145 +               NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
1146 +               NFC_SET_ST_CMD(0x70); \
1147 +               raw_write(raw_read(NFC_CONFIG3) | 1 << 20, NFC_CONFIG3); \
1148 +       } \
1149 +} while (0)
1150
1151  #define READ_PAGE()    send_read_page(0)
1152  #define PROG_PAGE()    send_prog_page(0)
1153 -#define CHECK_NFC_RB            1
1154
1155  #endif                         /* __MXC_NAND_H__ */
1156 diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h
1157 index ae91982..7446c39 100644
1158 --- a/include/configs/mx51_3stack.h
1159 +++ b/include/configs/mx51_3stack.h
1160 @@ -58,7 +58,7 @@
1161  /*
1162   * Size of malloc() pool
1163   */
1164 -#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 512 * 1024)
1165 +#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
1166  /* size in bytes reserved for initial data */
1167  #define CONFIG_SYS_GBL_DATA_SIZE       128
1168
1169 @@ -83,7 +83,8 @@
1170  #define CONFIG_CMD_PING
1171  #define CONFIG_CMD_DHCP
1172  /* Enable below configure when supporting nand */
1173 -/* #define CONFIG_CMD_NAND */
1174 +#define CONFIG_CMD_NAND
1175 +#define CONFIG_CMD_ENV
1176  #undef CONFIG_CMD_IMLS
1177
1178  #define CONFIG_BOOTDELAY       3
1179 @@ -172,16 +173,15 @@
1180  /*-----------------------------------------------------------------------
1181   * NAND FLASH driver setup
1182   */
1183 -#define NAND_MAX_CHIPS         1
1184 +#define NAND_MAX_CHIPS         8
1185  #define CONFIG_SYS_MAX_NAND_DEVICE    1
1186  #define CONFIG_SYS_NAND_BASE          0x40000000
1187
1188  /* Monitor at beginning of flash */
1189 -#define CONFIG_ENV_IS_NOWHERE 1
1190 -#define CONFIG_ENV_SECT_SIZE   (128 * 1024)
1191 +#define CONFIG_ENV_IS_IN_NAND 1
1192 +#define CONFIG_ENV_SECT_SIZE   (1024 * 1024)
1193  #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
1194 -/* #define CFG_ENV_ADDR                (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) */
1195 -#define CONFIG_ENV_OFFSET              0x40000
1196 +#define CONFIG_ENV_OFFSET              0x100000
1197  /*
1198   * JFFS2 partitions
1199   */
1200 diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
1201 index 3e0044b..7d5196a 100644
1202 --- a/include/linux/mtd/nand.h
1203 +++ b/include/linux/mtd/nand.h
1204 @@ -50,8 +50,8 @@ extern void nand_wait_ready(struct mtd_info *mtd);
1205   * is supported now. If you add a chip with bigger oobsize/page
1206   * adjust this accordingly.
1207   */
1208 -#define NAND_MAX_OOBSIZE       218
1209 -#define NAND_MAX_PAGESIZE      4096
1210 +#define NAND_MAX_OOBSIZE       (218 * CONFIG_SYS_NAND_MAX_CHIPS)
1211 +#define NAND_MAX_PAGESIZE      (4096 * CONFIG_SYS_NAND_MAX_CHIPS)
1212
1213  /*
1214   * Constants for hardware specific CLE/ALE/NCE function
1215 --
1216 1.5.4.4
1217